ARM: OMAP2+: clock cleanup series for 3.17

PATCH New Tero Kristo 3 participants 17 messages Jul 2, 2014 – Jul 15, 2014

Subsystems (4)

Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP clock framework support

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Tero Kristo

author

2014-07-02 08:47 UTC #0 lore raw

cover ARM: OMAP2+: clock cleanup series for 3.17

Hi,

This sets cleans up some of the omap specific clock drivers still residing under arch/arm/mach-omap2. This set is done in preparation to migrate these drivers eventually under drivers/clk/ti, where we don't have access to certain board specific functionality. The basic idea of this set is to introduce clk_features struct which contains any SoC specific data / flags within it, and this is used runtime instead of the current cpu_is_? checks.

There are also a couple of bug fixes introduced in this set:
- Patch #1 : fix potential overflow in _dpll_test_fint
- Patch #8 : embeds a fix for checking omap5/dra7 for the bypass modes also

Set tested on following boards:

- omap2430-sdp : boot
- omap3-beagle : boot / suspend
- omap4-panda-es : boot / suspend
- omap5-uevm : boot
- dra7-evm : boot

Branch also available:

tree: https://github.com/t-kristo/linux-pm.git
branch: for-v3.17/omap2-clk-cleanup

-Tero

Tero Kristo

author

2014-07-02 08:47 UTC #1 lore raw

PATCH 1/13 ARM: OMAP2+: clock/dpll: fix _dpll_test_fint arithmetics overflow

The divider value provided to the _dpll_test_fint can reach value of 256 with J type DPLLs (USB etc.), which causes an overflow with the u8 datatype. Fix this by changing the parameter to be an int instead.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clkt_dpll.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/mach-omap2/clkt_dpll.c +1 -1

index 332af92..5aa734a 100644
@@ -76,7 +76,7 @@
  * (assuming that it is counting N upwards), or -2 if the enclosing loop
  * should skip to the next iteration (again assuming N is increasing).
  */
-static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
+static int _dpll_test_fint(struct clk_hw_omap *clk, int n)
 {
 	struct dpll_data *dd;
 	long fint, fint_min, fint_max;

Signature · 1 line

1.7.9.5

Paul Walmsley

maintainer Applied

2014-07-06 21:58 UTC #2 lore raw

PATCH 1/13 ARM: OMAP2+: clock/dpll: fix _dpll_test_fint arithmetics overflow

Quoted 25 lines · Tero Kristo

The divider value provided to the _dpll_test_fint can reach value of 256 with J type DPLLs (USB etc.), which causes an overflow with the u8 datatype. Fix this by changing the parameter to be an int instead.
Signed-off-by Tero Kristo <[email protected]>
---
 arch/arm/mach-omap2/clkt_dpll.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/mach-omap2/clkt_dpll.c +1 -1
index 332af92..5aa734a 100644
@@ -76,7 +76,7 @@
  * (assuming that it is counting N upwards), or -2 if the enclosing loop
  * should skip to the next iteration (again assuming N is increasing).
  */
-static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
+static int _dpll_test_fint(struct clk_hw_omap *clk, int n)
 {
 	struct dpll_data *dd;
 	long fint, fint_min, fint_max;
Signature · 1 line
1.7.9.5

Queued for v3.16-rc fixes, but I've changed the type of 'n' to be unsigned int rather than int, since a negative n is meaningless.

- Paul

Tero Kristo

author

2014-07-02 08:47 UTC #3 lore raw

PATCH 2/13 ARM: OMAP4+: clock: remove DEFINE_CLK_OMAP_HSDIVIDER macro

In reply to Tero Kristo

This clock type declaration is no longer used as all omap4+ SoC clock data has been moved to DT, thus remove it.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clock.h |   25 -------------------------
 1 file changed, 25 deletions(-)

arch/arm/mach-omap2/clock.h +0 ~~-25~~

index 12f54d4..e29f982 100644
@@ -101,31 +101,6 @@ struct clockdomain;
 	};							\
 	DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
 
-#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name,		\
-				_parent_ptr, _flags,		\
-				_clksel_reg, _clksel_mask)	\
-	static const struct clksel _name##_div[] = {		\
-		{						\
-			.parent = _parent_ptr,			\
-			.rates = div31_1to31_rates		\
-		},						\
-		{ .parent = NULL },				\
-	};							\
-	static struct clk _name;				\
-	static const char *_name##_parent_names[] = {		\
-		_parent_name,					\
-	};							\
-	static struct clk_hw_omap _name##_hw = {		\
-		.hw = {						\
-			.clk = &_name,				\
-		},						\
-		.clksel		= _name##_div,			\
-		.clksel_reg	= _clksel_reg,			\
-		.clksel_mask	= _clksel_mask,			\
-		.ops		= &clkhwops_omap4_dpllmx,	\
-	};							\
-	DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
-
 /* struct clksel_rate.flags possibilities */
 #define RATE_IN_242X		(1 << 0)
 #define RATE_IN_243X		(1 << 1)

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #4 lore raw

PATCH 3/13 ARM: OMAP4+: dpll: remove cpu_is_omap44xx checks

In reply to Tero Kristo

These are unnecessary, as the clock code is only used on OMAP4+ platforms through clock registrations. This also allows to eventually migrate the clock type implementation under clock driver.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/dpll44xx.c |    7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

arch/arm/mach-omap2/dpll44xx.c +3 -4

index 52f9438..b071891 100644
@@ -15,7 +15,6 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
 
-#include "soc.h"
 #include "clock.h"
 #include "clock44xx.h"
 #include "cm-regbits-44xx.h"

@@ -35,7 +34,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
 	u32 v;
 	u32 mask;
 
-	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+	if (!clk || !clk->clksel_reg)
 		return -EINVAL;
 
 	mask = clk->flags & CLOCK_CLKOUTX2 ?

@@ -54,7 +53,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
 	u32 v;
 	u32 mask;
 
-	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+	if (!clk || !clk->clksel_reg)
 		return;
 
 	mask = clk->flags & CLOCK_CLKOUTX2 ?

@@ -72,7 +71,7 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
 	u32 v;
 	u32 mask;
 
-	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+	if (!clk || !clk->clksel_reg)
 		return;
 
 	mask = clk->flags & CLOCK_CLKOUTX2 ?

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #5 lore raw

PATCH 4/13 ARM: OMAP4+: dpll44xx: remove cm-regbits-44xx.h and clock44xx.h includes

In reply to Tero Kristo

Instead, copy the used bitfield definitions to the source file. Done in preparation to migrate the clock implementation under clock driver.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/dpll44xx.c |   12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

arch/arm/mach-omap2/dpll44xx.c +10 -2

index b071891..4613f1e 100644
@@ -16,8 +16,6 @@
 #include <linux/bitops.h>
 
 #include "clock.h"
-#include "clock44xx.h"
-#include "cm-regbits-44xx.h"
 
 /*
  * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that

@@ -28,6 +26,16 @@
 #define OMAP4_DPLL_LP_FINT_MAX	1000000
 #define OMAP4_DPLL_LP_FOUT_MAX	100000000
 
+/*
+ * Bitfield declarations
+ */
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK		(1 << 8)
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK		(1 << 10)
+#define OMAP4430_DPLL_REGM4XEN_MASK			(1 << 11)
+
+/* Static rate multiplier for OMAP4 REGM4XEN clocks */
+#define OMAP4430_REGM4XEN_MULT				4
+
 /* Supported only on OMAP4 */
 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
 {

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #6 lore raw

PATCH 5/13 ARM: OMAP2+: clock: introduce ti_clk_features flags

In reply to Tero Kristo

This shall be used to replace the cpu type checks around the clock code. Actual bit values will be introduced in patches later.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clock.c |   14 ++++++++++++++
 arch/arm/mach-omap2/clock.h |   10 ++++++++++
 arch/arm/mach-omap2/io.c    |    2 ++
 3 files changed, 26 insertions(+)

arch/arm/mach-omap2/clock.c +14 -0

index 591581a..7897053 100644
@@ -47,6 +47,11 @@
 u16 cpu_mask;
 
 /*
+ * Clock features setup. Used instead of CPU type checks.
+ */
+struct ti_clk_features ti_clk_features;
+
+/*
  * clkdm_control: if true, then when a clock is enabled in the
  * hardware, its clockdomain will first be enabled; and when a clock
  * is disabled in the hardware, its clockdomain will be disabled

@@ -731,3 +736,12 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 		(clk_get_rate(core_ck) / 1000000),
 		(clk_get_rate(mpu_ck) / 1000000));
 }
+
+/**
+ * ti_clk_init_features - init clock features struct for the SoC
+ *
+ * Initializes the clock features struct based on the SoC type.
+ */
+void __init ti_clk_init_features(void)
+{
+}

arch/arm/mach-omap2/clock.h +10 -0

index e29f982..9b89cc0 100644
@@ -223,6 +223,14 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
 
 extern u16 cpu_mask;
 
+/*
+ * Clock features setup. Used instead of CPU type checks.
+ */
+struct ti_clk_features {
+	u32 flags;
+};
+extern struct ti_clk_features ti_clk_features;
+
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_dummy;
 extern const struct clkops clkops_omap2_dflt;

@@ -261,4 +269,6 @@ extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 
 extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
+
+void __init ti_clk_init_features(void);
 #endif

arch/arm/mach-omap2/io.c +2 -0

index 8f55945..1fae5c1 100644
@@ -728,6 +728,8 @@ int __init omap_clk_init(void)
 	if (!omap_clk_soc_init)
 		return 0;
 
+	ti_clk_init_features();
+
 	ret = of_prcm_init();
 	if (!ret)
 		ret = omap_clk_soc_init();

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #7 lore raw

PATCH 6/13 ARM: OMAP2+: clock: add fint values to the ti_clk_features struct

In reply to Tero Kristo

These are SoC specific and get their init values based on the SoC type. Previously the values were hard coded within the DPLL clock code, but having them inside the clock features avoids runtime cpu_is_X type checks.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clkt_dpll.c |   34 ++++++++++++----------------------
 arch/arm/mach-omap2/clock.c     |   23 +++++++++++++++++++++++
 arch/arm/mach-omap2/clock.h     |    4 ++++
 3 files changed, 39 insertions(+), 22 deletions(-)

arch/arm/mach-omap2/clkt_dpll.c +12 ~~-22~~

index 5aa734a..5207e84 100644
@@ -44,20 +44,12 @@
 #define DPLL_ROUNDING_VAL		((DPLL_SCALE_BASE / 2) * \
 					 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
 
-/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
-#define OMAP3430_DPLL_FINT_BAND1_MIN	750000
-#define OMAP3430_DPLL_FINT_BAND1_MAX	2100000
-#define OMAP3430_DPLL_FINT_BAND2_MIN	7500000
-#define OMAP3430_DPLL_FINT_BAND2_MAX	21000000
-
 /*
  * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
  * From device data manual section 4.3 "DPLL and DLL Specifications".
  */
 #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN	500000
 #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX	2500000
-#define OMAP3PLUS_DPLL_FINT_MIN		32000
-#define OMAP3PLUS_DPLL_FINT_MAX		52000000
 
 /* _dpll_test_fint() return codes */
 #define DPLL_FINT_UNDERFLOW		-1

@@ -87,33 +79,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, int n)
 	/* DPLL divider must result in a valid jitter correction val */
 	fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
 
-	if (cpu_is_omap24xx()) {
-		/* Should not be called for OMAP2, so warn if it is called */
-		WARN(1, "No fint limits available for OMAP2!\n");
-		return DPLL_FINT_INVALID;
-	} else if (cpu_is_omap3430()) {
-		fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
-		fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
-	} else if (dd->flags & DPLL_J_TYPE) {
+	if (dd->flags & DPLL_J_TYPE) {
 		fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
 		fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
 	} else {
-		fint_min = OMAP3PLUS_DPLL_FINT_MIN;
-		fint_max = OMAP3PLUS_DPLL_FINT_MAX;
+		fint_min = ti_clk_features.fint_min;
+		fint_max = ti_clk_features.fint_max;
+	}
+
+	if (!fint_min || !fint_max) {
+		WARN(1, "No fint limits available!\n");
+		return DPLL_FINT_INVALID;
 	}
 
-	if (fint < fint_min) {
+	if (fint < ti_clk_features.fint_min) {
 		pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
 			 n);
 		dd->max_divider = n;
 		ret = DPLL_FINT_UNDERFLOW;
-	} else if (fint > fint_max) {
+	} else if (fint > ti_clk_features.fint_max) {
 		pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
 			 n);
 		dd->min_divider = n;
 		ret = DPLL_FINT_INVALID;
-	} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
-		   fint < OMAP3430_DPLL_FINT_BAND2_MIN) {
+	} else if (fint > ti_clk_features.fint_band1_max &&
+		   fint < ti_clk_features.fint_band2_min) {
 		pr_debug("rejecting n=%d due to Fint failure\n", n);
 		ret = DPLL_FINT_INVALID;
 	}

arch/arm/mach-omap2/clock.c +23 -0

index 7897053..7efe66e 100644
@@ -51,6 +51,19 @@ u16 cpu_mask;
  */
 struct ti_clk_features ti_clk_features;
 
+/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
+#define OMAP3430_DPLL_FINT_BAND1_MIN	750000
+#define OMAP3430_DPLL_FINT_BAND1_MAX	2100000
+#define OMAP3430_DPLL_FINT_BAND2_MIN	7500000
+#define OMAP3430_DPLL_FINT_BAND2_MAX	21000000
+
+/*
+ * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
+ * From device data manual section 4.3 "DPLL and DLL Specifications".
+ */
+#define OMAP3PLUS_DPLL_FINT_MIN		32000
+#define OMAP3PLUS_DPLL_FINT_MAX		52000000
+
 /*
  * clkdm_control: if true, then when a clock is enabled in the
  * hardware, its clockdomain will first be enabled; and when a clock

@@ -744,4 +757,14 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
  */
 void __init ti_clk_init_features(void)
 {
+	/* Fint setup for DPLLs */
+	if (cpu_is_omap3430()) {
+		ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
+		ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
+		ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
+		ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
+	} else {
+		ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
+		ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
+	}
 }

arch/arm/mach-omap2/clock.h +4 -0

index 9b89cc0..02aa2e3 100644
@@ -228,6 +228,10 @@ extern u16 cpu_mask;
  */
 struct ti_clk_features {
 	u32 flags;
+	long fint_min;
+	long fint_max;
+	long fint_band1_max;
+	long fint_band2_min;
 };
 extern struct ti_clk_features ti_clk_features;

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #8 lore raw

PATCH 7/13 ARM: OMAP2+: clock/dpll: add private API for checking if DPLL is in bypass

In reply to Tero Kristo

Currently, same functionality is copy pasted in two locations. Instead, add a private API for this and get rid of some duplicated code.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clkt_dpll.c |   60 +++++++++++++++++++++------------------
 1 file changed, 32 insertions(+), 28 deletions(-)

arch/arm/mach-omap2/clkt_dpll.c +32 ~~-28~~

index 5207e84..f1b052a 100644
@@ -175,6 +175,33 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
 	return r;
 }
 
+/**
+ * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
+ * @v: bitfield value of the DPLL enable
+ *
+ * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
+ * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
+ */
+static int _omap2_dpll_is_in_bypass(u32 v)
+{
+	if (cpu_is_omap24xx()) {
+		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
+			return 1;
+	} else if (cpu_is_omap34xx()) {
+		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
+			return 1;
+	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
+		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
+		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+			return 1;
+	}
+
+	return 0;
+}
+
 /* Public functions */
 u8 omap2_init_dpll_parent(struct clk_hw *hw)
 {

@@ -191,20 +218,9 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
 	v >>= __ffs(dd->enable_mask);
 
 	/* Reparent the struct clk in case the dpll is in bypass */
-	if (cpu_is_omap24xx()) {
-		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
-		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-			return 1;
-	} else if (cpu_is_omap34xx()) {
-		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
-		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-			return 1;
-	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
-		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
-		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-			return 1;
-	}
+	if (_omap2_dpll_is_in_bypass(v))
+		return 1;
+
 	return 0;
 }

@@ -237,20 +253,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
 	v &= dd->enable_mask;
 	v >>= __ffs(dd->enable_mask);
 
-	if (cpu_is_omap24xx()) {
-		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
-		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-			return __clk_get_rate(dd->clk_bypass);
-	} else if (cpu_is_omap34xx()) {
-		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
-		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-			return __clk_get_rate(dd->clk_bypass);
-	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
-		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
-		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-			return __clk_get_rate(dd->clk_bypass);
-	}
+	if (_omap2_dpll_is_in_bypass(v))
+		return __clk_get_rate(dd->clk_bypass);
 
 	v = omap2_clk_readl(clk, dd->mult_div1_reg);
 	dpll_mult = v & dd->mult_mask;

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #9 lore raw

PATCH 8/13 ARM: OMAP2+: clock/dpll: convert bypass check to use clk_features

In reply to Tero Kristo

OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses clk_features data provided during boot. This avoids the need to use cpu_is_X type checks runtime, and allows us to eventually move the clock code under the clock driver.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clkt_dpll.c |   25 +++++++++++++------------
 arch/arm/mach-omap2/clock.c     |   17 +++++++++++++++++
 arch/arm/mach-omap2/clock.h     |    1 +
 3 files changed, 31 insertions(+), 12 deletions(-)

arch/arm/mach-omap2/clkt_dpll.c +13 ~~-12~~

index f1b052a..51f995a 100644
@@ -184,18 +184,19 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
  */
 static int _omap2_dpll_is_in_bypass(u32 v)
 {
-	if (cpu_is_omap24xx()) {
-		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
-		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-			return 1;
-	} else if (cpu_is_omap34xx()) {
-		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
-		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-			return 1;
-	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
-		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
-		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+	u8 mask, val;
+
+	mask = ti_clk_features.dpll_bypass_vals;
+
+	/*
+	 * Each set bit in the mask corresponds to a bypass value equal
+	 * to the bitshift. Go through each set-bit in the mask and
+	 * compare against the given register value.
+	 */
+	while (mask) {
+		val = __ffs(mask);
+		mask ^= (1 << val);
+		if (v == val)
 			return 1;
 	}

arch/arm/mach-omap2/clock.c +17 -0

index 7efe66e..e438437 100644
@@ -767,4 +767,21 @@ void __init ti_clk_init_features(void)
 		ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
 		ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
 	}
+
+	/* Bypass value setup for DPLLs */
+	if (cpu_is_omap24xx()) {
+		ti_clk_features.dpll_bypass_vals |=
+			(1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
+			(1 << OMAP2XXX_EN_DPLL_FRBYPASS);
+	} else if (cpu_is_omap34xx()) {
+		ti_clk_features.dpll_bypass_vals |=
+			(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
+			(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
+	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
+		   soc_is_omap54xx() || soc_is_dra7xx()) {
+		ti_clk_features.dpll_bypass_vals |=
+			(1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
+			(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
+			(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
+	}
 }

arch/arm/mach-omap2/clock.h +1 -0

index 02aa2e3..7b2b099 100644
@@ -232,6 +232,7 @@ struct ti_clk_features {
 	long fint_max;
 	long fint_band1_max;
 	long fint_band2_min;
+	u8 dpll_bypass_vals;
 };
 extern struct ti_clk_features ti_clk_features;

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #10 lore raw

PATCH 9/13 ARM: OMAP2+: clock/dpll: add jitter correction behind clk_features

In reply to Tero Kristo

Currently DPLL code uses runtime cpu_is_343x checks to see if the DPLL has freqsel fields in its control register or not. Instead, add a new flag to the clk_features.flags and use this during runtime. Allows eventual move of the DPLL code under clock driver.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clock.c    |    4 ++++
 arch/arm/mach-omap2/clock.h    |    3 +++
 arch/arm/mach-omap2/dpll3xxx.c |    4 ++--
 3 files changed, 9 insertions(+), 2 deletions(-)

arch/arm/mach-omap2/clock.c +4 -0

index e438437..23b5f05 100644
@@ -784,4 +784,8 @@ void __init ti_clk_init_features(void)
 			(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
 			(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
 	}
+
+	/* Jitter correction only available on OMAP343X */
+	if (cpu_is_omap343x())
+		ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
 }

arch/arm/mach-omap2/clock.h +3 -0

index 7b2b099..d3ef147 100644
@@ -234,6 +234,9 @@ struct ti_clk_features {
 	long fint_band2_min;
 	u8 dpll_bypass_vals;
 };
+
+#define TI_CLK_DPLL_HAS_FREQSEL		(1 << 0)
+
 extern struct ti_clk_features ti_clk_features;
 
 extern const struct clkops clkops_omap2_dflt_wait;

arch/arm/mach-omap2/dpll3xxx.c +2 -2

index 6d7ba37..12ad0f5 100644
@@ -310,7 +310,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 	 * Set jitter correction. Jitter correction applicable for OMAP343X
 	 * only since freqsel field is no longer present on other devices.
 	 */
-	if (cpu_is_omap343x()) {
+	if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
 		v = omap2_clk_readl(clk, dd->control_reg);
 		v &= ~dd->freqsel_mask;
 		v |= freqsel << __ffs(dd->freqsel_mask);

@@ -512,7 +512,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 			return -EINVAL;
 
 		/* Freqsel is available only on OMAP343X devices */
-		if (cpu_is_omap343x()) {
+		if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
 			freqsel = _omap3_dpll_compute_freqsel(clk,
 						dd->last_rounded_n);
 			WARN_ON(!freqsel);

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #11 lore raw

PATCH 10/13 ARM: OMAP2+: clock/interface: add a clk_features definition for idlest value

In reply to Tero Kristo

Helps to get rid of some runtime cpu_is_x checks. This also allows eventual migration of the code under clock driver.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clock.c |   18 +++++++++++-------
 arch/arm/mach-omap2/clock.h |    1 +
 2 files changed, 12 insertions(+), 7 deletions(-)

arch/arm/mach-omap2/clock.c +11 -7

index 23b5f05..5a0cac9 100644
@@ -305,13 +305,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 	 * 34xx reverses this, just to keep us on our toes
 	 * AM35xx uses both, depending on the module.
 	 */
-	if (cpu_is_omap24xx())
-		*idlest_val = OMAP24XX_CM_IDLEST_VAL;
-	else if (cpu_is_omap34xx())
-		*idlest_val = OMAP34XX_CM_IDLEST_VAL;
-	else
-		BUG();
-
+	*idlest_val = ti_clk_features.cm_idlest_val;
 }
 
 /**

@@ -788,4 +782,14 @@ void __init ti_clk_init_features(void)
 	/* Jitter correction only available on OMAP343X */
 	if (cpu_is_omap343x())
 		ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
+
+	/* Idlest value for interface clocks.
+	 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+	 * 34xx reverses this, just to keep us on our toes
+	 * AM35xx uses both, depending on the module.
+	 */
+	if (cpu_is_omap24xx())
+		ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
+	else if (cpu_is_omap34xx())
+		ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
 }

arch/arm/mach-omap2/clock.h +1 -0

index d3ef147..0f100dc 100644
@@ -233,6 +233,7 @@ struct ti_clk_features {
 	long fint_band1_max;
 	long fint_band2_min;
 	u8 dpll_bypass_vals;
+	u8 cm_idlest_val;
 };
 
 #define TI_CLK_DPLL_HAS_FREQSEL		(1 << 0)

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #12 lore raw

PATCH 11/13 ARM: OMAP2+: clock/dpll: remove unused header includes from clkt_dpll.c

In reply to Tero Kristo

Some of the machine specific header includes are no longer used, so remove these from the source file. This allows migration of the file under clock driver.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clkt_dpll.c |    3 ---
 1 file changed, 3 deletions(-)

arch/arm/mach-omap2/clkt_dpll.c +0 -3

index 51f995a..cdc3674 100644
@@ -21,10 +21,7 @@
 
 #include <asm/div64.h>
 
-#include "soc.h"
 #include "clock.h"
-#include "cm-regbits-24xx.h"
-#include "cm-regbits-34xx.h"
 
 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
 #define DPLL_MIN_MULTIPLIER		2

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #13 lore raw

PATCH 12/13 ARM: OMAP2+: clock/dpll: remove unused header includes from dpll3xxx.c

In reply to Tero Kristo

Some of the machine specific header includes are no longer used, so remove these from the source file. This allows migration of the file under clock driver.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/dpll3xxx.c |    3 ---
 1 file changed, 3 deletions(-)

arch/arm/mach-omap2/dpll3xxx.c +0 -3

index 12ad0f5..cd5f3a0 100644
@@ -28,11 +28,8 @@
 #include <linux/bitops.h>
 #include <linux/clkdev.h>
 
-#include "soc.h"
 #include "clockdomain.h"
 #include "clock.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-34xx.h"
 
 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
 #define DPLL_AUTOIDLE_DISABLE			0x0

Signature · 1 line

1.7.9.5

Tero Kristo

author

2014-07-02 08:47 UTC #14 lore raw

PATCH 13/13 ARM: OMAP2+: clock/interface: remove some headers from clkt_iclk.c file

In reply to Tero Kristo

Instead, copy the used constants from the header file to the source file. This allows the code to be migrated under drivers folder where we don't have access to the OMAP specific header files.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/clkt_iclk.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

arch/arm/mach-omap2/clkt_iclk.c +4 -4

index 333f0a6..55eb579 100644
@@ -14,11 +14,11 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 
-
 #include "clock.h"
-#include "clock2xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
+
+/* Register offsets */
+#define CM_AUTOIDLE			0x30
+#define CM_ICLKEN			0x10
 
 /* Private functions */

Signature · 1 line

1.7.9.5

Mike Turquette

2014-07-13 13:53 UTC #15 lore raw

cover ARM: OMAP2+: clock cleanup series for 3.17

In reply to Tero Kristo

Quoting Tero Kristo (2014-07-02 01:47:34)

Quoted 8 lines

Hi,
This sets cleans up some of the omap specific clock drivers still residing under arch/arm/mach-omap2. This set is done in preparation to migrate these drivers eventually under drivers/clk/ti, where we don't have access to certain board specific functionality. The basic idea of this set is to introduce clk_features struct which contains any SoC specific data / flags within it, and this is used runtime instead of the current cpu_is_? checks.

Reviewed-by Mike Turquette <[email protected]>

Quoted 20 lines

There are also a couple of bug fixes introduced in this set:
- Patch #1 : fix potential overflow in _dpll_test_fint
- Patch #8 : embeds a fix for checking omap5/dra7 for the bypass modes also
Set tested on following boards:
- omap2430-sdp : boot
- omap3-beagle : boot / suspend
- omap4-panda-es : boot / suspend
- omap5-uevm : boot
- dra7-evm : boot
Branch also available:
tree: https://github.com/t-kristo/linux-pm.git
branch: for-v3.17/omap2-clk-cleanup
-Tero

Paul Walmsley

maintainer

2014-07-15 20:11 UTC #16 lore raw

cover ARM: OMAP2+: clock cleanup series for 3.17

Quoted 11 lines · Mike Turquette

Quoting Tero Kristo (2014-07-02 01:47:34)
Quoted 8 lines
Hi,
This sets cleans up some of the omap specific clock drivers still residing under arch/arm/mach-omap2. This set is done in preparation to migrate these drivers eventually under drivers/clk/ti, where we don't have access to certain board specific functionality. The basic idea of this set is to introduce clk_features struct which contains any SoC specific data / flags within it, and this is used runtime instead of the current cpu_is_? checks.
Reviewed-by Mike Turquette <[email protected]>

Thanks, queued for 3.17 with the exception of patch 1 which was previously queued.

- Paul