socfpga: initialize designware ethernet

PATCH New Pavel Machek 3 participants 10 messages Jul 11, 2014 – Aug 30, 2014 Arm (32-bit)

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Pavel Machek

author

2014-07-11 09:45 UTC #0 lore raw

PATCH 1/1 socfpga: initialize designware ethernet

Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment.

Signed-off-by Pavel Machek <[email protected]>

arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +2 -0

index f564046..a6d1680 100644
@@ -14,5 +14,7 @@
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_EMAC0_ADDRESS 0xff700000
+#define SOCFPGA_EMAC1_ADDRESS 0xff702000
 
 #endif /* _SOCFPGA_BASE_ADDRS_H_ */

board/altera/socfpga/socfpga_cyclone5.c +8 -1

index a960eb6..2214ab7 100644
@@ -1,5 +1,6 @@
 /*
  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2014 Pavel Machek, pavel at denx.de
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -7,7 +8,7 @@
 #include <common.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/io.h>
-
+#include <miiphy.h>
 #include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -67,5 +68,11 @@ int overwrite_console(void)
 /* We know all the init functions have been run now */
 int board_eth_init(bd_t *bis)
 {
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+       /* initialize and register the emac */
+	int rval = designware_initialize(CONFIG_EMAC_BASE, CONFIG_PHY_INTERFACE_MODE);
+	return rval;
+#else
 	return 0;
+#endif
 }

include/configs/socfpga_cyclone5.h +32 -0

index 0254249..c9c8e53 100644
@@ -206,6 +209,38 @@
 #define CONFIG_ENV_IS_NOWHERE
 
 /*
+ * network support
+ */
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_DESIGNWARE_ETH          1
+#endif
+
+#ifdef CONFIG_DESIGNWARE_ETH
+#define CONFIG_EMAC0_BASE              SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_EMAC1_BASE              SOCFPGA_EMAC1_ADDRESS
+/* console support for network */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+/* designware */
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+#define CONFIG_DW_AUTONEG
+#define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+/* EMAC controller and PHY used */
+#define CONFIG_EMAC_BASE               CONFIG_EMAC1_BASE
+#define CONFIG_EPHY_PHY_ADDR           CONFIG_EPHY1_PHY_ADDR
+#define CONFIG_PHY_INTERFACE_MODE      PHY_INTERFACE_MODE_RGMII
+#endif /* CONFIG_DESIGNWARE_ETH */
+
+/*
  * SPL "Second Program Loader" aka Initial Software
  */

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Marek Vasut

2014-07-11 09:49 UTC #1 lore raw

PATCH 1/1 socfpga: initialize designware ethernet

On Friday, July 11, 2014 at 11:45:56 AM, Pavel Machek wrote:
[...]

board/altera/socfpga/socfpga_cyclone5.c line 3

Quoted 8 lines

(quoted diff) +0 -0
b/board/altera/socfpga/socfpga_cyclone5.c index a960eb6..2214ab7 100644
board/altera/socfpga/socfpga_cyclone5.c +1 -0
@@ -1,5 +1,6 @@
 /*
  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2014 Pavel Machek, pavel at denx.de

NAK ;-) Can you please keep the email address in this extremely relevant comment in the same format as above (in the <> chars) .

Quoted 14 lines

board/altera/socfpga/socfpga_cyclone5.c +1 -1

  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -7,7 +8,7 @@
 #include <common.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/io.h>
-
+#include <miiphy.h>
 #include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -67,5 +68,11 @@ int overwrite_console(void)
 /* We know all the init functions have been run now */

board/altera/socfpga/socfpga_cyclone5.c int overwrite_console(void) · line 78

Quoted 10 lines

board/altera/socfpga/socfpga_cyclone5.c +5 -0

 int board_eth_init(bd_t *bis)
 {
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+       /* initialize and register the emac */
+	int rval = designware_initialize(CONFIG_EMAC_BASE,
 CONFIG_PHY_INTERFACE_MODE); +	return rval;
+#else
 	return 0;
+#endif
 }

Can this all not go into cpu_eth_init() and into arch/arm/... instead ?

[...]

Best regards,
Marek Vasut

Pavel Machek

author

2014-07-11 10:40 UTC #2 lore raw

PATCH 1/1 socfpga: initialize designware ethernet

Quoted 13 lines · Marek Vasut

On Friday, July 11, 2014 at 11:45:56 AM, Pavel Machek wrote:
[...]
board/altera/socfpga/socfpga_cyclone5.c line 3
Quoted 8 lines
(quoted diff) +0 -0
b/board/altera/socfpga/socfpga_cyclone5.c index a960eb6..2214ab7 100644
board/altera/socfpga/socfpga_cyclone5.c +1 -0
@@ -1,5 +1,6 @@
 /*
  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2014 Pavel Machek, pavel at denx.de
NAK ;-) Can you please keep the email address in this extremely relevant comment in the same format as above (in the <> chars) .

Umm, note that above is web address and mine is email address :-).

Quoted 6 lines

board/altera/socfpga/socfpga_cyclone5.c +2 -0

@@ -67,5 +68,11 @@ int overwrite_console(void)
 /* We know all the init functions have been run now */
 int board_eth_init(bd_t *bis)
 {
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+       /* initialize and register the emac */

Quoted 8 lines

board/altera/socfpga/socfpga_cyclone5.c int overwrite_console(void)
Quoted 6 lines
board/altera/socfpga/socfpga_cyclone5.c +3 -0
+	int rval = designware_initialize(CONFIG_EMAC_BASE,
 CONFIG_PHY_INTERFACE_MODE); +	return rval;
+#else
 	return 0;
+#endif
 }
Can this all not go into cpu_eth_init() and into arch/arm/... instead ?

No idea. When I move it to arch/arm/, like this, it still works, so I guess it can be moved.

Should I prepare new patch?
Pavel

arch/arm/cpu/armv7/socfpga/misc.c +18 -0

index 2f1c716..6c64f28 100644
@@ -6,6 +6,8 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -14,3 +16,19 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
+
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+       /* initialize and register the emac */
+	return designware_initialize(CONFIG_EMAC_BASE,
+				     CONFIG_PHY_INTERFACE_MODE);
+#else
+	return 0;
+#endif
+}

board/altera/socfpga/socfpga_cyclone5.c +0 ~~-17~~

index 2214ab7..5cbe695 100644
@@ -8,8 +8,6 @@
 #include <common.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/io.h>
-#include <miiphy.h>
-#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -61,18 +59,3 @@ int overwrite_console(void)
 	return 0;
 }
 #endif
-
-/*
- * DesignWare Ethernet initialization
- */
-/* We know all the init functions have been run now */
-int board_eth_init(bd_t *bis)
-{
-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
-       /* initialize and register the emac */
-	int rval = designware_initialize(CONFIG_EMAC_BASE, CONFIG_PHY_INTERFACE_MODE);
-	return rval;
-#else
-	return 0;
-#endif
-}

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Marek Vasut

2014-07-11 10:44 UTC #3 lore raw

PATCH 1/1 socfpga: initialize designware ethernet

On Friday, July 11, 2014 at 12:40:06 PM, Pavel Machek wrote:

[...]

Quoted 8 lines

Quoted 6 lines
Quoted 3 lines
* Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014 Pavel Machek, pavel at denx.de
NAK ;-) Can you please keep the email address in this extremely relevant comment in the same format as above (in the <> chars) .
Umm, note that above is web address and mine is email address :-).

It still seems the email addresses are in those <> signs quite often ;-).

Quoted 17 lines

Quoted 17 lines
Quoted 17 lines
(quoted diff) +1 -0
@@ -67,5 +68,11 @@ int overwrite_console(void)
 
 /* We know all the init functions have been run now */
 int board_eth_init(bd_t *bis)
 {
 
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) &&
!defined(CONFIG_SPL_BUILD) + /* initialize and register the emac
*/
(quoted diff) +1 -0
+	int rval = designware_initialize(CONFIG_EMAC_BASE,
CONFIG_PHY_INTERFACE_MODE); + return rval;
(quoted diff) +2 -0
+#else
 
 	return 0;
 
+#endif

Quoted 8 lines

Quoted 3 lines
Quoted 1 line
}
Can this all not go into cpu_eth_init() and into arch/arm/... instead ?
No idea. When I move it to arch/arm/, like this, it still works, so I guess it can be moved.
Should I prepare new patch?

Yes please, but I can only give you a general guidance, I'm no socfpga expert.

Best regards,
Marek Vasut

Pavel Machek

author

2014-07-13 08:06 UTC #4 lore raw

PATCH v2 1/1 socfpga: initialize designware ethernet

In reply to Pavel Machek

Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment.

Signed-off-by Pavel Machek <[email protected]>

---

Changes from v1: moved ethernet initialization to arch/arm, as suggested by Marek.

arch/arm/cpu/armv7/socfpga/misc.c +18 -0

index 2f1c716..6c64f28 100644
@@ -6,6 +6,8 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -14,3 +16,19 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
+
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+       /* initialize and register the emac */
+	return designware_initialize(CONFIG_EMAC_BASE,
+				     CONFIG_PHY_INTERFACE_MODE);
+#else
+	return 0;
+#endif
+}

arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +2 -0

index f564046..a6d1680 100644
@@ -14,5 +14,7 @@
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_EMAC0_ADDRESS 0xff700000
+#define SOCFPGA_EMAC1_ADDRESS 0xff702000
 
 #endif /* _SOCFPGA_BASE_ADDRS_H_ */

board/altera/socfpga/socfpga_cyclone5.c +0 ~~-11~~

index a960eb6..5cbe695 100644
@@ -8,8 +9,6 @@
 #include <asm/arch/reset_manager.h>
 #include <asm/io.h>
 
-#include <netdev.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_DISPLAY_CPUINFO)

@@ -60,12 +59,3 @@ int overwrite_console(void)
 	return 0;
 }
 #endif
-
-/*
- * DesignWare Ethernet initialization
- */
-/* We know all the init functions have been run now */
-int board_eth_init(bd_t *bis)
-{
-	return 0;
-}

include/configs/socfpga_cyclone5.h +32 -0

index 0254249..c9c8e53 100644
@@ -206,6 +209,38 @@
 #define CONFIG_ENV_IS_NOWHERE
 
 /*
+ * network support
+ */
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_DESIGNWARE_ETH          1
+#endif
+
+#ifdef CONFIG_DESIGNWARE_ETH
+#define CONFIG_EMAC0_BASE              SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_EMAC1_BASE              SOCFPGA_EMAC1_ADDRESS
+/* console support for network */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+/* designware */
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+#define CONFIG_DW_AUTONEG
+#define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+/* EMAC controller and PHY used */
+#define CONFIG_EMAC_BASE               CONFIG_EMAC1_BASE
+#define CONFIG_EPHY_PHY_ADDR           CONFIG_EPHY1_PHY_ADDR
+#define CONFIG_PHY_INTERFACE_MODE      PHY_INTERFACE_MODE_RGMII
+#endif /* CONFIG_DESIGNWARE_ETH */
+
+/*
  * SPL "Second Program Loader" aka Initial Software
  */

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Marek Vasut

2014-07-13 13:30 UTC #5 lore raw

PATCH v2 1/1 socfpga: initialize designware ethernet

On Sunday, July 13, 2014 at 10:06:50 AM, Pavel Machek wrote:
[...]

arch/arm/cpu/armv7/socfpga/misc.c int dram_init(void) · line 25

Quoted 11 lines

arch/arm/cpu/armv7/socfpga/misc.c +7 -0

@@ -14,3 +16,19 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
+
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)

This would be cpu_eth_init()

arch/arm/cpu/armv7/socfpga/misc.c int dram_init(void) · line 34

Quoted 9 lines

arch/arm/cpu/armv7/socfpga/misc.c +9 -0

+{
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+       /* initialize and register the emac */
+	return designware_initialize(CONFIG_EMAC_BASE,
+				     CONFIG_PHY_INTERFACE_MODE);
+#else
+	return 0;
+#endif
+}

[...]
Best regards,
Marek Vasut

Pavel Machek

author

2014-07-14 12:14 UTC #6 lore raw

PATCH v3 1/1 socfpga: initialize designware ethernet

In reply to Pavel Machek

Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment.

Signed-off-by Pavel Machek <[email protected]>

---

Changes from v1: moved ethernet initialization to arch/arm, as suggested by Marek.

Changes from v2: use right function name after moving to arch/arm. Thanks to Marek.

Patch hand-edited so that it can be applied after the "timer counts down" fix.

arch/arm/cpu/armv7/socfpga/misc.c +17 -0

index 2f1c716..bb71c91 100644
@@ -6,6 +6,8 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -14,3 +16,18 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
+
+
+/*
+ * DesignWare Ethernet initialization
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
+       /* initialize and register the emac */
+	return designware_initialize(CONFIG_EMAC_BASE,
+				     CONFIG_PHY_INTERFACE_MODE);
+#else
+	return 0;
+#endif
+}

arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +2 -0

index f564046..a6d1680 100644
@@ -14,5 +14,7 @@
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_EMAC0_ADDRESS 0xff700000
+#define SOCFPGA_EMAC1_ADDRESS 0xff702000
 
 #endif /* _SOCFPGA_BASE_ADDRS_H_ */

board/altera/socfpga/socfpga_cyclone5.c +0 -9

index a960eb6..5cbe695 100644
@@ -60,12 +59,3 @@ int overwrite_console(void)
 	return 0;
 }
 #endif
-
-/*
- * DesignWare Ethernet initialization
- */
-/* We know all the init functions have been run now */
-int board_eth_init(bd_t *bis)
-{
-	return 0;
-}

include/configs/socfpga_cyclone5.h +32 -0

index 0254249..cc4f690 100644
@@ -201,12 +204,44 @@
 #else
 #define CONFIG_SYS_TIMER_RATE		25000000
 #endif
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
 
 #define CONFIG_ENV_IS_NOWHERE
 
 /*
+ * network support
+ */
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_DESIGNWARE_ETH          1
+#endif
+
+#ifdef CONFIG_DESIGNWARE_ETH
+#define CONFIG_EMAC0_BASE              SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_EMAC1_BASE              SOCFPGA_EMAC1_ADDRESS
+/* console support for network */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+/* designware */
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+#define CONFIG_DW_AUTONEG
+#define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+/* EMAC controller and PHY used */
+#define CONFIG_EMAC_BASE               CONFIG_EMAC1_BASE
+#define CONFIG_EPHY_PHY_ADDR           CONFIG_EPHY1_PHY_ADDR
+#define CONFIG_PHY_INTERFACE_MODE      PHY_INTERFACE_MODE_RGMII
+#endif /* CONFIG_DESIGNWARE_ETH */
+
+/*
  * SPL "Second Program Loader" aka Initial Software
  */

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Marek Vasut

2014-07-14 12:28 UTC #7 lore raw

PATCH v3 1/1 socfpga: initialize designware ethernet

Quoted 7 lines · Pavel Machek

Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment.
Signed-off-by Pavel Machek <[email protected]>
---

btw. is there any reason why the patch is missing a diffstat ?

Best regards,
Marek Vasut

Pavel Machek

author

2014-07-14 12:38 UTC #8 lore raw

PATCH v3 1/1 socfpga: initialize designware ethernet

Quoted 10 lines · Marek Vasut

Quoted 7 lines · Pavel Machek
Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment.
Signed-off-by Pavel Machek <[email protected]>
---
btw. is there any reason why the patch is missing a diffstat ?

I had to hand-edit the patch to make it fit after the time fixes...

(Plus, I don't normally do diffstats as they are not required for kernel submissions.)

Pavel

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Tom Rini

2014-08-30 15:13 UTC #9 lore raw

PATCH v3 1/1 socfpga: initialize designware ethernet

In reply to Pavel Machek

Quoted 5 lines · Pavel Machek

Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment.
Signed-off-by Pavel Machek <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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