OMAP Mailbox DT node/hwmod cleanup
Subsystems (5)
v2 cover OMAP Mailbox DT node/hwmod cleanup
Hi Tony,
This is a refresh of the OMAP Mailbox DT node/hwmod cleanup series [1], addressing the review comments [2] from Pavel Machek about the Mailbox IP design parameters. The changes are limited to only the DTS patches, and mainly bring back the DT properties that were dropped in the previous series. The hwmod patches in the series are identical to v1 (I added the Acked-by responses from Paul Walmsley on 2 patches). I will refresh the OMAP Mailbox framework adoption and DT conversion series [3] as well, which builds on top of this cleanup series.
Changes in v2:
- Add a new patch that adds the new DT properties: ti,mbox-num-users and ti,mbox-num-fifos to existing DT nodes as of 3.16-rc2
- Updated the other DTS patches from v1 to include the new DT properties
- Updated the compatible properties on AM33xx and DRA7 to use the same compatible string as OMAP4.
The following shows the boot logs on various OMAP platforms with just these patches on top of 3.16-rc2:
OMAP3 (BeagleXM) : http://slexy.org/view/s21MEzZ4bU OMAP4 (PandaBoard) : http://slexy.org/view/s2S5sxIjYw OMAP5 (OMAP5 uEVM) : http://slexy.org/view/s21siI3Vi2 DRA7 (DRA7 EVM) : http://slexy.org/view/s21RVgqBeT
AM33xx (BeagleBone Black) : http://slexy.org/view/s20fcQqcOd
AM43xx (AM437x GP EVM) : http://slexy.org/view/s2k3GzeZK1
[1] http://marc.info/?l=linux-omap&m=140365833121612&w=2
[2] https://patchwork.kernel.org/patch/4415881/
[3] http://marc.info/?l=linux-omap&m=140366093024233&w=2
Suman Anna (10):
ARM: dts: OMAP2+: Add mailbox fifo and user information
ARM: dts: OMAP4: Add mailbox node
ARM: dts: AM33xx: Add mailbox node
ARM: dts: AM4372: Correct mailbox node data
ARM: dts: DRA7: Add mailbox nodes
ARM: DRA7: hwmod_data: Add mailbox hwmod data
ARM: OMAP2+: Avoid mailbox legacy device creation for DT-boot
ARM: OMAP2: hwmod_data: Remove legacy mailbox data and addrs
ARM: OMAP4: hwmod_data: Remove legacy mailbox addrs
ARM: AM33xx: hwmod_data: Remove legacy mailbox addrs
arch/arm/boot/dts/am33xx.dtsi | 9 + arch/arm/boot/dts/am4372.dtsi | 3 - arch/arm/boot/dts/dra7.dtsi | 117 ++++++++ arch/arm/boot/dts/omap2420.dtsi | 2 + arch/arm/boot/dts/omap2430.dtsi | 2 + arch/arm/boot/dts/omap3.dtsi | 2 + arch/arm/boot/dts/omap4.dtsi | 9 + arch/arm/boot/dts/omap5.dtsi | 2 + arch/arm/mach-omap2/devices.c | 2 +- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 14 - arch/arm/mach-omap2/omap_hwmod_2430_data.c | 13 - .../omap_hwmod_2xxx_3xxx_interconnect_data.c | 9 - .../omap_hwmod_33xx_43xx_interconnect_data.c | 10 - arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 10 - arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 +++++++++++++++++++++ arch/arm/mach-omap2/omap_hwmod_common_data.h | 1 - 16 files changed, 449 insertions(+), 61 deletions(-)
Signature · 1 line
2.0.0
PATCH v2 1/10 ARM: dts: OMAP2+: Add mailbox fifo and user information
The number of mailbox fifos and users (IP interrupts) are added to the Mailbox DT nodes on OMAP2420, OMAP2430, OMAP3, and OMAP5 family of SoCs through the DT properties "ti,mbox-num-fifos" and "ti,mbox-num-users" properties. This data represents the same data that used to be represented in hwmod attribute data through the .num_fifos and .num_users fields previously.
--- arch/arm/boot/dts/omap2420.dtsi | 2 ++ arch/arm/boot/dts/omap2430.dtsi | 2 ++ arch/arm/boot/dts/omap3.dtsi | 2 ++ arch/arm/boot/dts/omap5.dtsi | 2 ++ 4 files changed, 8 insertions(+)
arch/arm/boot/dts/omap2420.dtsi +2 -0
@@ -157,6 +157,8 @@ interrupts = <26>, <34>; interrupt-names = "dsp", "iva"; ti,hwmods = "mailbox"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <6>; }; timer1: timer at 48028000 {
arch/arm/boot/dts/omap2430.dtsi +2 -0
@@ -247,6 +247,8 @@ reg = <0x48094000 0x200>; interrupts = <26>; ti,hwmods = "mailbox"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <6>; }; timer1: timer at 49018000 {
arch/arm/boot/dts/omap3.dtsi +2 -0
@@ -332,6 +332,8 @@ ti,hwmods = "mailbox"; reg = <0x48094000 0x200>; interrupts = <26>; + ti,mbox-num-users = <2>; + ti,mbox-num-fifos = <2>; }; mcspi1: spi at 48098000 {
arch/arm/boot/dts/omap5.dtsi +2 -0
@@ -641,6 +641,8 @@ reg = <0x4a0f4000 0x200>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox"; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; }; timer1: timer at 4ae18000 {
Signature · 1 line
2.0.0
PATCH v2 1/10 ARM: dts: OMAP2+: Add mailbox fifo and user information
Quoted 8 lines · Suman Anna
The number of mailbox fifos and users (IP interrupts) are added to the Mailbox DT nodes on OMAP2420, OMAP2430, OMAP3, and OMAP5 family of SoCs through the DT properties "ti,mbox-num-fifos" and "ti,mbox-num-users" properties. This data represents the same data that used to be represented in hwmod attribute data through the .num_fifos and .num_users fields previously.
Signed-off-by Suman Anna <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH v2 2/10 ARM: dts: OMAP4: Add mailbox node
In reply to Suman AnnaThe mailbox DT node data has been added for OMAP44xx devices.
--- arch/arm/boot/dts/omap4.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/boot/dts/omap4.dtsi +9 -0
@@ -649,6 +649,15 @@ }; }; + mailbox: mailbox at 4a0f4000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4a0f4000 0x200>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "mailbox"; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + }; + timer1: timer at 4a318000 { compatible = "ti,omap3430-timer"; reg = <0x4a318000 0x80>;
Signature · 1 line
2.0.0
PATCH v2 3/10 ARM: dts: AM33xx: Add mailbox node
In reply to Suman AnnaThe mailbox DT node data has been added for AM33xx device. The mailbox IP in AM33xx is similar to the version found in OMAP4+ devices.
--- arch/arm/boot/dts/am33xx.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/boot/dts/am33xx.dtsi +9 -0
@@ -347,6 +347,15 @@ status = "disabled"; }; + mailbox: mailbox at 480C8000 { + compatible = "ti,omap4-mailbox"; + reg = <0x480C8000 0x200>; + interrupts = <77>; + ti,hwmods = "mailbox"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <8>; + }; + timer1: timer at 44e31000 { compatible = "ti,am335x-timer-1ms"; reg = <0x44e31000 0x400>;
Signature · 1 line
2.0.0
PATCH v2 4/10 ARM: dts: AM4372: Correct mailbox node data
In reply to Suman AnnaThe mailbox DT node for AM4372 is enabled and is corrected to remove some properties that have crept in by mistake.
--- arch/arm/boot/dts/am4372.dtsi | 3 --- 1 file changed, 3 deletions(-)
arch/arm/boot/dts/am4372.dtsi +0 -3
@@ -168,9 +168,6 @@ ti,hwmods = "mailbox"; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; - ti,mbox-names = "wkup_m3"; - ti,mbox-data = <0 0 0 0>; - status = "disabled"; }; timer1: timer at 44e31000 {
Signature · 1 line
2.0.0
PATCH v2 5/10 ARM: dts: DRA7: Add mailbox nodes
In reply to Suman AnnaDRA7xx has 13 system mailboxes, and is present on both the DRA72x and DRA74x family of SoCs. Add the DT nodes for all these 13 mailboxes. Except for mailbox 1, all other mailboxes do not have interrupts mapped into the MPU GIC by default.
All the mailboxes have been disabled and the interrupts property information is left out intentionally for now, because of the dependencies against the crossbar driver. These mailboxes can be enabled when a usecase arises and the crossbar driver dependencies are met.
NOTE: The mailbox 1 has different number of mailbox fifos and IP interrupts compared to the remaining 12 mailboxes.
--- arch/arm/boot/dts/dra7.dtsi | 117 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+)
arch/arm/boot/dts/dra7.dtsi +117 -0
@@ -338,6 +338,123 @@ status = "disabled"; }; + mailbox1: mailbox at 4a0f4000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4a0f4000 0x200>; + ti,hwmods = "mailbox1"; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + status = "disabled"; + }; + + mailbox2: mailbox at 4883a000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4883a000 0x200>; + ti,hwmods = "mailbox2"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox3: mailbox at 4883c000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4883c000 0x200>; + ti,hwmods = "mailbox3"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox4: mailbox at 4883e000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4883e000 0x200>; + ti,hwmods = "mailbox4"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox5: mailbox at 48840000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48840000 0x200>; + ti,hwmods = "mailbox5"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox6: mailbox at 48842000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48842000 0x200>; + ti,hwmods = "mailbox6"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox7: mailbox at 48844000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48844000 0x200>; + ti,hwmods = "mailbox7"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox8: mailbox at 48846000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48846000 0x200>; + ti,hwmods = "mailbox8"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox9: mailbox at 4885e000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4885e000 0x200>; + ti,hwmods = "mailbox9"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox10: mailbox at 48860000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48860000 0x200>; + ti,hwmods = "mailbox10"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox11: mailbox at 48862000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48862000 0x200>; + ti,hwmods = "mailbox11"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox12: mailbox at 48864000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48864000 0x200>; + ti,hwmods = "mailbox12"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox13: mailbox at 48802000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48802000 0x200>; + ti,hwmods = "mailbox13"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + timer1: timer at 4ae18000 { compatible = "ti,omap5430-timer"; reg = <0x4ae18000 0x80>;
Signature · 1 line
2.0.0
PATCH v2 6/10 ARM: DRA7: hwmod_data: Add mailbox hwmod data
In reply to Suman AnnaAdd the hwmod data for the 13 instances of the system mailbox IP in DRA7 SoC. The patch is needed for performing a soft-reset while configuring the respective mailbox instance, otherwise is a non-essential change for functionality. The modules are smart idled on reset, and the IP module mode is hardware controlled.
--- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+)
arch/arm/mach-omap2/omap_hwmod_7xx_data.c +305 -0
@@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { };/* +* 'mailbox' class +* +*/ + +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 , + .sysc_flags = (SYSC_HAS_RESET_STATUS |SYSC_HAS_SIDLEMODE | +SYSC_HAS_SOFTRESET ), + .idlemodes = (SIDLE_FORCE |SIDLE_NO |SIDLE_SMART ), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { + .name ="mailbox" , + .sysc = &dra7xx_mailbox_sysc, +}; + +/* mailbox1 */ +static struct omap_hwmod dra7xx_mailbox1_hwmod = { + .name ="mailbox1" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox2 */ +static struct omap_hwmod dra7xx_mailbox2_hwmod = { + .name ="mailbox2" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox3 */ +static struct omap_hwmod dra7xx_mailbox3_hwmod = { + .name ="mailbox3" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox4 */ +static struct omap_hwmod dra7xx_mailbox4_hwmod = { + .name ="mailbox4" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox5 */ +static struct omap_hwmod dra7xx_mailbox5_hwmod = { + .name ="mailbox5" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox6 */ +static struct omap_hwmod dra7xx_mailbox6_hwmod = { + .name ="mailbox6" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox7 */ +static struct omap_hwmod dra7xx_mailbox7_hwmod = { + .name ="mailbox7" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox8 */ +static struct omap_hwmod dra7xx_mailbox8_hwmod = { + .name ="mailbox8" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox9 */ +static struct omap_hwmod dra7xx_mailbox9_hwmod = { + .name ="mailbox9" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox10 */ +static struct omap_hwmod dra7xx_mailbox10_hwmod = { + .name ="mailbox10" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox11 */ +static struct omap_hwmod dra7xx_mailbox11_hwmod = { + .name ="mailbox11" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox12 */ +static struct omap_hwmod dra7xx_mailbox12_hwmod = { + .name ="mailbox12" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET , + }, + }, +}; + +/* mailbox13 */ +static struct omap_hwmod dra7xx_mailbox13_hwmod = { + .name ="mailbox13" , + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name ="l4cfg_clkdm" , + .prcm = { + .omap4 = { + .clkctrl_offs =DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET , + .context_offs =DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET , + }, + }, +}; + +/* * 'mcspi' class * */
@@ -2246,6 +2434,110 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> mailbox1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_mailbox1_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox2_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox3_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox4_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox5_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox6_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox7_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox8_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox9 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox9_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox10 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox10_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox11 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox11_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox12 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox12_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* l4_per3 -> mailbox13 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox13_hwmod, + .clk ="l3_iclk_div" , + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; +/* l4_per1 -> mcspi1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { .master = &dra7xx_l4_per1_hwmod,
@@ -2662,6 +2954,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__i2c3, &dra7xx_l4_per1__i2c4, &dra7xx_l4_per1__i2c5, + &dra7xx_l4_cfg__mailbox1, + &dra7xx_l4_per3__mailbox2, + &dra7xx_l4_per3__mailbox3, + &dra7xx_l4_per3__mailbox4, + &dra7xx_l4_per3__mailbox5, + &dra7xx_l4_per3__mailbox6, + &dra7xx_l4_per3__mailbox7, + &dra7xx_l4_per3__mailbox8, + &dra7xx_l4_per3__mailbox9, + &dra7xx_l4_per3__mailbox10, + &dra7xx_l4_per3__mailbox11, + &dra7xx_l4_per3__mailbox12, + &dra7xx_l4_per3__mailbox13, &dra7xx_l4_per1__mcspi1, &dra7xx_l4_per1__mcspi2, &dra7xx_l4_per1__mcspi3,
Signature · 1 line
2.0.0
Tony Lindgren
maintainerPATCH v2 6/10 ARM: DRA7: hwmod_data: Add mailbox hwmod data
Quoted 28 lines · Suman Anna
Add the hwmod data for the 13 instances of the system mailbox IP in DRA7 SoC. The patch is needed for performing a soft-reset while configuring the respective mailbox instance, otherwise is a non-essential change for functionality. The modules are smart idled on reset, and the IP module mode is hardware controlled.
Cc Rajendra Nayak <[email protected]>Cc Paul Walmsley <[email protected]>Signed-off-by Suman Anna <[email protected]>--- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+)arch/arm/mach-omap2/omap_hwmod_7xx_data.c +7
-0@@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { };/* +* 'mailbox' class +* +*/ + +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 ,
arch/arm/mach-omap2/omap_hwmod_7xx_data.c static struct omap_hwmod dra7xx_i2c5_hwmod = { · line 958
Quoted 10 lines
arch/arm/mach-omap2/omap_hwmod_7xx_data.c +10
-0+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { + .name ="mailbox" , + .sysc = &dra7xx_mailbox_sysc, +};
Hmm I'm seeing just the following MAILBOX_SYSCONFIG in at least am57xx TRM:
31:4 RESERVED
3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved
1 RESERVED
0 SOFTRESET
So it seems that SYSC_HAS_RESET_STATUS above is wrong? Can you guys please check.
Regards,
Tony
PATCH v2 6/10 ARM: DRA7: hwmod_data: Add mailbox hwmod data
Hi Tony,
Quoted 43 lines · Tony Lindgren
Quoted 28 lines · Suman Anna
Add the hwmod data for the 13 instances of the system mailbox IP in DRA7 SoC. The patch is needed for performing a soft-reset while configuring the respective mailbox instance, otherwise is a non-essential change for functionality. The modules are smart idled on reset, and the IP module mode is hardware controlled.
Cc Rajendra Nayak <[email protected]>Cc Paul Walmsley <[email protected]>Signed-off-by Suman Anna <[email protected]>--- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+)arch/arm/mach-omap2/omap_hwmod_7xx_data.c +7
-0@@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { };/* +* 'mailbox' class +* +*/ + +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 ,arch/arm/mach-omap2/omap_hwmod_7xx_data.c static struct omap_hwmod dra7xx_i2c5_hwmod = { · line 958
Quoted 10 lines
arch/arm/mach-omap2/omap_hwmod_7xx_data.c +10
-0+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { + .name ="mailbox" , + .sysc = &dra7xx_mailbox_sysc, +};Hmm I'm seeing just the following
MAILBOX_SYSCONFIGin at least am57xx TRM:
Quoted 7 lines
31:4 RESERVED
3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved
1 RESERVED
0 SOFTRESETSo it seems that
SYSC_HAS_RESET_STATUSabove is wrong? Can you guys please check.
The same SOFTRESET bit is used for both triggering the softreset and reading the reset done status. Once you write a 1 to trigger a reset, the bit will be cleared once the reset is done. This is no different from OMAP4. The logic in _wait_softreset_complete in omap_hwmod.c was already designed to work with this properly.
regards
Suman
Tony Lindgren
maintainerPATCH v2 6/10 ARM: DRA7: hwmod_data: Add mailbox hwmod data
Quoted 51 lines · Suman Anna
Hi Tony,
Quoted 48 lines · Tony Lindgren
Quoted 28 lines · Suman Anna
Add the hwmod data for the 13 instances of the system mailbox IP in DRA7 SoC. The patch is needed for performing a soft-reset while configuring the respective mailbox instance, otherwise is a non-essential change for functionality. The modules are smart idled on reset, and the IP module mode is hardware controlled.
Cc Rajendra Nayak <[email protected]>Cc Paul Walmsley <[email protected]>Signed-off-by Suman Anna <[email protected]>--- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+)arch/arm/mach-omap2/omap_hwmod_7xx_data.c +7
-0@@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { };/* +* 'mailbox' class +* +*/ + +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 ,arch/arm/mach-omap2/omap_hwmod_7xx_data.c static struct omap_hwmod dra7xx_i2c5_hwmod = { · line 958
Quoted 10 lines
arch/arm/mach-omap2/omap_hwmod_7xx_data.c +10
-0+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { + .name ="mailbox" , + .sysc = &dra7xx_mailbox_sysc, +};Hmm I'm seeing just the following
MAILBOX_SYSCONFIGin at least am57xx TRM:31:4 RESERVED
3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved
1 RESERVED
0 SOFTRESET
Quoted 8 lines
Quoted 2 lines
So it seems that
SYSC_HAS_RESET_STATUSabove is wrong? Can you guys please check.The same SOFTRESET bit is used for both triggering the softreset and reading the reset done status. Once you write a 1 to trigger a reset, the bit will be cleared once the reset is done. This is no different from OMAP4. The logic in
_wait_softreset_completeinomap_hwmod.cwas already designed to work with this properly.
Oh OK, I guess I got it confused with SYSS_HAS_RESET_STATUS. Paul, want to ack this one if no other issues? I can then set this series into a branch against -rc1 that we can all merge in as needed as it seems that the driver changes may need this branch as a base too.
Regards,
Tony
Tony Lindgren
maintainerPATCH v2 6/10 ARM: DRA7: hwmod_data: Add mailbox hwmod data
Quoted 61 lines · Tony Lindgren
Quoted 51 lines · Suman Anna
Hi Tony,
Quoted 48 lines · Tony Lindgren
Quoted 28 lines · Suman Anna
Add the hwmod data for the 13 instances of the system mailbox IP in DRA7 SoC. The patch is needed for performing a soft-reset while configuring the respective mailbox instance, otherwise is a non-essential change for functionality. The modules are smart idled on reset, and the IP module mode is hardware controlled.
Cc Rajendra Nayak <[email protected]>Cc Paul Walmsley <[email protected]>Signed-off-by Suman Anna <[email protected]>--- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+)arch/arm/mach-omap2/omap_hwmod_7xx_data.c +7
-0@@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { };/* +* 'mailbox' class +* +*/ + +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 ,arch/arm/mach-omap2/omap_hwmod_7xx_data.c static struct omap_hwmod dra7xx_i2c5_hwmod = { · line 958
Quoted 10 lines
arch/arm/mach-omap2/omap_hwmod_7xx_data.c +10
-0+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { + .name ="mailbox" , + .sysc = &dra7xx_mailbox_sysc, +};Hmm I'm seeing just the following
MAILBOX_SYSCONFIGin at least am57xx TRM:31:4 RESERVED
3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved
1 RESERVED
0 SOFTRESETQuoted 8 lines
Quoted 2 lines
So it seems that
SYSC_HAS_RESET_STATUSabove is wrong? Can you guys please check.The same SOFTRESET bit is used for both triggering the softreset and reading the reset done status. Once you write a 1 to trigger a reset, the bit will be cleared once the reset is done. This is no different from OMAP4. The logic in
_wait_softreset_completeinomap_hwmod.cwas already designed to work with this properly.
Quoted 4 lines
Oh OK, I guess I got it confused with
SYSS_HAS_RESET_STATUS. Paul, want to ack this one if no other issues? I can then set this series into a branch against -rc1 that we can all merge in as needed as it seems that the driver changes may need this branch as a base too.
I have applied these into omap-for-v3.17/mailbox and merged also into omap-for-v3.17/soc.
Regards,
Tony
PATCH v2 6/10 ARM: DRA7: hwmod_data: Add mailbox hwmod data
Quoted 62 lines · Tony Lindgren
Quoted 61 lines · Tony Lindgren
Quoted 59 lines · Suman Anna
Hi Tony,
Quoted 43 lines · Tony Lindgren
Quoted 28 lines · Suman Anna
Add the hwmod data for the 13 instances of the system mailbox IP in DRA7 SoC. The patch is needed for performing a soft-reset while configuring the respective mailbox instance, otherwise is a non-essential change for functionality. The modules are smart idled on reset, and the IP module mode is hardware controlled.
Cc Rajendra Nayak <[email protected]>Cc Paul Walmsley <[email protected]>Signed-off-by Suman Anna <[email protected]>--- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 305 ++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+)arch/arm/mach-omap2/omap_hwmod_7xx_data.c +7
-0@@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { };/* +* 'mailbox' class +* +*/ + +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 ,arch/arm/mach-omap2/omap_hwmod_7xx_data.c static struct omap_hwmod dra7xx_i2c5_hwmod = { · line 958
Quoted 10 lines
arch/arm/mach-omap2/omap_hwmod_7xx_data.c +10
-0+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { + .name ="mailbox" , + .sysc = &dra7xx_mailbox_sysc, +};Hmm I'm seeing just the following
MAILBOX_SYSCONFIGin at least am57xx TRM:Quoted 7 lines
31:4 RESERVED
3:2 SIDLEMODE 0 = force-idle 1 = no-idle, 2 = smart-idle, 3 = reserved
1 RESERVED
0 SOFTRESETSo it seems that
SYSC_HAS_RESET_STATUSabove is wrong? Can you guys please check.The same SOFTRESET bit is used for both triggering the softreset and reading the reset done status. Once you write a 1 to trigger a reset, the bit will be cleared once the reset is done. This is no different from OMAP4. The logic in
_wait_softreset_completeinomap_hwmod.cwas already designed to work with this properly.
Quoted 8 lines
Quoted 4 lines
Oh OK, I guess I got it confused with
SYSS_HAS_RESET_STATUS. Paul, want to ack this one if no other issues? I can then set this series into a branch against -rc1 that we can all merge in as needed as it seems that the driver changes may need this branch as a base too.I have applied these into omap-for-v3.17/mailbox and merged also into omap-for-v3.17/soc.
Thank you, Tony.
regards
Suman
PATCH v2 7/10 ARM: OMAP2+: Avoid mailbox legacy device creation for DT-boot
In reply to Suman AnnaThe legacy platform device for mailbox should not be created for a DT boot, so adjust the platform device initialization logic appropriately.
--- arch/arm/mach-omap2/devices.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/mach-omap2/devices.c +1 -1
@@ -460,9 +460,9 @@ static int __init omap2_init_devices(void)omap_init_audio ();omap_init_camera ();omap_init_hdmi_audio (); -omap_init_mbox ();/* If dtb is there, the devices will be created dynamically */ if (!of_have_populated_dt ()) { +omap_init_mbox ();omap_init_mcspi ();omap_init_sham ();omap_init_aes ();
Signature · 1 line
2.0.0
PATCH v2 8/10 ARM: OMAP2: hwmod_data: Remove legacy mailbox data and addrs
In reply to Suman AnnaOMAP2 devices are devicetree boot only, and the legacy mode of mailbox device creation should no longer be used, so remove the mailbox attribute data and the hwmod addr space used for creating mailboxes in legacy mode.
--- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 14 -------------- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 13 ------------- .../mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c | 9 --------- arch/arm/mach-omap2/omap_hwmod_common_data.h | 1 - 4 files changed, 37 deletions(-)
arch/arm/mach-omap2/omap_hwmod_2420_data.c +0 -14
@@ -16,7 +16,6 @@#include <linux/i2c-omap.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/omap-dma.h> -#include <linux/platform_data/mailbox-omap.h> #include <plat/dmtimer.h> #include "omap_hwmod.h"
@@ -163,18 +162,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { };/* mailbox */ -static struct omap_mbox_dev_info omap2420_mailbox_info[] = { - { .name ="dsp" , .tx_id =0 , .rx_id =1 , .irq_id =0 , .usr_id =0 }, - { .name ="iva" , .tx_id =2 , .rx_id =3 , .irq_id =1 , .usr_id =3 }, -}; - -static struct omap_mbox_pdata omap2420_mailbox_attrs = { - .num_users =4 , - .num_fifos =6 , - .info_cnt =ARRAY_SIZE (omap2420_mailbox_info), - .info = omap2420_mailbox_info, -}; -static struct omap_hwmod omap2420_mailbox_hwmod = { .name ="mailbox" , .class = &omap2xxx_mailbox_hwmod_class,
@@ -188,7 +175,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .dev_attr = &omap2420_mailbox_attrs, };/*
arch/arm/mach-omap2/omap_hwmod_2430_data.c +0 -13
@@ -17,7 +17,6 @@#include <linux/platform_data/asoc-ti-mcbsp.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/omap-dma.h> -#include <linux/platform_data/mailbox-omap.h> #include <plat/dmtimer.h> #include "omap_hwmod.h"
@@ -161,17 +160,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { };/* mailbox */ -static struct omap_mbox_dev_info omap2430_mailbox_info[] = { - { .name ="dsp" , .tx_id =0 , .rx_id =1 }, -}; - -static struct omap_mbox_pdata omap2430_mailbox_attrs = { - .num_users =4 , - .num_fifos =6 , - .info_cnt =ARRAY_SIZE (omap2430_mailbox_info), - .info = omap2430_mailbox_info, -}; -static struct omap_hwmod omap2430_mailbox_hwmod = { .name ="mailbox" , .class = &omap2xxx_mailbox_hwmod_class,
@@ -185,7 +173,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .dev_attr = &omap2430_mailbox_attrs, };/* mcspi3 */
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c +0 -9
@@ -152,15 +152,6 @@ struct omap_hwmod_addr_space omap2_dma_system_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2_mailbox_addrs[] = { - { - .pa_start =0x48094000 , - .pa_end =0x48094000 +SZ_512 -1 , - .flags =ADDR_TYPE_RT , - }, - { } -}; -struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = { { .name ="mpu" ,
arch/arm/mach-omap2/omap_hwmod_common_data.h +0 -1
@@ -33,7 +33,6 @@ extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; -extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
Signature · 1 line
2.0.0
PATCH v2 9/10 ARM: OMAP4: hwmod_data: Remove legacy mailbox addrs
In reply to Suman AnnaThe legacy-style definition of the hwmod addr space is no longer required after the addition of the OMAP4 mailbox DT node, so clean up this data.
--- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 10 ---------- 1 file changed, 10 deletions(-)
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +0 -10
@@ -4142,21 +4142,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { - { - .pa_start =0x4a0f4000 , - .pa_end =0x4a0f41ff , - .flags =ADDR_TYPE_RT - }, - { } -}; -/* l4_cfg -> mailbox */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_mailbox_hwmod, .clk ="l4_div_ck" , - .addr = omap44xx_mailbox_addrs, .user =OCP_USER_MPU |OCP_USER_SDMA , };
Signature · 1 line
2.0.0
PATCH v2 10/10 ARM: AM33xx: hwmod_data: Remove legacy mailbox addrs
In reply to Suman AnnaThe legacy-style definition of the hwmod addr space is no longer required as AM33xx/AM43xx are DT-boot only, and the minimal mailbox DT nodes have been added, so clean up this data.
--- arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c | 10 ---------- 1 file changed, 10 deletions(-)
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +0 -10
@@ -317,21 +317,11 @@ struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { - { - .pa_start =0x480C8000 , - .pa_end =0x480C8000 + (SZ_4K -1 ), - .flags =ADDR_TYPE_RT - }, - { } -}; -/* l4 ls -> mailbox */ struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_mailbox_hwmod, .clk ="l4ls_gclk" , - .addr = am33xx_mailbox_addrs, .user =OCP_USER_MPU , };
Signature · 1 line
2.0.0