arm: clk-imx6q: parent lvds_sel input from upstream clock gates
Subsystems (3)
PATCH 1/1 arm: clk-imx6q: parent lvds_sel input from upstream clock gates
The i.MX6 reference manual doesn't make a clear distinction between the fixed clock divider and the enable gate for the pcie and sata reference clocks. This lead to the lvds mux inputs in the imx6q clk driver to be parented from the ref clock (which is the divider) instead of the actual gate, which in turn prevents the upstream clock to actually be enabled when lvds clk out is active.
This fixes a hard machine hang regression in kernel 3.16 for boards where only pcie is active but no sata, as with this kernel version the imx6-pcie driver is no longer enabling the upstream clock directly but only lvds clk out.
---
Shawn, this is an urgent fix for 3.16. Can you please Ack it so arm-soc people can take this directly?
--- arch/arm/mach-imx/clk-imx6q.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/mach-imx/clk-imx6q.c +2 -2
@@ -70,7 +70,7 @@ static const char *cko_sels[] = { "cko1", "cko2", };static const char *lvds_sels[] = {"dummy" ,"dummy" ,"dummy" ,"dummy" ,"dummy" ,"dummy" ,"pll4_audio" ,"pll5_video" ,"pll8_mlb" ,"enet_ref" , -"pcie_ref" ,"sata_ref" , +"pcie_ref_125m" ,"sata_ref_100m" , };enum mx6q_clks {
@@ -491,7 +491,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)/* All existing boards with PCIe use LVDS1 */ if (IS_ENABLED (CONFIG_PCI_IMX6 )) -clk_set_parent (clk[lvds1_sel], clk[sata_ref]); +clk_set_parent (clk[lvds1_sel], clk[sata_ref_100m]);/* Set initial power mode */ imx6q_set_lpm (WAIT_CLOCKED );
Signature · 1 line
2.0.1
PATCH 1/1 arm: clk-imx6q: parent lvds_sel input from upstream clock gates
Quoted 13 lines · Lucas Stach
The i.MX6 reference manual doesn't make a clear distinction between the fixed clock divider and the enable gate for the pcie and sata reference clocks. This lead to the lvds mux inputs in the imx6q clk driver to be parented from the ref clock (which is the divider) instead of the actual gate, which in turn prevents the upstream clock to actually be enabled when lvds clk out is active.
This fixes a hard machine hang regression in kernel 3.16 for boards where only pcie is active but no sata, as with this kernel version the imx6-pcie driver is no longer enabling the upstream clock directly but only lvds clk out.
Quoted 7 lines
Reported-by Arne Ruhnau <[email protected]>Signed-off-by Lucas Stach <[email protected]>Tested-by Arne Ruhnau <[email protected]>---
Shawn, this is an urgent fix for 3.16. Can you please Ack it so arm-soc people can take this directly?
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It will conflict with the patch switching to use macro for clock IDs, which I'm about to send for 3.17, though.
Shawn
PATCH 1/1 arm: clk-imx6q: parent lvds_sel input from upstream clock gates
Quoted 22 lines · Shawn Guo
Quoted 13 lines · Lucas Stach
The i.MX6 reference manual doesn't make a clear distinction between the fixed clock divider and the enable gate for the pcie and sata reference clocks. This lead to the lvds mux inputs in the imx6q clk driver to be parented from the ref clock (which is the divider) instead of the actual gate, which in turn prevents the upstream clock to actually be enabled when lvds clk out is active.
This fixes a hard machine hang regression in kernel 3.16 for boards where only pcie is active but no sata, as with this kernel version the imx6-pcie driver is no longer enabling the upstream clock directly but only lvds clk out.
Quoted 7 lines
Reported-by Arne Ruhnau <[email protected]>Signed-off-by Lucas Stach <[email protected]>Tested-by Arne Ruhnau <[email protected]>---
Shawn, this is an urgent fix for 3.16. Can you please Ack it so arm-soc people can take this directly?
---
Quoted 4 lines
Acked-by Shawn Guo <[email protected]>It will conflict with the patch switching to use macro for clock IDs, which I'm about to send for 3.17, though.
Arnd, Olof,
Please do not apply the patch manually. I will send you a git tag for it, so that I can sort out the conflict in my tree.
Shawn