ARM: i.MX6: add more chip revision support
Subsystems (3)
PATCH 1/1 ARM: i.MX6: add more chip revision support
From: Jason Liu <[email protected]>
Add more revision support for the new i.MX6DQ tap-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed.
--- arch/arm/mach-imx/anatop.c | 9 +++++++++ arch/arm/mach-imx/mxc.h | 2 ++ 2 files changed, 11 insertions(+)
arch/arm/mach-imx/anatop.c +9 -0
@@ -104,6 +104,15 @@ void __init imx_init_revision_from_anatop(void)case 2 : revision =IMX_CHIP_REVISION_1_2 ;break ; +case 3 : + revision =IMX_CHIP_REVISION_1_3 ; +break ; +case 4 : + revision =IMX_CHIP_REVISION_1_4 ; +break ; +case 5 : + revision =IMX_CHIP_REVISION_1_5 ; +break ;default : revision =IMX_CHIP_REVISION_UNKNOWN ; }
arch/arm/mach-imx/mxc.h +2 -0
@@ -43,6 +43,8 @@#define IMX_CHIP_REVISION_1_1 0x11#define IMX_CHIP_REVISION_1_2 0x12#define IMX_CHIP_REVISION_1_3 0x13 +#define IMX_CHIP_REVISION_1_4 0x14 +#define IMX_CHIP_REVISION_1_5 0x15#define IMX_CHIP_REVISION_2_0 0x20#define IMX_CHIP_REVISION_2_1 0x21#define IMX_CHIP_REVISION_2_2 0x22
Signature · 1 line
1.9.1
Sascha Hauer
maintainerPATCH 1/1 ARM: i.MX6: add more chip revision support
Quoted 5 lines · Shawn Guo
From: Jason Liu <[email protected]>
Add more revision support for the new i.MX6DQ tap-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed.
So the chip identifies itself as 1.5 but the data sheet refers to it as 1.3. Is there a way to make that clear somewhere? Otherwise it's really confusing.
Sascha
Quoted 45 lines
Signed-off-by Jason Liu <[email protected]>Signed-off-by Shawn Guo <[email protected]>--- arch/arm/mach-imx/anatop.c | 9 +++++++++ arch/arm/mach-imx/mxc.h | 2 ++ 2 files changed, 11 insertions(+)arch/arm/mach-imx/anatop.c +9
-0@@ -104,6 +104,15 @@ void __init imx_init_revision_from_anatop(void)case 2 : revision =IMX_CHIP_REVISION_1_2 ;break ; +case 3 : + revision =IMX_CHIP_REVISION_1_3 ; +break ; +case 4 : + revision =IMX_CHIP_REVISION_1_4 ; +break ; +case 5 : + revision =IMX_CHIP_REVISION_1_5 ; +break ;default : revision =IMX_CHIP_REVISION_UNKNOWN ; }arch/arm/mach-imx/mxc.h +2
-0@@ -43,6 +43,8 @@#define IMX_CHIP_REVISION_1_1 0x11#define IMX_CHIP_REVISION_1_2 0x12#define IMX_CHIP_REVISION_1_3 0x13 +#define IMX_CHIP_REVISION_1_4 0x14 +#define IMX_CHIP_REVISION_1_5 0x15#define IMX_CHIP_REVISION_2_0 0x20#define IMX_CHIP_REVISION_2_1 0x21#define IMX_CHIP_REVISION_2_2 0x22Signature · 1 line
1.9.1
Signature · 4 lines
Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
PATCH 1/1 ARM: i.MX6: add more chip revision support
Quoted 4 lines · Sascha Hauer
Quoted 3 lines · Shawn Guo
From: Jason Liu <[email protected]>
Add more revision support for the new i.MX6DQ tap-out (TO1.5). This
Is it "tap-out" or "tape-out"? A quick google request suggests the latter.
Quoted 6 lines
Quoted 2 lines
TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed.
So the chip identifies itself as 1.5 but the data sheet refers to it as 1.3. Is there a way to make that clear somewhere? Otherwise it's really confusing.
Yeah, from the commit log I would have expected the following patch:
+ case 5:
+ revision = IMX_CHIP_REVISION_1_3;
+ break;
maybe with a code comment. Also, the commit log only mentions i.MX6DQ; I wonder about the other imx6 variants. I hope they use the same logic?
Best regards
Uwe
Quoted 20 lines
Quoted 20 lines
arch/arm/mach-imx/anatop.c +9
-0@@ -104,6 +104,15 @@ void __init imx_init_revision_from_anatop(void)case 2 : revision =IMX_CHIP_REVISION_1_2 ;break ; +case 3 : + revision =IMX_CHIP_REVISION_1_3 ; +break ; +case 4 : + revision =IMX_CHIP_REVISION_1_4 ; +break ; +case 5 : + revision =IMX_CHIP_REVISION_1_5 ; +break ;default : revision =IMX_CHIP_REVISION_UNKNOWN ; }
Signature · 2 lines
Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | http://www.pengutronix.de/ |
PATCH 1/1 ARM: i.MX6: add more chip revision support
Quoted 7 lines · Uwe Kleine-K?nig
Quoted 4 lines · Sascha Hauer
Quoted 3 lines · Shawn Guo
From: Jason Liu <[email protected]>
Add more revision support for the new i.MX6DQ tap-out (TO1.5). This
Is it "tap-out" or "tape-out"? A quick google request suggests the latter.
Yes, you're right.
Quoted 13 lines
Quoted 7 lines
Quoted 3 lines
TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed.
So the chip identifies itself as 1.5 but the data sheet refers to it as 1.3. Is there a way to make that clear somewhere? Otherwise it's really confusing.
Yeah, from the commit log I would have expected the following patch:
arch/arm/mach-imx/anatop.c +3
-0+case 5 : + revision =IMX_CHIP_REVISION_1_3 ; +break ;
Quoted 1 line
maybe with a code comment.
I did consider such fix-up when I was trying to submit Jason's patch from FSL internal tree. But this TO1.5 numbering has been already used in a couple of FSL BSP releases. We do not really want to maintain two different numbering scheme between FSL BSP and upstream kernel.
Quoted 2 lines
Also, the commit log only mentions i.MX6DQ; I
wonder about the other imx6 variants. I hope they use the same logic?
This is another reason for that above fix-up may not be good. This revision mismatch between register and document is only with i.MX6DQ. So far, only i.MX6DQ revision goes beyond 1.2, but I'm sure such mismatch/mistake will not be with other imx6 variants.
Shawn
PATCH 1/1 ARM: i.MX6: add more chip revision support
In reply to Sascha HauerQuoted 10 lines · Sascha Hauer
Quoted 5 lines · Shawn Guo
From: Jason Liu <[email protected]>
Add more revision support for the new i.MX6DQ tap-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed.
So the chip identifies itself as 1.5 but the data sheet refers to it as 1.3. Is there a way to make that clear somewhere? Otherwise it's really confusing.
I can add a note about that in the code, but I'm not really sure if there is a better way to pass such info to end users. Suggestions are welcomed.
Shawn
Sascha Hauer
maintainerPATCH 1/1 ARM: i.MX6: add more chip revision support
Quoted 8 lines · Shawn Guo
Quoted 7 lines · Sascha Hauer
Quoted 5 lines · Shawn Guo
From: Jason Liu <[email protected]>
Add more revision support for the new i.MX6DQ tap-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed.
Quoted 7 lines
Quoted 3 lines
So the chip identifies itself as 1.5 but the data sheet refers to it as 1.3. Is there a way to make that clear somewhere? Otherwise it's really confusing.
I can add a note about that in the code, but I'm not really sure if there is a better way to pass such info to end users. Suggestions are welcomed.
Since the anatop code can be used by other SoCs aswell and you're saying that even the other i.MX6 SoC variants may have a different numbering I think adding a comment to the code is the best we can do.
The only other possibility I can think of is to make the info string we print during boot SoC specific again, but I think we are all glad that this isn't the case anymore.
So adding a comment should be fine. At least the code would be the place I would look if I remembered that there is some inconsistency and don't know exactly what it was.
Sascha
Signature · 4 lines
Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |