igb_uio related patches

@@ -22,6 +22,8 @@
  *   Intel Corporation
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/device.h>
 #include <linux/module.h>
 #include <linux/pci.h>

@@ -394,7 +396,7 @@ done:
 	pci_unlock(pdev);
 spin_unlock:
 	spin_unlock_irqrestore(&udev->lock, flags);
-	printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
+	pr_info("irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
 
 	return ret;
 }

@@ -557,7 +559,7 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	 * memory
 	 */
 	if (pci_enable_device(dev)) {
-		printk(KERN_ERR "Cannot enable PCI device\n");
+		dev_err(&dev->dev, "Cannot enable PCI device\n");
 		goto fail_free;
 	}
 

@@ -566,7 +568,7 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	 * module
 	 */
 	if (pci_request_regions(dev, "igb_uio")) {
-		printk(KERN_ERR "Cannot request regions\n");
+		dev_err(&dev->dev, "Cannot request regions\n");
 		goto fail_disable;
 	}
 

@@ -579,10 +581,10 @@ igbuio_pci_probe(struct pci_dev *dev, co
 
 	/* set 64-bit DMA mask */
 	if (pci_set_dma_mask(dev,  DMA_BIT_MASK(64))) {
-		printk(KERN_ERR "Cannot set DMA mask\n");
+		dev_err(&dev->dev, "Cannot set DMA mask\n");
 		goto fail_release_iomem;
 	} else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
-		printk(KERN_ERR "Cannot set consistent DMA mask\n");
+		dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
 		goto fail_release_iomem;
 	}
 

@@ -613,7 +615,7 @@ igbuio_pci_probe(struct pci_dev *dev, co
 		}
 		else {
 			pci_disable_msix(udev->pdev);
-			printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n");
+			pr_info("fail to enable pci msix, or not enough msix entries\n");
 		}
 	}
 	switch (udev->mode) {

@@ -665,7 +667,7 @@ igbuio_pci_remove(struct pci_dev *dev)
 	struct uio_info *info = pci_get_drvdata(dev);
 
 	if (info->priv == NULL) {
-		printk(KERN_DEBUG "Not igbuio device\n");
+		pr_notice("Not igbuio device\n");
 		return;
 	}
 

@@ -685,18 +687,18 @@ static int
 igbuio_config_intr_mode(char *intr_str)
 {
 	if (!intr_str) {
-		printk(KERN_INFO "Use MSIX interrupt by default\n");
+		pr_info("Use MSIX interrupt by default\n");
 		return 0;
 	}
 
 	if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
 		igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
-		printk(KERN_INFO "Use MSIX interrupt\n");
+		pr_info("Use MSIX interrupt\n");
 	} else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
 		igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
-		printk(KERN_INFO "Use legacy interrupt\n");
+		pr_info("Use legacy interrupt\n");
 	} else {
-		printk(KERN_INFO "Error: bad parameter - %s\n", intr_str);
+		pr_info("Error: bad parameter - %s\n", intr_str);
 		return -EINVAL;
 	}
 

@@ -589,7 +589,7 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	}
 
 	/* fill uio infos */
-	udev->info.name = "Intel IGB UIO";
+	udev->info.name = "igb_uio";
 	udev->info.version = "0.1";
 	udev->info.handler = igbuio_pci_irqhandler;
 	udev->info.irqcontrol = igbuio_pci_irqcontrol;

@@ -83,9 +83,8 @@ igbuio_get_uio_pci_dev(struct uio_info *
 }
 
 /* sriov sysfs */
-int local_pci_num_vf(struct pci_dev *dev)
-{
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
+static int pci_num_vf(struct pci_dev *dev)
 	struct iov {
 		int pos;
 		int nres;

@@ -100,17 +99,15 @@ int local_pci_num_vf(struct pci_dev *dev
 		return 0;
 
 	return iov->nr_virtfn;
-#else
-	return pci_num_vf(dev);
-#endif
 }
+#endif
 
 static ssize_t
 show_max_vfs(struct device *dev, struct device_attribute *attr,
 	     char *buf)
 {
-	return snprintf(buf, 10, "%u\n", local_pci_num_vf(
-				container_of(dev, struct pci_dev, dev)));
+	return snprintf(buf, 10, "%u\n",
+			pci_num_vf(container_of(dev, struct pci_dev, dev)));
 }
 
 static ssize_t

@@ -126,7 +123,7 @@ store_max_vfs(struct device *dev, struct
 
 	if (0 == max_vfs)
 		pci_disable_sriov(pdev);
-	else if (0 == local_pci_num_vf(pdev))
+	else if (0 == pci_num_vf(pdev))
 		err = pci_enable_sriov(pdev, max_vfs);
 	else /* do nothing if change max_vfs number */
 		err = -EINVAL;

@@ -37,19 +37,6 @@
 #endif
 #include <rte_pci_dev_features.h>
 
-/**
- * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
- * but none of them in kernel 2.6.35.
- */
-#ifndef PCI_MSIX_ENTRY_SIZE
-#define PCI_MSIX_ENTRY_SIZE             16
-#define PCI_MSIX_ENTRY_LOWER_ADDR       0
-#define PCI_MSIX_ENTRY_UPPER_ADDR       4
-#define PCI_MSIX_ENTRY_DATA             8
-#define PCI_MSIX_ENTRY_VECTOR_CTRL      12
-#define PCI_MSIX_ENTRY_CTRL_MASKBIT     1
-#endif
-
 #ifdef RTE_PCI_CONFIG
 #define PCI_SYS_FILE_BUF_SIZE      10
 #define PCI_DEV_CAP_REG            0xA4

@@ -59,8 +46,6 @@
 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 #endif
 
-#define IGBUIO_NUM_MSI_VECTORS 1
-
 /**
  * A structure describing the private information for a uio device.
  */

@@ -69,8 +54,6 @@ struct rte_uio_pci_dev {
 	struct pci_dev *pdev;
 	spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
 	enum rte_intr_mode mode;
-	struct msix_entry \
-		msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
 };
 
 static char *intr_mode = NULL;

@@ -546,6 +529,7 @@ static int
 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
 	struct rte_uio_pci_dev *udev;
+	struct msix_entry msix_entry;
 
 	udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
 	if (!udev)

@@ -602,12 +586,8 @@ igbuio_pci_probe(struct pci_dev *dev, co
 
 	/* check if it need to try msix first */
 	if (igbuio_intr_mode_preferred == RTE_INTR_MODE_MSIX) {
-		int vector;
-
-		for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
-			udev->msix_entries[vector].entry = vector;
-
-		if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
+		msix_entry.entry = 0;
+		if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
 			udev->mode = RTE_INTR_MODE_MSIX;
 		}
 		else {

@@ -618,7 +598,7 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	switch (udev->mode) {
 	case RTE_INTR_MODE_MSIX:
 		udev->info.irq_flags = 0;
-		udev->info.irq = udev->msix_entries[0].vector;
+		udev->info.irq = msix_entry.vector;
 		break;
 	case RTE_INTR_MODE_MSI:
 		break;

@@ -518,7 +518,7 @@ igbuio_setup_bars(struct pci_dev *dev, s
 		}
 	}
 
-	return ((iom != 0) ? ret : ENOENT);
+	return (iom != 0) ? ret : -ENOENT;
 }
 
 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)

@@ -530,6 +530,7 @@ igbuio_pci_probe(struct pci_dev *dev, co
 {
 	struct rte_uio_pci_dev *udev;
 	struct msix_entry msix_entry;
+	int err;
 
 	udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
 	if (!udev)

@@ -539,7 +540,8 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	 * enable device: ask low-level code to enable I/O and
 	 * memory
 	 */
-	if (pci_enable_device(dev)) {
+	err = pci_enable_device(dev);
+	if (err != 0) {
 		dev_err(&dev->dev, "Cannot enable PCI device\n");
 		goto fail_free;
 	}

@@ -548,7 +550,8 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	 * reserve device's PCI memory regions for use by this
 	 * module
 	 */
-	if (pci_request_regions(dev, "igb_uio")) {
+	err = pci_request_regions(dev, "igb_uio");
+	if (err != 0) {
 		dev_err(&dev->dev, "Cannot request regions\n");
 		goto fail_disable;
 	}

@@ -557,14 +560,19 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	pci_set_master(dev);
 
 	/* remap IO memory */
-	if (igbuio_setup_bars(dev, &udev->info))
+	err = igbuio_setup_bars(dev, &udev->info);
+	if (err != 0)
 		goto fail_release_iomem;
 
 	/* set 64-bit DMA mask */
-	if (pci_set_dma_mask(dev,  DMA_BIT_MASK(64))) {
+	err = pci_set_dma_mask(dev,  DMA_BIT_MASK(64));
+	if (err != 0) {
 		dev_err(&dev->dev, "Cannot set DMA mask\n");
 		goto fail_release_iomem;
-	} else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
+	}
+
+	err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
+	if (err != 0) {
 		dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
 		goto fail_release_iomem;
 	}

@@ -613,19 +621,22 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	pci_set_drvdata(dev, udev);
 	igbuio_pci_irqcontrol(&udev->info, 0);
 
-	if (sysfs_create_group(&dev->dev.kobj, &dev_attr_grp))
+	err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
+	if (err != 0)
 		goto fail_release_iomem;
 
 	/* register uio driver */
-	if (uio_register_device(&dev->dev, &udev->info))
-		goto fail_release_iomem;
+	err = uio_register_device(&dev->dev, &udev->info);
+	if (err != 0)
+		goto fail_remove_group;
 
 	printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
 
 	return 0;
 
-fail_release_iomem:
+fail_remove_group:
 	sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
+fail_release_iomem:
 	igbuio_pci_release_iomem(&udev->info);
 	if (udev->mode == RTE_INTR_MODE_MSIX)
 		pci_disable_msix(udev->pdev);

@@ -635,7 +646,7 @@ fail_disable:
 fail_free:
 	kfree(udev);
 
-	return -ENODEV;
+	return err;
 }
 
 static void

@@ -721,7 +721,7 @@ igbuio_pci_exit_module(void)
 module_init(igbuio_pci_init_module);
 module_exit(igbuio_pci_exit_module);
 
-module_param(intr_mode, charp, S_IRUGO | S_IWUSR);
+module_param(intr_mode, charp, S_IRUGO);
 MODULE_PARM_DESC(intr_mode,
 "igb_uio interrupt mode (default=msix):\n"
 "    " RTE_INTR_MODE_MSIX_NAME "       Use MSIX interrupt\n"

@@ -52,7 +52,6 @@
 struct rte_uio_pci_dev {
 	struct uio_info info;
 	struct pci_dev *pdev;
-	spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
 	enum rte_intr_mode mode;
 };
 

@@ -220,36 +219,67 @@ static const struct attribute_group dev_
 	.attrs = dev_attrs,
 };
 
-static inline int
-pci_lock(struct pci_dev * pdev)
-{
-	/* Some function names changes between 3.2.0 and 3.3.0... */
+
 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
-	pci_block_user_cfg_access(pdev);
-	return 1;
-#else
-	return pci_cfg_access_trylock(pdev);
-#endif
+/* Check if INTX works to control irq's.
+ * Set's INTX_DISABLE flag and reads it back
+ */
+static bool pci_intx_mask_supported(struct pci_dev *dev)
+{
+	bool mask_supported = false;
+	uint16_t orig, new
+
+	pci_block_user_cfg_access(dev);
+	pci_read_config_word(pdev, PCI_COMMAND, &orig);
+	pci_write_config_word(dev, PCI_COMMAND,
+			      orig ^ PCI_COMMAND_INTX_DISABLE);
+	pci_read_config_word(dev, PCI_COMMAND, &new);
+
+	if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
+		dev_err(&dev->dev, "Command register changed from "
+			"0x%x to 0x%x: driver or hardware bug?\n", orig, new);
+	} else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
+		mask_supported = true;
+		pci_write_config_word(dev, PCI_COMMAND, orig);
+	}
+	pci_unblock_user_cfg_access(dev);
 }
 
-static inline void
-pci_unlock(struct pci_dev * pdev)
+static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 {
-	/* Some function names changes between 3.2.0 and 3.3.0... */
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
-	pci_unblock_user_cfg_access(pdev);
-#else
-	pci_cfg_access_unlock(pdev);
-#endif
+	bool pending;
+	uint32_t status;
+
+	pci_block_user_cfg_access(dev);
+	pci_read_config_dword(pdev, PCI_COMMAND, &status);
+
+	/* interrupt is not ours, goes to out */
+	pending = (((status >> 16) & PCI_STATUS_INTERRUPT) != 0);
+	if (pending) {
+		uint16_t old, new;
+
+		old = status;
+		if (state != 0)
+			new = old & (~PCI_COMMAND_INTX_DISABLE);
+		else
+			new = old | PCI_COMMAND_INTX_DISABLE;
+
+		if (old != new)
+			pci_write_config_word(pdev, PCI_COMMAND, new);
+	}
+	pci_unblock_user_cfg_access(dev);
+
+	return pending;
 }
+#endif
 
-/**
+/*
  * It masks the msix on/off of generating MSI-X messages.
  */
-static int
+static void
 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
 {
-	uint32_t mask_bits = desc->masked;
+	u32 mask_bits = desc->masked;
 	unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
 						PCI_MSIX_ENTRY_VECTOR_CTRL;
 

@@ -263,48 +293,25 @@ igbuio_msix_mask_irq(struct msi_desc *de
 		readl(desc->mask_base);
 		desc->masked = mask_bits;
 	}
-
-	return 0;
 }
 
-/**
- * This function sets/clears the masks for generating LSC interrupts.
- *
- * @param info
- *   The pointer to struct uio_info.
- * @param on
- *   The on/off flag of masking LSC.
- * @return
- *   -On success, zero value.
- *   -On failure, a negative value.
- */
-static int
-igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
-{
-	struct pci_dev *pdev = udev->pdev;
-
-	if (udev->mode == RTE_INTR_MODE_MSIX) {
-		struct msi_desc *desc;
 
-		list_for_each_entry(desc, &pdev->msi_list, list) {
-			igbuio_msix_mask_irq(desc, state);
-		}
-	} else if (udev->mode == RTE_INTR_MODE_LEGACY) {
-		uint32_t status;
-		uint16_t old, new;
+static void
+igbuio_msi_mask_irq(struct irq_data *data, u32 enable)
+{
+	struct msi_desc *desc = irq_data_get_msi(data);
+	u32 mask_bits = desc->masked;
+	unsigned offset = data->irq - desc->dev->irq;
+	u32 mask = 1 << offset;
+	u32 flag = enable << offset;
 
-		pci_read_config_dword(pdev, PCI_COMMAND, &status);
-		old = status;
-		if (state != 0)
-			new = old & (~PCI_COMMAND_INTX_DISABLE);
-		else
-			new = old | PCI_COMMAND_INTX_DISABLE;
+	mask_bits &= ~mask;
+	mask_bits |= flag;
 
-		if (old != new)
-			pci_write_config_word(pdev, PCI_COMMAND, new);
+	if (desc->msi_attrib.maskbit && mask_bits != desc->masked) {
+		pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
+		desc->masked = mask_bits;
 	}
-
-	return 0;
 }
 
 /**

@@ -323,20 +330,23 @@ igbuio_set_interrupt_mask(struct rte_uio
 static int
 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
 {
-	unsigned long flags;
 	struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
 	struct pci_dev *pdev = udev->pdev;
 
-	spin_lock_irqsave(&udev->lock, flags);
-	if (!pci_lock(pdev)) {
-		spin_unlock_irqrestore(&udev->lock, flags);
-		return -1;
-	}
+	pci_cfg_access_lock(pdev);
+	if (udev->mode == RTE_INTR_MODE_LEGACY)
+		pci_intx(pdev, !!irq_state);
+	else if (udev->mode == RTE_INTR_MODE_MSI) {
+		struct irq_data *data = irq_get_irq_data(pdev->irq);
 
-	igbuio_set_interrupt_mask(udev, irq_state);
+		igbuio_msi_mask_irq(data, !!irq_state);
+	} else if (udev->mode == RTE_INTR_MODE_MSIX) {
+		struct msi_desc *desc;
 
-	pci_unlock(pdev);
-	spin_unlock_irqrestore(&udev->lock, flags);
+		list_for_each_entry(desc, &pdev->msi_list, list)
+			igbuio_msix_mask_irq(desc, irq_state);
+	}
+	pci_cfg_access_unlock(pdev);
 
 	return 0;
 }

@@ -348,37 +358,15 @@ igbuio_pci_irqcontrol(struct uio_info *i
 static irqreturn_t
 igbuio_pci_irqhandler(int irq, struct uio_info *info)
 {
-	irqreturn_t ret = IRQ_NONE;
-	unsigned long flags;
 	struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
-	struct pci_dev *pdev = udev->pdev;
-	uint32_t cmd_status_dword;
-	uint16_t status;
 
-	spin_lock_irqsave(&udev->lock, flags);
-	/* block userspace PCI config reads/writes */
-	if (!pci_lock(pdev))
-		goto spin_unlock;
-
-	/* for legacy mode, interrupt maybe shared */
-	if (udev->mode == RTE_INTR_MODE_LEGACY) {
-		pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
-		status = cmd_status_dword >> 16;
-		/* interrupt is not ours, goes to out */
-		if (!(status & PCI_STATUS_INTERRUPT))
-			goto done;
-	}
-
-	igbuio_set_interrupt_mask(udev, 0);
-	ret = IRQ_HANDLED;
-done:
-	/* unblock userspace PCI config reads/writes */
-	pci_unlock(pdev);
-spin_unlock:
-	spin_unlock_irqrestore(&udev->lock, flags);
-	pr_info("irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
+	/* Legacy mode need to mask in hardware */
+	if (udev->mode == RTE_INTR_MODE_LEGACY &&
+	    !pci_check_and_mask_intx(udev->pdev))
+		return IRQ_NONE;
 
-	return ret;
+	/* Message signal mode, no share IRQ and automasked */
+	return IRQ_HANDLED;
 }
 
 #ifdef CONFIG_XEN_DOM0

@@ -582,6 +570,7 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	udev->info.version = "0.1";
 	udev->info.handler = igbuio_pci_irqhandler;
 	udev->info.irqcontrol = igbuio_pci_irqcontrol;
+	udev->info.irq = dev->irq;
 #ifdef CONFIG_XEN_DOM0
 	/* check if the driver run on Xen Dom0 */
 	if (xen_initial_domain())

@@ -589,38 +578,48 @@ igbuio_pci_probe(struct pci_dev *dev, co
 #endif
 	udev->info.priv = udev;
 	udev->pdev = dev;
-	udev->mode = RTE_INTR_MODE_LEGACY;
-	spin_lock_init(&udev->lock);
 
-	/* check if it need to try msix first */
-	if (igbuio_intr_mode_preferred == RTE_INTR_MODE_MSIX) {
+	switch (igbuio_intr_mode_preferred) {
+	case RTE_INTR_MODE_NONE:
+		udev->info.irq = 0;
+		break;
+
+	case RTE_INTR_MODE_MSIX:
+		/* Only 1 msi-x vector needed */
 		msix_entry.entry = 0;
 		if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
+			dev_dbg(&dev->dev, "using MSI-X");
+			udev->info.irq = msix_entry.vector;
 			udev->mode = RTE_INTR_MODE_MSIX;
+			break;
 		}
-		else {
-			pci_disable_msix(udev->pdev);
-			pr_info("fail to enable pci msix, or not enough msix entries\n");
-		}
-	}
-	switch (udev->mode) {
-	case RTE_INTR_MODE_MSIX:
-		udev->info.irq_flags = 0;
-		udev->info.irq = msix_entry.vector;
-		break;
+		/* fall back to MSI */
 	case RTE_INTR_MODE_MSI:
-		break;
+		if (pci_enable_msi(dev) == 0) {
+			dev_dbg(&dev->dev, "using MSI");
+			udev->info.irq = dev->irq;
+			udev->mode = RTE_INTR_MODE_MSI;
+			break;
+		}
+		/* fall back to INTX */
 	case RTE_INTR_MODE_LEGACY:
-		udev->info.irq_flags = IRQF_SHARED;
-		udev->info.irq = dev->irq;
+		if (pci_intx_mask_supported(dev)) {
+			dev_dbg(&dev->dev, "using INTX");
+			udev->info.irq_flags = IRQF_SHARED;
+			udev->mode = RTE_INTR_MODE_LEGACY;
+		} else {
+			dev_err(&dev->dev, "PCI INTX mask not supported\n");
+			err = -EIO;
+			goto fail_release_iomem;
+		}
 		break;
 	default:
-		break;
+		dev_err(&dev->dev, "invalid IRQ mode %u",
+			igbuio_intr_mode_preferred);
+		err = -EINVAL;
+		goto fail_release_iomem;
 	}
 
-	pci_set_drvdata(dev, udev);
-	igbuio_pci_irqcontrol(&udev->info, 0);
-
 	err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
 	if (err != 0)
 		goto fail_release_iomem;

@@ -630,7 +629,10 @@ igbuio_pci_probe(struct pci_dev *dev, co
 	if (err != 0)
 		goto fail_remove_group;
 
-	printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
+	pci_set_drvdata(dev, udev);
+
+	dev_info(&dev->dev, "uio device registered with irq %lx\n",
+		 udev->info.irq);
 
 	return 0;
 

@@ -640,6 +642,8 @@ fail_release_iomem:
 	igbuio_pci_release_iomem(&udev->info);
 	if (udev->mode == RTE_INTR_MODE_MSIX)
 		pci_disable_msix(udev->pdev);
+	if (udev->mode == RTE_INTR_MODE_MSI)
+		pci_disable_msi(udev->pdev);
 	pci_release_regions(dev);
 fail_disable:
 	pci_disable_device(dev);

@@ -39,8 +39,7 @@ enum rte_intr_mode {
 	RTE_INTR_MODE_NONE = 0,
 	RTE_INTR_MODE_LEGACY,
 	RTE_INTR_MODE_MSI,
-	RTE_INTR_MODE_MSIX,
-	RTE_INTR_MODE_MAX
+	RTE_INTR_MODE_MSIX
 };
 
 #endif /* _RTE_PCI_DEV_DEFS_H_ */

@@ -148,10 +148,13 @@ store_extended_tag(struct device *dev,
 	else
 		return -EINVAL;
 
+	pci_cfg_access_lock(pci_dev);
 	pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
 					PCI_DEV_CAP_REG, &val);
-	if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
+	if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
+		pci_cfg_access_unlock(pci_dev);
 		return -EPERM;
+	}
 
 	val = 0;
 	pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,

@@ -162,6 +165,7 @@ store_extended_tag(struct device *dev,
 		val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
 	pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
 					PCI_DEV_CTRL_REG, val);
+	pci_cfg_access_unlock(pci_dev);
 
 	return count;
 }

@@ -646,7 +646,7 @@ fail_release_iomem:
 	igbuio_pci_release_iomem(&udev->info);
 	if (udev->mode == RTE_INTR_MODE_MSIX)
 		pci_disable_msix(udev->pdev);
-	if (udev->mode == RTE_INTR_MODE_MSI)
+	else if (udev->mode == RTE_INTR_MODE_MSI)
 		pci_disable_msi(udev->pdev);
 	pci_release_regions(dev);
 fail_disable:

@@ -661,6 +661,7 @@ static void
 igbuio_pci_remove(struct pci_dev *dev)
 {
 	struct uio_info *info = pci_get_drvdata(dev);
+	struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
 
 	if (info->priv == NULL) {
 		pr_notice("Not igbuio device\n");

@@ -670,9 +671,10 @@ igbuio_pci_remove(struct pci_dev *dev)
 	sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
 	uio_unregister_device(info);
 	igbuio_pci_release_iomem(info);
-	if (((struct rte_uio_pci_dev *)info->priv)->mode ==
-			RTE_INTR_MODE_MSIX)
+	if (udev->mode == RTE_INTR_MODE_MSIX)
 		pci_disable_msix(dev);
+	else if (udev->mode == RTE_INTR_MODE_MSI)
+		pci_disable_msi(dev);
 	pci_release_regions(dev);
 	pci_disable_device(dev);
 	pci_set_drvdata(dev, NULL);

@@ -690,6 +692,9 @@ igbuio_config_intr_mode(char *intr_str)
 	if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
 		igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
 		pr_info("Use MSIX interrupt\n");
+	} else if (!strcmp(intr_str, RTE_INTR_MODE_MSI_NAME)) {
+		igbuio_intr_mode_preferred = RTE_INTR_MODE_MSI;
+		pr_info("Use MSI interrupt\n");
 	} else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
 		igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
 		pr_info("Use legacy interrupt\n");

@@ -733,6 +738,7 @@ module_param(intr_mode, charp, S_IRUGO);
 MODULE_PARM_DESC(intr_mode,
 "igb_uio interrupt mode (default=msix):\n"
 "    " RTE_INTR_MODE_MSIX_NAME "       Use MSIX interrupt\n"
+"    " RTE_INTR_MODE_MSI_NAME "       Use MSI interrupt\n"
 "    " RTE_INTR_MODE_LEGACY_NAME "     Use Legacy interrupt\n"
 "\n");
 

@@ -65,7 +65,7 @@ igbuio_get_uio_pci_dev(struct uio_info *
 }
 
 /* sriov sysfs */
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34)
 static int pci_num_vf(struct pci_dev *dev)
 	struct iov {
 		int pos;

@@ -75,7 +75,7 @@ static int pci_num_vf(struct pci_dev *de
 		u16 total;
 		u16 initial;
 		u16 nr_virtfn;
-	} *iov = (struct iov*)dev->sriov;
+	} *iov = (struct iov *)dev->sriov;
 
 	if (!dev->is_physfn)
 		return 0;

@@ -204,9 +204,9 @@ store_max_read_request_size(struct devic
 
 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
 #ifdef RTE_PCI_CONFIG
-static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag, \
+static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,
 	store_extended_tag);
-static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR, \
+static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,
 	show_max_read_request_size, store_max_read_request_size);
 #endif
 

@@ -216,7 +216,7 @@ static struct attribute *dev_attrs[] = {
 	&dev_attr_extended_tag.attr,
 	&dev_attr_max_read_request_size.attr,
 #endif
-        NULL,
+	NULL,
 };
 
 static const struct attribute_group dev_attr_grp = {

@@ -224,7 +224,7 @@ static const struct attribute_group dev_
 };
 
 
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
 /* Check if INTX works to control irq's.
  * Set's INTX_DISABLE flag and reads it back
  */

@@ -378,6 +378,7 @@ static int
 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
 {
 	int idx;
+
 	idx = (int)vma->vm_pgoff;
 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 	vma->vm_page_prot.pgprot |= _PAGE_IOMAP;

@@ -400,8 +401,9 @@ igbuio_dom0_pci_mmap(struct uio_info *in
 
 	if (vma->vm_pgoff >= MAX_UIO_MAPS)
 		return -EINVAL;
-	if(info->mem[vma->vm_pgoff].size == 0)
-		return  -EINVAL;
+
+	if (info->mem[vma->vm_pgoff].size == 0)
+		return -EINVAL;
 
 	idx = (int)vma->vm_pgoff;
 	switch (info->mem[idx].memtype) {

@@ -423,8 +425,8 @@ igbuio_pci_setup_iomem(struct pci_dev *d
 	unsigned long addr, len;
 	void *internal_addr;
 
-	if (sizeof(info->mem) / sizeof (info->mem[0]) <= n)
-		return (EINVAL);
+	if (sizeof(info->mem) / sizeof(info->mem[0]) <= n)
+		return -EINVAL;
 
 	addr = pci_resource_start(dev, pci_bar);
 	len = pci_resource_len(dev, pci_bar);

@@ -448,20 +450,20 @@ igbuio_pci_setup_ioport(struct pci_dev *
 {
 	unsigned long addr, len;
 
-	if (sizeof(info->port) / sizeof (info->port[0]) <= n)
-		return (EINVAL);
+	if (sizeof(info->port) / sizeof(info->port[0]) <= n)
+		return -EINVAL;
 
 	addr = pci_resource_start(dev, pci_bar);
 	len = pci_resource_len(dev, pci_bar);
 	if (addr == 0 || len == 0)
-		return (-1);
+		return -EINVAL;
 
 	info->port[n].name = name;
 	info->port[n].start = addr;
 	info->port[n].size = len;
 	info->port[n].porttype = UIO_PORT_X86;
 
-	return (0);
+	return 0;
 }
 
 /* Unmap previously ioremap'd resources */

@@ -469,6 +471,7 @@ static void
 igbuio_pci_release_iomem(struct uio_info *info)
 {
 	int i;
+
 	for (i = 0; i < MAX_UIO_MAPS; i++) {
 		if (info->mem[i].internal_addr)
 			iounmap(info->mem[i].internal_addr);

@@ -497,14 +500,16 @@ igbuio_setup_bars(struct pci_dev *dev, s
 				pci_resource_start(dev, i) != 0) {
 			flags = pci_resource_flags(dev, i);
 			if (flags & IORESOURCE_MEM) {
-				if ((ret = igbuio_pci_setup_iomem(dev, info,
-						iom, i, bar_names[i])) != 0)
-					return (ret);
+				ret = igbuio_pci_setup_iomem(dev, info, iom,
+							     i, bar_names[i]);
+				if (ret != 0)
+					return ret;
 				iom++;
 			} else if (flags & IORESOURCE_IO) {
-				if ((ret = igbuio_pci_setup_ioport(dev, info,
-						iop, i, bar_names[i])) != 0)
-					return (ret);
+				ret = igbuio_pci_setup_ioport(dev, info, iop,
+							      i, bar_names[i]);
+				if (ret != 0)
+					return ret;
 				iop++;
 			}
 		}

@@ -513,7 +518,7 @@ igbuio_setup_bars(struct pci_dev *dev, s
 	return (iom != 0) ? ret : -ENOENT;
 }
 
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
 static int __devinit
 #else
 static int

index 05cbe8e..c5dbbe2 100644
@@ -148,11 +148,11 @@ store_extended_tag(struct device *dev,
 	else
 		return -EINVAL;
 
-	pci_cfg_access_lock(pci_dev);
+	pci_block_user_cfg_access(pci_dev);
 	pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
 					PCI_DEV_CAP_REG, &val);
 	if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
-		pci_cfg_access_unlock(pci_dev);
+		pci_unblock_user_cfg_access(pci_dev);
 		return -EPERM;
 	}
 

@@ -165,7 +165,7 @@ store_extended_tag(struct device *dev,
 		val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
 	pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
 					PCI_DEV_CTRL_REG, val);
-	pci_cfg_access_unlock(pci_dev);
+	pci_block_user_cfg_access(pci_dev);
 
 	return count;
 }

@@ -227,25 +227,26 @@ static const struct attribute_group dev_attr_grp = {
 /* Check if INTX works to control irq's.
  * Set's INTX_DISABLE flag and reads it back
  */
-static bool pci_intx_mask_supported(struct pci_dev *dev)
+static bool pci_intx_mask_supported(struct pci_dev *pdev)
 {
 	bool mask_supported = false;
-	uint16_t orig, new
+	uint16_t orig, new;
 
-	pci_block_user_cfg_access(dev);
+	pci_block_user_cfg_access(pdev);
 	pci_read_config_word(pdev, PCI_COMMAND, &orig);
-	pci_write_config_word(dev, PCI_COMMAND,
+	pci_write_config_word(pdev, PCI_COMMAND,
 			      orig ^ PCI_COMMAND_INTX_DISABLE);
-	pci_read_config_word(dev, PCI_COMMAND, &new);
+	pci_read_config_word(pdev, PCI_COMMAND, &new);
 
 	if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
-		dev_err(&dev->dev, "Command register changed from "
+		dev_err(&pdev->dev, "Command register changed from "
 			"0x%x to 0x%x: driver or hardware bug?\n", orig, new);
 	} else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
 		mask_supported = true;
-		pci_write_config_word(dev, PCI_COMMAND, orig);
+		pci_write_config_word(pdev, PCI_COMMAND, orig);
 	}
-	pci_unblock_user_cfg_access(dev);
+	pci_unblock_user_cfg_access(pdev);
+	return mask_supported;
 }
 
 static bool pci_check_and_mask_intx(struct pci_dev *pdev)

@@ -253,7 +254,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 	bool pending;
 	uint32_t status;
 
-	pci_block_user_cfg_access(dev);
+	pci_block_user_cfg_access(pdev);
 	pci_read_config_dword(pdev, PCI_COMMAND, &status);
 
 	/* interrupt is not ours, goes to out */

@@ -262,7 +263,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 		uint16_t old, new;
 
 		old = status;
-		if (state != 0)
+		if (status != 0)
 			new = old & (~PCI_COMMAND_INTX_DISABLE);
 		else
 			new = old | PCI_COMMAND_INTX_DISABLE;

@@ -270,7 +271,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 		if (old != new)
 			pci_write_config_word(pdev, PCI_COMMAND, new);
 	}
-	pci_unblock_user_cfg_access(dev);
+	pci_unblock_user_cfg_access(pdev);
 
 	return pending;
 }

@@ -335,7 +336,7 @@ igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
 	struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
 	struct pci_dev *pdev = udev->pdev;
 
-	pci_cfg_access_lock(pdev);
+	pci_block_user_cfg_access(pdev);
 	if (udev->mode == RTE_INTR_MODE_LEGACY)
 		pci_intx(pdev, !!irq_state);
 	else if (udev->mode == RTE_INTR_MODE_MSI) {

@@ -348,7 +349,7 @@ igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
 		list_for_each_entry(desc, &pdev->msi_list, list)
 			igbuio_msix_mask_irq(desc, irq_state);
 	}
-	pci_cfg_access_unlock(pdev);
+	pci_unblock_user_cfg_access(pdev);
 
 	return 0;
 }

index 05cbe8e..02545d9 100644
@@ -227,25 +227,27 @@ static const struct attribute_group dev_attr_grp = {
 /* Check if INTX works to control irq's.
  * Set's INTX_DISABLE flag and reads it back
  */
-static bool pci_intx_mask_supported(struct pci_dev *dev)
+static bool pci_intx_mask_supported(struct pci_dev *pdev)
 {
 	bool mask_supported = false;
-	uint16_t orig, new
+	uint16_t orig, new;
 
-	pci_block_user_cfg_access(dev);
+	pci_block_user_cfg_access(pdev);
 	pci_read_config_word(pdev, PCI_COMMAND, &orig);
-	pci_write_config_word(dev, PCI_COMMAND,
+	pci_write_config_word(pdev, PCI_COMMAND,
 			      orig ^ PCI_COMMAND_INTX_DISABLE);
-	pci_read_config_word(dev, PCI_COMMAND, &new);
+	pci_read_config_word(pdev, PCI_COMMAND, &new);
 
 	if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
-		dev_err(&dev->dev, "Command register changed from "
+		dev_err(&pdev->dev, "Command register changed from "
 			"0x%x to 0x%x: driver or hardware bug?\n", orig, new);
 	} else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
 		mask_supported = true;
-		pci_write_config_word(dev, PCI_COMMAND, orig);
+		pci_write_config_word(pdev, PCI_COMMAND, orig);
 	}
-	pci_unblock_user_cfg_access(dev);
+	pci_unblock_user_cfg_access(pdev);
+
+	return mask_supported;
 }
 
 static bool pci_check_and_mask_intx(struct pci_dev *pdev)

@@ -253,7 +255,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 	bool pending;
 	uint32_t status;
 
-	pci_block_user_cfg_access(dev);
+	pci_block_user_cfg_access(pdev);
 	pci_read_config_dword(pdev, PCI_COMMAND, &status);
 
 	/* interrupt is not ours, goes to out */

@@ -262,7 +264,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 		uint16_t old, new;
 
 		old = status;
-		if (state != 0)
+		if (status != 0)
 			new = old & (~PCI_COMMAND_INTX_DISABLE);
 		else
 			new = old | PCI_COMMAND_INTX_DISABLE;

@@ -270,7 +272,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 		if (old != new)
 			pci_write_config_word(pdev, PCI_COMMAND, new);
 	}
-	pci_unblock_user_cfg_access(dev);
+	pci_unblock_user_cfg_access(pdev);
 
 	return pending;
 }

index 02545d9..605410e 100644
@@ -223,6 +223,26 @@ static const struct attribute_group dev_attr_grp = {
 	.attrs = dev_attrs,
 };
 
+static inline void
+pci_config_lock(struct pci_dev *pdev)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
+	pci_block_user_cfg_access(pdev);
+#else
+	pci_cfg_access_lock(pdev);
+#endif
+}
+
+static inline void
+pci_config_unlock(struct pci_dev *pdev)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
+	pci_unblock_user_cfg_access(pdev);
+#else
+	pci_cfg_access_unlock(pdev);
+#endif
+}
+
 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
 /* Check if INTX works to control irq's.
  * Set's INTX_DISABLE flag and reads it back

index 605410e..418bfa2 100644
@@ -148,11 +148,11 @@ store_extended_tag(struct device *dev,
 	else
 		return -EINVAL;
 
-	pci_cfg_access_lock(pci_dev);
+	pci_config_lock(pci_dev);
 	pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
 					PCI_DEV_CAP_REG, &val);
 	if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
-		pci_cfg_access_unlock(pci_dev);
+		pci_config_unlock(pci_dev);
 		return -EPERM;
 	}
 

@@ -165,7 +165,7 @@ store_extended_tag(struct device *dev,
 		val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
 	pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
 					PCI_DEV_CTRL_REG, val);
-	pci_cfg_access_unlock(pci_dev);
+	pci_config_unlock(pci_dev);
 
 	return count;
 }

@@ -252,7 +252,7 @@ static bool pci_intx_mask_supported(struct pci_dev *pdev)
 	bool mask_supported = false;
 	uint16_t orig, new;
 
-	pci_block_user_cfg_access(pdev);
+	pci_config_lock(pdev);
 	pci_read_config_word(pdev, PCI_COMMAND, &orig);
 	pci_write_config_word(pdev, PCI_COMMAND,
 			      orig ^ PCI_COMMAND_INTX_DISABLE);

@@ -265,7 +265,7 @@ static bool pci_intx_mask_supported(struct pci_dev *pdev)
 		mask_supported = true;
 		pci_write_config_word(pdev, PCI_COMMAND, orig);
 	}
-	pci_unblock_user_cfg_access(pdev);
+	pci_config_unlock(pdev);
 
 	return mask_supported;
 }

@@ -275,7 +275,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 	bool pending;
 	uint32_t status;
 
-	pci_block_user_cfg_access(pdev);
+	pci_config_lock(pdev);
 	pci_read_config_dword(pdev, PCI_COMMAND, &status);
 
 	/* interrupt is not ours, goes to out */

@@ -292,7 +292,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 		if (old != new)
 			pci_write_config_word(pdev, PCI_COMMAND, new);
 	}
-	pci_unblock_user_cfg_access(pdev);
+	pci_config_unlock(pdev);
 
 	return pending;
 }

@@ -357,7 +357,7 @@ igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
 	struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
 	struct pci_dev *pdev = udev->pdev;
 
-	pci_cfg_access_lock(pdev);
+	pci_config_lock(pdev);
 	if (udev->mode == RTE_INTR_MODE_LEGACY)
 		pci_intx(pdev, !!irq_state);
 	else if (udev->mode == RTE_INTR_MODE_MSI) {

@@ -370,7 +370,7 @@ igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
 		list_for_each_entry(desc, &pdev->msi_list, list)
 			igbuio_msix_mask_irq(desc, irq_state);
 	}
-	pci_cfg_access_unlock(pdev);
+	pci_config_unlock(pdev);
 
 	return 0;
 }