crypto: qat: Checkpatch and other cleanups plus SKU1

index dd4e0d3..f22b488 100644
@@ -1088,14 +1088,13 @@ static void qat_uclo_fill_uwords(struct icp_qat_uclo_objhandle *obj_handle,
 		*uword = fill;
 }
 
-static int qat_uclo_wr_uimage_raw_page(struct icp_qat_fw_loader_handle *handle,
-				       struct icp_qat_uclo_encap_page
-				       *encap_page, unsigned int ae)
+static void qat_uclo_wr_uimage_raw_page(struct icp_qat_fw_loader_handle *handle,
+					struct icp_qat_uclo_encap_page
+					*encap_page, unsigned int ae)
 {
 	unsigned int uw_physical_addr, uw_relative_addr, i, words_num, cpylen;
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
 	uint64_t fill_pat;
-	int status = 0;
 
 	/* load the page starting at appropriate ustore address */
 	/* get fill-pattern from an image -- they are all the same */

@@ -1126,18 +1125,15 @@ static int qat_uclo_wr_uimage_raw_page(struct icp_qat_fw_loader_handle *handle,
 		uw_relative_addr += cpylen;
 		words_num -= cpylen;
 	}
-	return status;
 }
 
-static int
-qat_uclo_wr_uimage_pages(struct icp_qat_fw_loader_handle *handle,
-			 struct icp_qat_uof_image *image)
+static void qat_uclo_wr_uimage_pages(struct icp_qat_fw_loader_handle *handle,
+				     struct icp_qat_uof_image *image)
 {
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
 	unsigned int ctx_mask, s;
 	struct icp_qat_uclo_page *page;
 	unsigned char ae;
-	int retval = 0;
 	int ctx;
 
 	if (ICP_QAT_CTX_MODE(image->ae_mode) == ICP_QAT_UCLO_MAX_CTX)

@@ -1160,8 +1156,7 @@ qat_uclo_wr_uimage_pages(struct icp_qat_fw_loader_handle *handle,
 		page = obj_handle->ae_data[ae].ae_slices[s].page;
 		if (!page->encap_page->def_page)
 			continue;
-		if (qat_uclo_wr_uimage_raw_page(handle, page->encap_page, ae))
-			return -EINVAL;
+		qat_uclo_wr_uimage_raw_page(handle, page->encap_page, ae);
 
 		page = obj_handle->ae_data[ae].ae_slices[s].page;
 		for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++)

@@ -1172,7 +1167,6 @@ qat_uclo_wr_uimage_pages(struct icp_qat_fw_loader_handle *handle,
 		qat_hal_set_pc(handle, (unsigned char)ae, image->ctx_assigned,
 			       image->entry_address);
 	}
-	return retval;
 }
 
 int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle)

@@ -1187,9 +1181,8 @@ int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle)
 			return -EINVAL;
 		if (qat_uclo_init_ustore(handle, &(obj_handle->ae_uimage[i])))
 			return -EINVAL;
-		if (qat_uclo_wr_uimage_pages(handle,
-					     obj_handle->ae_uimage[i].img_ptr))
-			return -EINVAL;
+		qat_uclo_wr_uimage_pages(handle,
+					 obj_handle->ae_uimage[i].img_ptr);
 	}
 	return 0;
 }

index 4eb8969..f854bac 100644
@@ -104,12 +104,15 @@ static inline int adf_bank_debugfs_add(struct adf_etr_bank_data *bank)
 {
 	return 0;
 }
+
 #define adf_bank_debugfs_rm(bank) do {} while (0)
+
 static inline int adf_ring_debugfs_add(struct adf_etr_ring_data *ring,
 				       const char *name)
 {
 	return 0;
 }
+
 #define adf_ring_debugfs_rm(ring) do {} while (0)
 #endif
 #endif

index d1d4802..c8d2669 100644
@@ -358,6 +358,7 @@ struct icp_qat_fw_la_resp {
 	uint64_t opaque_data;
 	uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
 };
+
 #define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \
 	((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \
 	  ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))

index 4279076..aba7f1d 100644
@@ -49,7 +49,6 @@
 #include <linux/list.h>
 #include <linux/seq_file.h>
 #include "adf_accel_devices.h"
-#include "adf_common_drv.h"
 #include "adf_cfg.h"
 
 static DEFINE_MUTEX(qat_cfg_read_lock);

index cc7ec40..5031f8c 100644
@@ -120,14 +120,14 @@ struct icp_qat_hw_auth_config {
 #define QAT_AUTH_ALGO_SHA3_BITPOS 22
 #define QAT_AUTH_ALGO_SHA3_MASK 0x3
 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
-	((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
-	(((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
+	(((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
+	((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
 	(((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
 	 QAT_AUTH_ALGO_SHA3_BITPOS) | \
 	 (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
 	(algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
 	& QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
-	(((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+	((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
 
 struct icp_qat_hw_auth_counter {
 	__be32 counter;

index 946686f..59df488 100644
@@ -759,7 +759,7 @@ void qat_alg_callback(void *resp)
 	qat_alg_free_bufl(inst, qat_req);
 	if (unlikely(qat_res != ICP_QAT_FW_COMN_STATUS_FLAG_OK))
 		res = -EBADMSG;
-	areq->base.complete(&(areq->base), res);
+	areq->base.complete(&areq->base, res);
 }
 
 static int qat_alg_dec(struct aead_request *areq)

146 lines not on this page · raw message

index 17a9954f..b1a16eb 100644
@@ -901,8 +901,8 @@ static int qat_uclo_set_ae_mode(struct icp_qat_fw_loader_handle *handle)
 			      (unsigned long *)&handle->hal_handle->ae_mask))
 			continue;
 		ae_data = &obj_handle->ae_data[ae];
-		for (s = 0; s < ae_data->slice_num && s < ICP_QAT_UCLO_MAX_CTX;
-		     s++) {
+		for (s = 0; s < min_t(unsigned int, ae_data->slice_num,
+				      ICP_QAT_UCLO_MAX_CTX); s++) {
 			if (!obj_handle->ae_data[ae].ae_slices[s].encap_image)
 				continue;
 			uof_image = ae_data->ae_slices[s].encap_image->img_ptr;

index 120fbce..2132a8c 100644
@@ -124,7 +124,7 @@ struct icp_qat_uclo_region {
 };
 
 struct icp_qat_uclo_aeslice {
-	struct icp_qat_uclo_region *regions;
+	struct icp_qat_uclo_region *region;
 	struct icp_qat_uclo_page *page;
 	struct icp_qat_uclo_page *cur_page[ICP_QAT_UCLO_MAX_CTX];
 	struct icp_qat_uclo_encapme *encap_image;

index b1a16eb..557fa60 100644
@@ -79,37 +79,37 @@ static int qat_uclo_init_ae_data(struct icp_qat_uclo_objhandle *obj_handle,
 	} else {
 		ae_slice->ctx_mask_assigned = 0;
 	}
-	ae_slice->regions = kzalloc(sizeof(*ae_slice->regions), GFP_KERNEL);
-	if (!ae_slice->regions)
+	ae_slice->region = kzalloc(sizeof(*ae_slice->region), GFP_KERNEL);
+	if (!ae_slice->region)
 		return -ENOMEM;
 	ae_slice->page = kzalloc(sizeof(*ae_slice->page), GFP_KERNEL);
 	if (!ae_slice->page)
 		goto out_err;
 	page = ae_slice->page;
 	page->encap_page = encap_image->page;
-	ae_slice->page->region = ae_slice->regions;
+	ae_slice->page->region = ae_slice->region;
 	ae_data->slice_num++;
 	return 0;
 out_err:
-	kfree(ae_slice->regions);
-	ae_slice->regions = NULL;
+	kfree(ae_slice->region);
+	ae_slice->region = NULL;
 	return -ENOMEM;
 }
 
 static int qat_uclo_free_ae_data(struct icp_qat_uclo_aedata *ae_data)
 {
-	unsigned int ss = 0;
+	unsigned int i;
 
 	if (!ae_data) {
 		pr_err("QAT: bad argument, ae_data is NULL\n ");
 		return -EINVAL;
 	}
 
-	for (ss = 0; ss < ae_data->slice_num; ss++) {
-		kfree(ae_data->ae_slices[ss].regions);
-		ae_data->ae_slices[ss].regions = NULL;
-		kfree(ae_data->ae_slices[ss].page);
-		ae_data->ae_slices[ss].page = NULL;
+	for (i = 0; i < ae_data->slice_num; i++) {
+		kfree(ae_data->ae_slices[i].region);
+		ae_data->ae_slices[i].region = NULL;
+		kfree(ae_data->ae_slices[i].page);
+		ae_data->ae_slices[i].page = NULL;
 	}
 	return 0;
 }

index 28da876..da9626b 100644
@@ -424,7 +424,7 @@ static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
 		SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl &
 			    (~MC_TIMESTAMP_ENABLE));
 
-	for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) {
+	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
 		if (!(handle->hal_handle->ae_mask & (1 << ae)))
 			continue;
 		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0);

@@ -492,7 +492,7 @@ int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle)
 		goto out_err;
 
 	/* Set undefined power-up/reset states to reasonable default values */
-	for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) {
+	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
 		if (!(handle->hal_handle->ae_mask & (1 << ae)))
 			continue;
 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES,

@@ -608,7 +608,7 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
 	unsigned int savctx = 0;
 	int ret = 0;
 
-	for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) {
+	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
 		if (!(handle->hal_handle->ae_mask & (1 << ae)))
 			continue;
 		for (reg = 0; reg < ICP_QAT_UCLO_MAX_GPR_REG; reg++) {

@@ -637,7 +637,7 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
 		qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0);
 		qat_hal_enable_ctx(handle, ae, ctx_mask);
 	}
-	for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) {
+	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
 		if (!(handle->hal_handle->ae_mask & (1 << ae)))
 			continue;
 		/* wait for AE to finish */

@@ -674,17 +674,16 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
 #define ICP_DH895XCC_PMISC_BAR 1
 int qat_hal_init(struct adf_accel_dev *accel_dev)
 {
-	unsigned char ae = 0;
-	unsigned int csr_val = 0;
-	unsigned int max_en_ae_num = 0;
-	struct icp_qat_fw_loader_handle *handle = NULL;
+	unsigned char ae;
+	unsigned int max_en_ae_id = 0;
+	struct icp_qat_fw_loader_handle *handle;
 	struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev;
 	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
 	struct adf_bar *bar = &pci_info->pci_bars[ADF_DH895XCC_PMISC_BAR];
 
 	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
 	if (!handle)
-		goto out_handle;
+		return -ENOMEM;
 
 	handle->hal_cap_g_ctl_csr_addr_v = bar->virt_addr +
 						ICP_DH895XCC_CAP_OFFSET;

@@ -713,9 +712,9 @@ int qat_hal_init(struct adf_accel_dev *accel_dev)
 		    handle->hal_handle->max_ustore;
 		handle->hal_handle->aes[ae].live_ctx_mask =
 						ICP_QAT_UCLO_AE_ALL_CTX;
-		max_en_ae_num = ae;
+		max_en_ae_id = ae;
 	}
-	handle->hal_handle->ae_max_num = max_en_ae_num;
+	handle->hal_handle->ae_max_num = max_en_ae_id + 1;
 	/* take all AEs out of reset */
 	if (qat_hal_clr_reset(handle)) {
 		pr_err("QAT: qat_hal_clr_reset error\n");

@@ -724,7 +723,9 @@ int qat_hal_init(struct adf_accel_dev *accel_dev)
 	if (qat_hal_clear_gpr(handle))
 		goto out_err;
 	/* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */
-	for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) {
+	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
+		unsigned int csr_val = 0;
+
 		if (!(hw_data->ae_mask & (1 << ae)))
 			continue;
 		qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE, &csr_val);

@@ -738,7 +739,6 @@ out_err:
 	kfree(handle->hal_handle);
 out_hal_handle:
 	kfree(handle);
-out_handle:
 	return -EFAULT;
 }
 

197 lines not on this page · raw message

index 25801fe..c77453b 100644
@@ -67,11 +67,11 @@ int adf_ae_fw_load(struct adf_accel_dev *accel_dev)
 	uof_size = loader_data->uof_fw->size;
 	uof_addr = (void *)loader_data->uof_fw->data;
 	if (qat_uclo_map_uof_obj(loader_data->fw_loader, uof_addr, uof_size)) {
-		pr_err("QAT: Failed to map uof\n");
+		pr_err("QAT: Failed to map UOF\n");
 		goto out_err;
 	}
 	if (qat_uclo_wr_all_uimage(loader_data->fw_loader)) {
-		pr_err("QAT: Failed to map uof\n");
+		pr_err("QAT: Failed to map UOF\n");
 		goto out_err;
 	}
 	return 0;

index 5c3d6f1..5c0e47a 100644
@@ -136,7 +136,7 @@ int adf_dev_start(struct adf_accel_dev *accel_dev)
 	set_bit(ADF_STATUS_AE_INITIALISED, &accel_dev->status);
 
 	if (adf_ae_fw_load(accel_dev)) {
-		pr_err("Failed to load acceleration FW\n");
+		pr_err("QAT: Failed to load acceleration FW\n");
 		adf_ae_fw_release(accel_dev);
 		return -EFAULT;
 	}

index da9626b..8d686a2 100644
@@ -849,8 +849,7 @@ static int qat_hal_exec_micro_inst(struct icp_qat_fw_loader_handle *handle,
 	unsigned int ctxarb_ctl, ctx_enables;
 
 	if ((inst_num > handle->hal_handle->max_ustore) || !micro_inst) {
-		pr_err("QAT: invalid instructs inst_num=%d, micro_inst=0x%p\n ",
-		       inst_num, micro_inst);
+		pr_err("QAT: invalid instruction num %d\n", inst_num);
 		return -EINVAL;
 	}
 	/* save current context */

index ebd5da0..2580091 100644
@@ -132,7 +132,7 @@ static int qat_uclo_check_format(struct icp_qat_uof_filehdr *hdr)
 		return -EINVAL;
 	}
 	if (min != ICP_QAT_UOF_MINVER || maj != ICP_QAT_UOF_MAJVER) {
-		pr_err("QAT: bad uof version, major 0x%x, minor 0x%x\n",
+		pr_err("QAT: bad UOF version, major 0x%x, minor 0x%x\n",
 		       maj, min);
 		return -EINVAL;
 	}

@@ -249,7 +249,7 @@ static int qat_uclo_fetch_initmem_ae(struct icp_qat_fw_loader_handle *handle,
 	}
 	str = qat_uclo_get_string(&obj_handle->str_table, init_mem->sym_name);
 	if (!str) {
-		pr_err("QAT: AE name assigned in uof init table is NULL\n");
+		pr_err("QAT: AE name assigned in UOF init table is NULL\n");
 		return -EINVAL;
 	}
 	if (qat_uclo_parse_num(str, ae)) {

@@ -751,14 +751,14 @@ static int qat_uclo_check_uof_compat(struct icp_qat_uclo_objhandle *obj_handle)
 	unsigned int maj_ver, prod_type = obj_handle->prod_type;
 
 	if (!(prod_type & obj_handle->encap_uof_obj.obj_hdr->cpu_type)) {
-		pr_err("QAT: uof type 0x%x not match with cur platform 0x%x\n",
+		pr_err("QAT: UOF type 0x%x not match with cur platform 0x%x\n",
 		       obj_handle->encap_uof_obj.obj_hdr->cpu_type, prod_type);
 		return -EINVAL;
 	}
 	maj_ver = obj_handle->prod_rev & 0xff;
 	if ((obj_handle->encap_uof_obj.obj_hdr->max_cpu_ver < maj_ver) ||
 	    (obj_handle->encap_uof_obj.obj_hdr->min_cpu_ver > maj_ver)) {
-		pr_err("QAT: uof majVer 0x%x out of range\n", maj_ver);
+		pr_err("QAT: UOF majVer 0x%x out of range\n", maj_ver);
 		return -EINVAL;
 	}
 	return 0;

@@ -868,7 +868,7 @@ static int qat_uclo_init_globals(struct icp_qat_fw_loader_handle *handle)
 		return 0;
 	if (obj_handle->init_mem_tab.entry_num) {
 		if (qat_uclo_init_memory(handle)) {
-			pr_err("QAT: initalize memory failed\n");
+			pr_err("QAT: initialize memory failed\n");
 			return -EINVAL;
 		}
 	}

@@ -917,13 +917,13 @@ static int qat_uclo_set_ae_mode(struct icp_qat_fw_loader_handle *handle)
 			if (qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0,
 						   (char)ICP_QAT_LOC_MEM0_MODE
 						   (uof_image->ae_mode))) {
-				pr_err("QAT: qat_hal_set_ae_lm_mode error\n ");
+				pr_err("QAT: qat_hal_set_ae_lm_mode LMEM0 error\n");
 				return -EFAULT;
 			}
 			if (qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM1,
 						   (char)ICP_QAT_LOC_MEM1_MODE
 						   (uof_image->ae_mode))) {
-				pr_err("QAT: qat_hal_set_ae_lm_mode error\n ");
+				pr_err("QAT: qat_hal_set_ae_lm_mode LMEM1 error\n");
 				return -EFAULT;
 			}
 		}

@@ -961,14 +961,14 @@ static int qat_uclo_parse_uof_obj(struct icp_qat_fw_loader_handle *handle)
 	obj_handle->prod_rev = PID_MAJOR_REV |
 			(PID_MINOR_REV & handle->hal_handle->revision_id);
 	if (qat_uclo_check_uof_compat(obj_handle)) {
-		pr_err("QAT: uof incompatible\n");
+		pr_err("QAT: UOF incompatible\n");
 		return -EINVAL;
 	}
 	obj_handle->ustore_phy_size = ICP_QAT_UCLO_MAX_USTORE;
 	if (!obj_handle->obj_hdr->file_buff ||
 	    !qat_uclo_map_str_table(obj_handle->obj_hdr, ICP_QAT_UOF_STRT,
 				    &obj_handle->str_table)) {
-		pr_err("QAT: uof doesn't have effective images\n");
+		pr_err("QAT: UOF doesn't have effective images\n");
 		goto out_err;
 	}
 	obj_handle->uimage_num =

index 8d686a2..9b8a315 100644
@@ -795,17 +795,6 @@ static void qat_hal_get_uwords(struct icp_qat_fw_loader_handle *handle,
 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);
 }
 
-static int qat_hal_count_bits(unsigned int word)
-{
-	int n = 0;
-
-	while (word) {
-		n++;
-		word &= word - 1;
-	}
-	return n;
-}
-
 void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle,
 		     unsigned char ae, unsigned int uaddr,
 		     unsigned int words_num, unsigned int *data)

@@ -822,9 +811,9 @@ void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle,
 			  ((data[i] & 0xff00) << 2) |
 			  (0x3 << 8) | (data[i] & 0xff);
 		uwrd_hi = (0xf << 4) | ((data[i] & 0xf0000000) >> 28);
-		uwrd_hi |= (qat_hal_count_bits(data[i] & 0xffff) & 0x1) << 8;
+		uwrd_hi |= (hweight32(data[i] & 0xffff) & 0x1) << 8;
 		tmp = ((data[i] >> 0x10) & 0xffff);
-		uwrd_hi |= (qat_hal_count_bits(tmp) & 0x1) << 9;
+		uwrd_hi |= (hweight32(tmp) & 0x1) << 9;
 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);
 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);
 	}

index 2580091..1e27f9f 100644
@@ -256,10 +256,6 @@ static int qat_uclo_fetch_initmem_ae(struct icp_qat_fw_loader_handle *handle,
 		pr_err("QAT: Parse num for AE number failed\n");
 		return -EINVAL;
 	}
-	if (!test_bit(*ae, (unsigned long *)&handle->hal_handle->ae_mask)) {
-		pr_err("QAT: ae %d to be init is fused off\n", *ae);
-		return -EINVAL;
-	}
 	if (*ae >= ICP_QAT_UCLO_MAX_AE) {
 		pr_err("QAT: ae %d out of range\n", *ae);
 		return -EINVAL;

@@ -456,7 +452,7 @@ static int qat_uclo_init_memory(struct icp_qat_fw_loader_handle *handle)
 			(sizeof(struct icp_qat_uof_memvar_attr) *
 			initmem->val_attr_num));
 	}
-	for (ae = 0; ae < ICP_QAT_UCLO_MAX_AE; ae++) {
+	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
 		if (qat_hal_batch_wr_lm(handle, ae,
 					obj_handle->lm_init_tab[ae])) {
 			pr_err("QAT: fail to batch init lmem for AE %d\n", ae);

index c5ce236..b707f29 100644
@@ -59,7 +59,7 @@
 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3
 #define ADF_DH895XCC_MAX_ACCELERATORS 6
 #define ADF_DH895XCC_MAX_ACCELENGINES 12
-#define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 18
+#define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 13
 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
 #define ADF_DH895XCC_LEGFUSE_OFFSET 0x4C