Audio clocks for sun[457]i, SoC revision detection
Subsystems (4)
Emilio López
maintainercover Audio clocks for sun[457]i, SoC revision detection
Hi everyone,
This series adds support for PLL2 on A10 rev B and higher, A10S, A13 and A20. It also includes support for the codec clock as well as module 1 clocks, used in the audio blocks. There's also two patches fixing sparse warnings on the driver.
I'm sending this as RFC as this does not support the A10 rev A PLL2 clock. It seems from the Allwinner code that rev A has a different register layout, and is programmed with different values. Unfortunately there's no mention of this on the User Manual, so I'm left to guess for the most part.
The clock code is not the only part in where rev A is special cased; there's some register writes just for it on the analog audio driver as well, so we probably need a way to support this in a generic way.
So, how should we proceed with this? Here are some ideas:
* Make different device trees with different compatibles. Pros:
not much extra code. Cons: we don't know the SoC revision on devices and/or they may change during the product lifecycle.
* Use different compatibles and change them on U-Boot. Pros: it keeps Linux simple. Cons: dependency on a newer bootloader.
* Use different compatibles and change them on early boot.
Pros: compatibility with existing bootloaders. Cons: Need code in Linux to fixup the DT
* Have a function "int sunxi_soc_revision(void)" that drivers can use to check which SoC revision they're running on.
Pros: no DT fixup. Cons: ugly and less portable if the driver ever needs to run on a non-sunxi platform.
* <your idea here>
I'd like to hear everyone's thoughts on this. From what I've seen around on LAKML, it seems the last option is the one in widest use, but I'd appreciate a confirmation. If this is the way forward, where should the code live in? The SoC detection is done by reading a register on the timer block on sun4i, and SID on sun5i.
As usual, all comments on the code are welcome as well.
Thanks!
Emilio
Emilio L?pez (8):
clk: sunxi: PLL2 support for sun4i, sun5i and sun7i
clk: sunxi: codec clock support
clk: sunxi: mod1 clock support
clk: sunxi: add __iomem markings to MMIO pointers
clk: sunxi: staticize structures and arrays
ARM: sunxi: Add PLL2 support
ARM: sunxi: Add codec clock support
ARM: sun7i: Add mod1 clock nodes
arch/arm/boot/dts/sun4i-a10.dtsi | 16 ++ arch/arm/boot/dts/sun5i-a10s.dtsi | 16 ++ arch/arm/boot/dts/sun5i-a13.dtsi | 16 ++ arch/arm/boot/dts/sun7i-a20.dtsi | 55 +++++++ drivers/clk/sunxi/Makefile | 3 + drivers/clk/sunxi/clk-a10-codec.c | 41 +++++ drivers/clk/sunxi/clk-a10-mod1.c | 69 +++++++++ drivers/clk/sunxi/clk-a10-pll2.c | 249 +++++++++++++++++++++++++++++++ drivers/clk/sunxi/clk-a20-gmac.c | 2 +- drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 2 +- drivers/clk/sunxi/clk-sun6i-apb0.c | 2 +- drivers/clk/sunxi/clk-sun6i-ar100.c | 4 +- drivers/clk/sunxi/clk-sun8i-apb0.c | 2 +- drivers/clk/sunxi/clk-sunxi.c | 10 +- 14 files changed, 476 insertions(+), 11 deletions(-) create mode 100644 drivers/clk/sunxi/clk-a10-codec.c create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c
Signature · 1 line
2.0.3
Emilio López
maintainerRFC 1/8 clk: sunxi: PLL2 support for sun4i, sun5i and sun7i
This patch adds support for PLL2 and derivates on A10 revision B and higher, as well as on sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates.
--- drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-a10-pll2.c | 249 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 250 insertions(+) create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c
drivers/clk/sunxi/Makefile +1 -0
@@ -4,6 +4,7 @@ obj-y += clk-sunxi.o clk-factors.o obj-y += clk-a10-hosc.o +obj-y += clk-a10-pll2.o obj-y += clk-a20-gmac.o obj-$(CONFIG_MFD_SUN6I_PRCM) += \
drivers/clk/sunxi/clk-a10-pll2.c new file +249 -0
249 lines not on this page · raw message
Signature · 1 line
2.0.3
Emilio López
maintainerRFC 2/8 clk: sunxi: codec clock support
In reply to Emilio LópezThe codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as parent.
--- drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-a10-codec.c | 41 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 drivers/clk/sunxi/clk-a10-codec.c
drivers/clk/sunxi/Makefile +1 -0
@@ -3,6 +3,7 @@ # obj-y += clk-sunxi.o clk-factors.o +obj-y += clk-a10-codec.o obj-y += clk-a10-hosc.o obj-y += clk-a10-pll2.o obj-y += clk-a20-gmac.o
drivers/clk/sunxi/clk-a10-codec.c new file +41 -0
41 lines not on this page · raw message
Signature · 1 line
2.0.3
RFC 2/8 clk: sunxi: codec clock support
Quoted 4 lines · Emilio L?pez
The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as parent.
Signed-off-by Emilio L?pez <[email protected]>
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140728/9ca4709e/attachment.sig>
Emilio López
maintainerRFC 3/8 clk: sunxi: mod1 clock support
In reply to Emilio LópezThe module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver.
---
As I have no clients for these clocks, this is untested. It would be great to get an ack from the guys working on IIS or SPDIF
drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-a10-mod1.c | 69 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c
drivers/clk/sunxi/Makefile +1 -0
@@ -5,6 +5,7 @@ obj-y += clk-sunxi.o clk-factors.o obj-y += clk-a10-codec.o obj-y += clk-a10-hosc.o +obj-y += clk-a10-mod1.o obj-y += clk-a10-pll2.o obj-y += clk-a20-gmac.o
drivers/clk/sunxi/clk-a10-mod1.c new file +69 -0
69 lines not on this page · raw message
Signature · 1 line
2.0.3
Emilio López
maintainerRFC 4/8 clk: sunxi: add __iomem markings to MMIO pointers
In reply to Emilio LópezThis commit adds __iomem thoughout the sunxi clock driver, in places where it was ommited. This cleans most of the sparse warnings we are getting here.
---
These are just non-critical fixes, they can wait until the next release if desired, although I feel they're trivial enough to go on -rc1 as well.
drivers/clk/sunxi/clk-a20-gmac.c | 2 +- drivers/clk/sunxi/clk-sunxi.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-)
drivers/clk/sunxi/clk-a20-gmac.c +1 -1
@@ -60,7 +60,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)struct clk_gate *gate;const char *clk_name = node->name;const char *parents[SUN7I_A20_GMAC_PARENTS ]; -void *reg; +void __iomem *reg;if (of_property_read_string (node,"clock-output-names" , &clk_name))return ;
drivers/clk/sunxi/clk-sunxi.c +5 -5
@@ -593,7 +593,7 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,struct clk_hw *mux_hw =NULL ;const char *clk_name = node->name;const char *parents[SUNXI_MAX_PARENTS ]; -void *reg; +void __iomem *reg;int i =0 ; reg =of_iomap (node,0 );
@@ -698,7 +698,7 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,struct clk *clk;const char *clk_name = node->name;const char *parents[SUNXI_MAX_PARENTS ]; -void *reg; +void __iomem *reg;int i =0 ; reg =of_iomap (node,0 );
@@ -780,7 +780,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,struct clk *clk;const char *clk_name = node->name;const char *clk_parent; -void *reg; +void __iomem *reg; reg =of_iomap (node,0 );
@@ -962,7 +962,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,struct gates_reset_data *reset_data;const char *clk_parent;const char *clk_name; -void *reg; +void __iomem *reg;int qty;int i =0 ;int j =0 ;
@@ -1084,7 +1084,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,struct clk_gate *gate =NULL ;struct clk_fixed_factor *fix_factor;struct clk_divider *divider; -void *reg; +void __iomem *reg;int i =0 ;int flags, clkflags;
Signature · 1 line
2.0.3
RFC 4/8 clk: sunxi: add __iomem markings to MMIO pointers
Quoted 5 lines · Emilio L?pez
This commit adds
__iomemthoughout the sunxi clock driver, in places where it was ommited. This cleans most of the sparse warnings we are getting here.Signed-off-by Emilio L?pez <[email protected]>
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140728/f336c99c/attachment-0001.sig>
RFC 4/8 clk: sunxi: add __iomem markings to MMIO pointers
Quoting Maxime Ripard (2014-07-28 06:21:18)
Quoted 8 lines · Emilio L?pez
Quoted 5 lines
This commit adds
__iomemthoughout the sunxi clock driver, in places where it was ommited. This cleans most of the sparse warnings we are getting here.Signed-off-by Emilio L?pez <[email protected]>Acked-by Maxime Ripard <[email protected]>
I've applied patches 4 & 5 to clk-next since they are useful fixes and you have already sent me a pull request for 3.17. Let me know if you would prefer for me to hold off on them for any reason.
Regards,
Mike
Quoted 7 lines
Maxime
Signature · 3 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
Emilio López
maintainerRFC 5/8 clk: sunxi: staticize structures and arrays
In reply to Emilio LópezThere are some structs and arrays on the driver that are not used anywhere else. Let's mark them as static.
---
These are just non-critical fixes, they can wait until the next release if desired, although I feel they're trivial enough to go on -rc1 as well.
drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 2 +- drivers/clk/sunxi/clk-sun6i-apb0.c | 2 +- drivers/clk/sunxi/clk-sun6i-ar100.c | 4 ++-- drivers/clk/sunxi/clk-sun8i-apb0.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-)
drivers/clk/sunxi/clk-sun6i-apb0-gates.c +1 -1
@@ -29,7 +29,7 @@ static const struct gates_data sun8i_a23_apb0_gates __initconst = { .mask = {0x5D}, }; -const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = { +static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = { { .compatible ="allwinner,sun6i-a31-apb0-gates-clk" , .data = &sun6i_a31_apb0_gates }, { .compatible ="allwinner,sun8i-a23-apb0-gates-clk" , .data = &sun8i_a23_apb0_gates }, { /* sentinel */ }
drivers/clk/sunxi/clk-sun6i-apb0.c +1 -1
@@ -57,7 +57,7 @@ static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev)return of_clk_add_provider (np, of_clk_src_simple_get, clk); } -const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = { +static const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = { { .compatible ="allwinner,sun6i-a31-apb0-clk" }, {/* sentinel */ } };
drivers/clk/sunxi/clk-sun6i-ar100.c +2 -2
@@ -160,7 +160,7 @@ static int ar100_set_rate(struct clk_hw *hw, unsigned long rate,return 0 ; } -struct clk_ops ar100_ops = { +static struct clk_ops ar100_ops = { .recalc_rate = ar100_recalc_rate, .determine_rate = ar100_determine_rate, .set_parent = ar100_set_parent,
@@ -213,7 +213,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)return of_clk_add_provider (np, of_clk_src_simple_get, clk); } -const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = { +static const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = { { .compatible ="allwinner,sun6i-a31-ar100-clk" }, {/* sentinel */ } };
drivers/clk/sunxi/clk-sun8i-apb0.c +1 -1
@@ -48,7 +48,7 @@ static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)return of_clk_add_provider (np, of_clk_src_simple_get, clk); } -const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = { +static const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = { { .compatible ="allwinner,sun8i-a23-apb0-clk" }, {/* sentinel */ } };
Signature · 1 line
2.0.3
RFC 5/8 clk: sunxi: staticize structures and arrays
Quoted 4 lines · Emilio L?pez
There are some structs and arrays on the driver that are not used anywhere else. Let's mark them as static.
Signed-off-by Emilio L?pez <[email protected]>
Thanks,
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140728/cdedde34/attachment-0001.sig>
Emilio López
maintainerRFC 6/8 ARM: sunxi: Add PLL2 support
In reply to Emilio LópezThis commit adds the PLL2 definition to the sun4i, sun5i and sun7i device trees. PLL2 is used to clock audio devices.
---
Note that there is no handling of A10 rev A here, this should not go in as-is.
arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++ arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 8 ++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 4 files changed, 32 insertions(+)
arch/arm/boot/dts/sun4i-a10.dtsi +8 -0
@@ -81,6 +81,14 @@ clock-output-names = "pll1"; }; + pll2: clk at 01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-b-pll2-clk"; + reg = <0x01c20008 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8"; + }; + pll4: clk at 01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk";
arch/arm/boot/dts/sun5i-a10s.dtsi +8 -0
@@ -74,6 +74,14 @@ clock-output-names = "pll1"; }; + pll2: clk at 01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-b-pll2-clk"; + reg = <0x01c20008 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8"; + }; + pll4: clk at 01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk";
arch/arm/boot/dts/sun5i-a13.dtsi +8 -0
@@ -75,6 +75,14 @@ clock-output-names = "pll1"; }; + pll2: clk at 01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-b-pll2-clk"; + reg = <0x01c20008 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8"; + }; + pll4: clk at 01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk";
arch/arm/boot/dts/sun7i-a20.dtsi +8 -0
@@ -91,6 +91,14 @@ clock-output-names = "pll1"; }; + pll2: clk at 01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-b-pll2-clk"; + reg = <0x01c20008 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8"; + }; + pll4: clk at 01c20018 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk";
Signature · 1 line
2.0.3
RFC 6/8 ARM: sunxi: Add PLL2 support
Quoted 20 lines · Emilio L?pez
This commit adds the PLL2 definition to the sun4i, sun5i and sun7i device trees. PLL2 is used to clock audio devices.
Not-signed-off-by Emilio L?pez <[email protected]>---
Note that there is no handling of A10 rev A here, this should not go in as-is.
arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++ arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 8 ++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 4 files changed, 32 insertions(+)arch/arm/boot/dts/sun4i-a10.dtsi +0
-0
arch/arm/boot/dts/sun4i-a10.dtsi line 89
Quoted 9 lines
arch/arm/boot/dts/sun4i-a10.dtsi +6
-0@@ -81,6 +81,14 @@ clock-output-names = "pll1"; }; + pll2: clk at 01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-b-pll2-clk"; + reg = <0x01c20008 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
Why don't you just declare the fixed factors as fixed factors? It would simplify greatly your driver, and be more accurate.
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140728/699da049/attachment-0001.sig>
Emilio López
maintainerRFC 7/8 ARM: sunxi: Add codec clock support
In reply to Emilio LópezThis commit adds the codec clock definition to the sun4i, sun5i and sun7i device trees. The codec clock is used in the analog codec block.
--- arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++ arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 8 ++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 4 files changed, 32 insertions(+)
arch/arm/boot/dts/sun4i-a10.dtsi +8 -0
@@ -339,6 +339,14 @@ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi3"; }; + + codec_clk: clk at 01c20140 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-codec-clk"; + reg = <0x01c20140 0x4>; + clocks = <&pll2 0>; + clock-output-names = "codec"; + }; }; soc at 01c00000 {
arch/arm/boot/dts/sun5i-a10s.dtsi +8 -0
@@ -293,6 +293,14 @@ clock-output-names = "usb_ohci0", "usb_phy"; }; + codec_clk: clk at 01c20140 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-codec-clk"; + reg = <0x01c20140 0x4>; + clocks = <&pll2 0>; + clock-output-names = "codec"; + }; + mbus_clk: clk at 01c2015c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk";
arch/arm/boot/dts/sun5i-a13.dtsi +8 -0
@@ -291,6 +291,14 @@ clock-output-names = "usb_ohci0", "usb_phy"; }; + codec_clk: clk at 01c20140 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-codec-clk"; + reg = <0x01c20140 0x4>; + clocks = <&pll2 0>; + clock-output-names = "codec"; + }; + mbus_clk: clk at 01c2015c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk";
arch/arm/boot/dts/sun7i-a20.dtsi +8 -0
@@ -352,6 +352,14 @@ clock-output-names = "spi3"; }; + codec_clk: clk at 01c20140 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-codec-clk"; + reg = <0x01c20140 0x4>; + clocks = <&pll2 0>; + clock-output-names = "codec"; + }; + mbus_clk: clk at 01c2015c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk";
Signature · 1 line
2.0.3
Emilio López
maintainerRFC 8/8 ARM: sun7i: Add mod1 clock nodes
In reply to Emilio LópezThis commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual.
---
As mentioned on an earlier patch, note that this is untested, and I only added them to sun7i. It'd be great if actual users of these clocks could comment :)
arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
arch/arm/boot/dts/sun7i-a20.dtsi +39 -0
@@ -335,6 +335,29 @@ clock-output-names = "ir1"; }; + iis0_clk: clk at 01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis0"; + }; + + ac97_clk: clk at 01c200bc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200bc 0x4>; + clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>; + clock-output-names = "ac97"; + }; + + spdif_clk: clk at 01c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "spdif"; + }; usb_clk: clk at 01c200cc { #clock-cells = <1>; #reset-cells = <1>;
@@ -352,6 +375,22 @@ clock-output-names = "spi3"; }; + iis1_clk: clk at 01c200d8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200d8 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis1"; + }; + + iis2_clk: clk at 01c200dc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200dc 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis2"; + }; + codec_clk: clk at 01c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-codec-clk";
Signature · 1 line
2.0.3
RFC 8/8 ARM: sun7i: Add mod1 clock nodes
Hi,
First I suggest adding "DT: " to the commit line of all the DT patches.
Quoted 18 lines · Emilio L?pez
This commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual.
Not-signed-off-by Emilio L?pez <[email protected]>---
As mentioned on an earlier patch, note that this is untested, and I only added them to sun7i. It'd be great if actual users of these clocks could comment :)
arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)arch/arm/boot/dts/sun7i-a20.dtsi +0
-0
arch/arm/boot/dts/sun7i-a20.dtsi line 342
Quoted 8 lines
arch/arm/boot/dts/sun7i-a20.dtsi +5
-0@@ -335,6 +335,29 @@ clock-output-names = "ir1"; }; + iis0_clk: clk at 01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
User manual says pll2x8, pll2x4, pll2x2, pll2 for all the the clocks. So the order here should be reversed. Same for the others.
Quoted 8 lines
arch/arm/boot/dts/sun7i-a20.dtsi +8
-0+ clock-output-names = "iis0"; + }; + + ac97_clk: clk at 01c200bc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200bc 0x4>; + clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>;
arch/arm/boot/dts/sun7i-a20.dtsi line 360
Quoted 10 lines
arch/arm/boot/dts/sun7i-a20.dtsi +10
-0+ clock-output-names = "ac97"; + }; + + spdif_clk: clk at 01c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "spdif"; + };
Newline. And the manuals don't have anything on the SPDIF clock, so I can't comment on it.
Quoted 17 lines
arch/arm/boot/dts/sun7i-a20.dtsi +10
-0usb_clk: clk at 01c200cc { #clock-cells = <1>; #reset-cells = <1>;@@ -352,6 +375,22 @@ clock-output-names = "spi3"; }; + iis1_clk: clk at 01c200d8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200d8 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis1"; + }; + + iis2_clk: clk at 01c200dc { + #clock-cells = <0>;
arch/arm/boot/dts/sun7i-a20.dtsi
Quoted 10 lines
arch/arm/boot/dts/sun7i-a20.dtsi +6
-1+ compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200dc 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis2"; + }; + codec_clk: clk at 01c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-codec-clk"; --
Apart from the title and the clock orders, everything looks good. Jon should test this with the above corrected.
Cheers
ChenYu
RFC 8/8 ARM: sun7i: Add mod1 clock nodes
Quoted 48 lines · Chen-Yu Tsai
Hi,
First I suggest adding "DT: " to the commit line of all the DT patches.
Quoted 18 lines · Emilio L?pez
This commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual.
Not-signed-off-by Emilio L?pez <[email protected]>---
As mentioned on an earlier patch, note that this is untested, and I only added them to sun7i. It'd be great if actual users of these clocks could comment :)
arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)arch/arm/boot/dts/sun7i-a20.dtsi +0
-0arch/arm/boot/dts/sun7i-a20.dtsi line 342
Quoted 8 lines
arch/arm/boot/dts/sun7i-a20.dtsi +5
-0@@ -335,6 +335,29 @@ clock-output-names = "ir1"; }; + iis0_clk: clk at 01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;User manual says pll2x8, pll2x4, pll2x2, pll2 for all the the clocks. So the order here should be reversed. Same for the others.
Quoted 13 lines
arch/arm/boot/dts/sun7i-a20.dtsi +13
-0+ clock-output-names = "iis0"; + }; + + ac97_clk: clk at 01c200bc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200bc 0x4>; + clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>; + clock-output-names = "ac97"; + }; + + spdif_clk: clk at 01c200c0 { + #clock-cells = <0>;
Quoted 8 lines
arch/arm/boot/dts/sun7i-a20.dtsi line 360
Quoted 5 lines
arch/arm/boot/dts/sun7i-a20.dtsi +5
-0+ compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "spdif"; + };Newline. And the manuals don't have anything on the SPDIF clock, so I can't comment on it.
We do have this much SPDIF doc.
http://linux-sunxi.org/SPDIF
Based on the Allwinner code I see no reason to think that the SPDIF clock varies from any of the other audio clocks. Who knows why they left SPDIF out of the manual.
Quoted 23 lines
Quoted 23 lines
arch/arm/boot/dts/sun7i-a20.dtsi +15
-0usb_clk: clk at 01c200cc { #clock-cells = <1>; #reset-cells = <1>;@@ -352,6 +375,22 @@ clock-output-names = "spi3"; }; + iis1_clk: clk at 01c200d8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200d8 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis1"; + }; + + iis2_clk: clk at 01c200dc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200dc 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis2"; + };
Quoted 8 lines
arch/arm/boot/dts/sun7i-a20.dtsi
Quoted 5 lines
arch/arm/boot/dts/sun7i-a20.dtsi +1
-1+ codec_clk: clk at 01c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-codec-clk"; --Apart from the title and the clock orders, everything looks good. Jon should test this with the above corrected.
I don't have i2s hardware available yet. Maybe by end of the week.
Quoted 4 lines
Cheers
ChenYu
Signature · 2 lines
Jon Smirl jonsmirl at gmail.com
RFC 8/8 ARM: sun7i: Add mod1 clock nodes
In reply to Emilio LópezQuoted 18 lines · Emilio L?pez
This commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual.
Not-signed-off-by Emilio L?pez <[email protected]>---
As mentioned on an earlier patch, note that this is untested, and I only added them to sun7i. It'd be great if actual users of these clocks could comment :)
arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)arch/arm/boot/dts/sun7i-a20.dtsi +0
-0
arch/arm/boot/dts/sun7i-a20.dtsi line 343
Quoted 9 lines
arch/arm/boot/dts/sun7i-a20.dtsi +6
-0@@ -335,6 +335,29 @@ clock-output-names = "ir1"; }; + iis0_clk: clk at 01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis0";
Usually, it's called i2s.
Otherwise, beside Chen-Yu's comment, it looks fine.
Maxime
Signature · 10 lines
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RFC 8/8 ARM: sun7i: Add mod1 clock nodes
Quoted 22 lines · Maxime Ripard
Quoted 21 lines · Emilio L?pez
This commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual.
Not-signed-off-by Emilio L?pez <[email protected]>---
As mentioned on an earlier patch, note that this is untested, and I only added them to sun7i. It'd be great if actual users of these clocks could comment :)
arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)arch/arm/boot/dts/sun7i-a20.dtsi +0
-0@@ -335,6 +335,29 @@ clock-output-names = "ir1"; };
Quoted 8 lines
arch/arm/boot/dts/sun7i-a20.dtsi line 343
Quoted 6 lines
arch/arm/boot/dts/sun7i-a20.dtsi +6
-0+ iis0_clk: clk at 01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis0";Usually, it's called i2s.
I'd preferred i2s, but Allwinner used iis everywhere in the manual. So which wins in the device tree?
Same issue happens with twi vs i2c.
Quoted 9 lines
Otherwise, beside Chen-Yu's comment, it looks fine.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Signature · 2 lines
Jon Smirl jonsmirl at gmail.com
RFC 8/8 ARM: sun7i: Add mod1 clock nodes
Quoted 33 lines · jonsmirl at gmail.com
Quoted 22 lines · Maxime Ripard
Quoted 21 lines · Emilio L?pez
This commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual.
Not-signed-off-by Emilio L?pez <[email protected]>---
As mentioned on an earlier patch, note that this is untested, and I only added them to sun7i. It'd be great if actual users of these clocks could comment :)
arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)arch/arm/boot/dts/sun7i-a20.dtsi +0
-0@@ -335,6 +335,29 @@ clock-output-names = "ir1"; };Quoted 8 lines
arch/arm/boot/dts/sun7i-a20.dtsi line 343
Quoted 6 lines
arch/arm/boot/dts/sun7i-a20.dtsi +6
-0+ iis0_clk: clk at 01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>; + clock-output-names = "iis0";Usually, it's called i2s.
Quoted 4 lines
I'd preferred i2s, but Allwinner used iis everywhere in the manual. So which wins in the device tree?
Same issue happens with twi vs i2c.
I'd say whatever is the most common, this is why we ended up using i2c instead of allwinner's twi, pinctrl over port controller, etc.
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140731/b9b3dd69/attachment.sig>
cover Audio clocks for sun[457]i, SoC revision detection
In reply to Emilio LópezHi Emilio,
Quoted 6 lines · Emilio L?pez
Hi everyone,
This series adds support for PLL2 on A10 rev B and higher, A10S, A13 and A20. It also includes support for the codec clock as well as module 1 clocks, used in the audio blocks. There's also two patches fixing sparse warnings on the driver.
And where is the SoC revision detection you were talking about ? :)
Quoted 5 lines
I'm sending this as RFC as this does not support the A10 rev A PLL2 clock. It seems from the Allwinner code that rev A has a different register layout, and is programmed with different values. Unfortunately there's no mention of this on the User Manual, so I'm left to guess for the most part.
Do you have any reference pointing this out?
Quoted 8 lines
The clock code is not the only part in where rev A is special cased; there's some register writes just for it on the analog audio driver as well, so we probably need a way to support this in a generic way.
So, how should we proceed with this? Here are some ideas:
* Make different device trees with different compatibles. Pros:
not much extra code. Cons: we don't know the SoC revision on devices and/or they may change during the product lifecycle.
Which makes it a pretty poor solution :)
Quoted 2 lines
* Use different compatibles and change them on U-Boot. Pros: it keeps Linux simple. Cons: dependency on a newer bootloader.
Which is a no-go.
Quoted 3 lines
* Use different compatibles and change them on early boot.
Pros: compatibility with existing bootloaders. Cons: Need code in Linux to fixup the DT
Plus, we don't need to care about having different DT, and let the user indentify which revision it has. I'm very much in favor of this solution. And it works for all the boards.
Quoted 4 lines
* Have a function "int
sunxi_soc_revision(void)" that drivers can use to check which SoC revision they're running on.
Pros: no DT fixup. Cons: ugly and less portable if the driver ever needs to run on a non-sunxi platform.
Yep.
Quoted 3 lines
I'd like to hear everyone's thoughts on this. From what I've seen around on LAKML, it seems the last option is the one in widest use, but I'd appreciate a confirmation.
Mostly for historical reason I'd say. All the newer platforms seem to handle this by fixing up the DT at the early stages.
Quoted 3 lines
If this is the way forward, where should the code live in? The SoC detection is done by reading a register on the timer block on sun4i, and SID on sun5i.
In mach-sunxi I'd say. I've started working on it a few weeks back, in order to use soc-device too, but it's pretty much wip for now.
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140728/1a7acfd7/attachment-0001.sig>
cover Audio clocks for sun[457]i, SoC revision detection
Quoted 49 lines · Maxime Ripard
Hi Emilio,
Quoted 6 lines · Emilio L?pez
Hi everyone,
This series adds support for PLL2 on A10 rev B and higher, A10S, A13 and A20. It also includes support for the codec clock as well as module 1 clocks, used in the audio blocks. There's also two patches fixing sparse warnings on the driver.
And where is the SoC revision detection you were talking about ? :)
Quoted 5 lines
I'm sending this as RFC as this does not support the A10 rev A PLL2 clock. It seems from the Allwinner code that rev A has a different register layout, and is programmed with different values. Unfortunately there's no mention of this on the User Manual, so I'm left to guess for the most part.
Do you have any reference pointing this out?
Quoted 8 lines
The clock code is not the only part in where rev A is special cased; there's some register writes just for it on the analog audio driver as well, so we probably need a way to support this in a generic way.
So, how should we proceed with this? Here are some ideas:
* Make different device trees with different compatibles. Pros:
not much extra code. Cons: we don't know the SoC revision on devices and/or they may change during the product lifecycle.Which makes it a pretty poor solution :)
Quoted 2 lines
* Use different compatibles and change them on U-Boot. Pros: it keeps Linux simple. Cons: dependency on a newer bootloader.
Which is a no-go.
Quoted 3 lines
* Use different compatibles and change them on early boot.
Pros: compatibility with existing bootloaders. Cons: Need code in Linux to fixup the DTPlus, we don't need to care about having different DT, and let the user indentify which revision it has. I'm very much in favor of this solution. And it works for all the boards.
Quoted 4 lines
* Have a function "int
sunxi_soc_revision(void)" that drivers can use to check which SoC revision they're running on.
Pros: no DT fixup. Cons: ugly and less portable if the driver ever needs to run on a non-sunxi platform.
Quoted 8 lines
Yep.
Quoted 3 lines
I'd like to hear everyone's thoughts on this. From what I've seen around on LAKML, it seems the last option is the one in widest use, but I'd appreciate a confirmation.
Mostly for historical reason I'd say. All the newer platforms seem to handle this by fixing up the DT at the early stages.
I thought we were going to do it like this..
http://lxr.free-electrons.com/source/arch/arm/mach-mvebu/board-v7.c#L71
The machine driver for the A10 would check the CPU revision and then alter the compatible strings as needed to create new ones that encode the chip revision level.
In this case it would look for "allwinner,sun4i-a10-codec" and then add a compatible string like "allwinner,sun4i-a10a-codec" to the front of the list so that it will be bound first.
Quoted 12 lines
Quoted 4 lines
If this is the way forward, where should the code live in? The SoC detection is done by reading a register on the timer block on sun4i, and SID on sun5i.
In mach-sunxi I'd say. I've started working on it a few weeks back, in order to use soc-device too, but it's pretty much wip for now.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Signature · 2 lines
Jon Smirl jonsmirl at gmail.com
cover Audio clocks for sun[457]i, SoC revision detection
Quoted 63 lines · jonsmirl at gmail.com
Quoted 49 lines · Maxime Ripard
Hi Emilio,
Quoted 6 lines · Emilio L?pez
Hi everyone,
This series adds support for PLL2 on A10 rev B and higher, A10S, A13 and A20. It also includes support for the codec clock as well as module 1 clocks, used in the audio blocks. There's also two patches fixing sparse warnings on the driver.
And where is the SoC revision detection you were talking about ? :)
Quoted 5 lines
I'm sending this as RFC as this does not support the A10 rev A PLL2 clock. It seems from the Allwinner code that rev A has a different register layout, and is programmed with different values. Unfortunately there's no mention of this on the User Manual, so I'm left to guess for the most part.
Do you have any reference pointing this out?
Quoted 8 lines
The clock code is not the only part in where rev A is special cased; there's some register writes just for it on the analog audio driver as well, so we probably need a way to support this in a generic way.
So, how should we proceed with this? Here are some ideas:
* Make different device trees with different compatibles. Pros:
not much extra code. Cons: we don't know the SoC revision on devices and/or they may change during the product lifecycle.Which makes it a pretty poor solution :)
Quoted 2 lines
* Use different compatibles and change them on U-Boot. Pros: it keeps Linux simple. Cons: dependency on a newer bootloader.
Which is a no-go.
Quoted 3 lines
* Use different compatibles and change them on early boot.
Pros: compatibility with existing bootloaders. Cons: Need code in Linux to fixup the DTPlus, we don't need to care about having different DT, and let the user indentify which revision it has. I'm very much in favor of this solution. And it works for all the boards.
Quoted 4 lines
* Have a function "int
sunxi_soc_revision(void)" that drivers can use to check which SoC revision they're running on.
Pros: no DT fixup. Cons: ugly and less portable if the driver ever needs to run on a non-sunxi platform.Quoted 8 lines
Yep.
Quoted 3 lines
I'd like to hear everyone's thoughts on this. From what I've seen around on LAKML, it seems the last option is the one in widest use, but I'd appreciate a confirmation.
Mostly for historical reason I'd say. All the newer platforms seem to handle this by fixing up the DT at the early stages.
I thought we were going to do it like this..
http://lxr.free-electrons.com/source/arch/arm/mach-mvebu/board-v7.c#L71
Quoted 7 lines
The machine driver for the A10 would check the CPU revision and then alter the compatible strings as needed to create new ones that encode the chip revision level.
In this case it would look for "allwinner,sun4i-a10-codec" and then add a compatible string like "allwinner,sun4i-a10a-codec" to the front of the list so that it will be bound first.
This is what I meant by "fixing up the DT at the early stages", sorry if it wasn't clear enough :)
Note that we don't add a new compatible, but replace it entirely.
Maxime
Signature · 10 lines
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