Audio clocks for sun[457]i, SoC revision detection

This commit adds SoC bus support on the sunxi platform, and exposes information such as the hardware revision to userspace and other kernel clients during init. A message with this information is also printed to the kernel log to ease future bug triaging.

Signed-off-by Emilio L?pez <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig        |   1 +
 arch/arm/mach-sunxi/Makefile       |   2 +-
 arch/arm/mach-sunxi/sunxi-soc-id.c | 226 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/sunxi-soc-id.h |   6 +
 4 files changed, 234 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-sunxi/sunxi-soc-id.c
 create mode 100644 arch/arm/mach-sunxi/sunxi-soc-id.h

arch/arm/mach-sunxi/Kconfig +1 -0

index 6434e3b..4a199df 100644
@@ -5,6 +5,7 @@ menuconfig ARCH_SUNXI
 	select GENERIC_IRQ_CHIP
 	select PINCTRL
 	select PINCTRL_SUNXI
+	select SOC_BUS
 	select SUN4I_TIMER
 
 if ARCH_SUNXI

arch/arm/mach-sunxi/Makefile +1 -1

index 27b168f..589239b 100644
@@ -1,2 +1,2 @@
-obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_ARCH_SUNXI) += sunxi.o sunxi-soc-id.o
 obj-$(CONFIG_SMP) += platsmp.o

arch/arm/mach-sunxi/sunxi-soc-id.c new file +68 -0

new file mode 100644
index 0000000..c7eff1c
@@ -0,0 +1,226 @@
+/*
+ * SoC revision detection for sunxi SoCs
+ *
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sys_soc.h>
+
+#include "sunxi-soc-id.h"
+
+/*
+ * On the A10 SoC, we can read the revision information from the timer
+ * block. The detection logic is extracted from similar code on the
+ * Allwinner vendor tree, as this is undocumented on the user manual
+ */
+
+#define TIMER_SOC_REV_REG		0x13c
+#define TIMER_SOC_REV_CLEAR(val)	((val) & ~(0x3 << 6))
+#define TIMER_SOC_REV_GET(val)		(((val) >> 6) & 0x3)
+
+static const struct of_device_id sun4i_timer_compatible[] __initconst = {
+	{ .compatible = "allwinner,sun4i-a10-timer", },
+	{},
+};
+
+static int __init sun4i_get_soc_revision(void)
+{
+	struct device_node *np;
+	void __iomem *base;
+	u32 val;
+	int ret;
+
+	/* Find the timer node */
+	np = of_find_matching_node(NULL, sun4i_timer_compatible);
+	if (!np)
+		return -ENODEV;
+
+	/* Temporarily map it for reading */
+	base = of_iomap(np, 0);
+	if (!base) {
+		of_node_put(np);
+		return -ENOMEM;
+	}
+
+	/* Clear the SoC revision bits and rewrite the register */
+	val = readl(base + TIMER_SOC_REV_REG);
+	val = TIMER_SOC_REV_CLEAR(val);
+	writel(val, base + TIMER_SOC_REV_REG);
+
+	/* Now read it again and see what shows up */

arch/arm/mach-sunxi/sunxi-soc-id.c new file +37 -0

+	}
+
+	iounmap(base);
+	of_node_put(np);
+
+	return ret;
+}
+
+/*
+ * On the sun5i SoCs (A10S, A13), we can read the revision information
+ * from the first bits in the Security ID. The detection logic is
+ * extracted from similar code on the Allwinner vendor tree, as this
+ * is undocumented on the user manual.
+ */
+
+static const struct of_device_id sun5i_sid_compatible[] __initconst = {
+	{ .compatible = "allwinner,sun4i-a10-sid", },
+	{},
+};
+
+static int __init sun5i_get_soc_revision(void)
+{
+	struct device_node *np;
+	void __iomem *sid;
+	u32 val;
+	int ret;
+
+	/* Find the SID node */
+	np = of_find_matching_node(NULL, sun5i_sid_compatible);
+	if (!np)
+		return -ENODEV;
+
+	/* Temporarily map it for reading */
+	sid = of_iomap(np, 0);
+	if (!sid) {
+		of_node_put(np);
+		return -ENOMEM;

arch/arm/mach-sunxi/sunxi-soc-id.c new file +33 -0

+		ret = 'A';
+		break;
+	case 0x162542: /* A10S/A13 rev B */
+		ret = 'B';
+		break;
+	default:       /* Unknown chip revision */
+		ret = -ENODATA;
+	}
+
+	iounmap(sid);
+	of_node_put(np);
+
+	return ret;
+}
+
+int __init sunxi_soc_revision(void)
+{
+	static int revision = -ENODEV;
+
+	/* Try to query the hardware just once */
+	if (!IS_ERR_VALUE(revision))
+		return revision;
+
+	if (of_machine_is_compatible("allwinner,sun4i-a10")) {
+		revision = sun4i_get_soc_revision();
+	} else if (of_machine_is_compatible("allwinner,sun5i-a10s") ||
+		   of_machine_is_compatible("allwinner,sun5i-a13")) {
+		revision = sun5i_get_soc_revision();
+	}
+
+	return revision;
+}
+

arch/arm/mach-sunxi/sunxi-soc-id.c new file +12 -0

+static int __init sunxi_register_soc_device(void)
+{
+	struct soc_device_attribute *soc_dev_attr;
+	struct soc_device *soc_dev;
+	const struct of_device_id *match;
+	struct device_node *root;
+	int revision;
+
+	/* Only run on sunxi SoCs that we know of */
+	root = of_find_node_by_path("/");
+	match = of_match_node(soc_matches, root);
+	if (!match)

arch/arm/mach-sunxi/sunxi-soc-id.c new file +10 -0

+
+	/* Revision may not always be available */
+	revision = sunxi_soc_revision();
+	if (IS_ERR_VALUE(revision))
+		soc_dev_attr->revision = kstrdup("Unknown", GFP_KERNEL);
+	else
+		soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c", revision);
+
+	soc_dev = soc_device_register(soc_dev_attr);
+	if (IS_ERR(soc_dev))

arch/arm/mach-sunxi/sunxi-soc-id.c new file +4 -0

+
+	return 0;
+
+free_struct:

Hi Emilio,

Quoted 113 lines · Emilio L?pez

This commit adds SoC bus support on the sunxi platform, and exposes information such as the hardware revision to userspace and other kernel clients during init. A message with this information is also printed to the kernel log to ease future bug triaging.

Signed-off-by Emilio L?pez <[email protected]>

---
  arch/arm/mach-sunxi/Kconfig        |   1 +
  arch/arm/mach-sunxi/Makefile       |   2 +-
  arch/arm/mach-sunxi/sunxi-soc-id.c | 226 +++++++++++++++++++++++++++++++++++++
  arch/arm/mach-sunxi/sunxi-soc-id.h |   6 +
  4 files changed, 234 insertions(+), 1 deletion(-)

create mode 100644 arch/arm/mach-sunxi/sunxi-soc-id.c create mode 100644 arch/arm/mach-sunxi/sunxi-soc-id.h

arch/arm/mach-sunxi/Kconfig +1 -0

index 6434e3b..4a199df 100644
@@ -5,6 +5,7 @@ menuconfig ARCH_SUNXI
  	select GENERIC_IRQ_CHIP
  	select PINCTRL
  	select PINCTRL_SUNXI
+	select SOC_BUS
  	select SUN4I_TIMER
 
  if ARCH_SUNXI

arch/arm/mach-sunxi/Makefile +1 -1

index 27b168f..589239b 100644
@@ -1,2 +1,2 @@
-obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_ARCH_SUNXI) += sunxi.o sunxi-soc-id.o
  obj-$(CONFIG_SMP) += platsmp.o

arch/arm/mach-sunxi/sunxi-soc-id.c new file +72 -0

new file mode 100644
index 0000000..c7eff1c
@@ -0,0 +1,226 @@
+/*
+ * SoC revision detection for sunxi SoCs
+ *
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sys_soc.h>
+
+#include "sunxi-soc-id.h"
+
+/*
+ * On the A10 SoC, we can read the revision information from the timer
+ * block. The detection logic is extracted from similar code on the
+ * Allwinner vendor tree, as this is undocumented on the user manual
+ */
+
+#define TIMER_SOC_REV_REG		0x13c
+#define TIMER_SOC_REV_CLEAR(val)	((val) & ~(0x3 << 6))
+#define TIMER_SOC_REV_GET(val)		(((val) >> 6) & 0x3)
+
+static const struct of_device_id sun4i_timer_compatible[] __initconst = {
+	{ .compatible = "allwinner,sun4i-a10-timer", },
+	{},
+};
+
+static int __init sun4i_get_soc_revision(void)
+{
+	struct device_node *np;
+	void __iomem *base;
+	u32 val;
+	int ret;
+
+	/* Find the timer node */
+	np = of_find_matching_node(NULL, sun4i_timer_compatible);
+	if (!np)
+		return -ENODEV;
+
+	/* Temporarily map it for reading */
+	base = of_iomap(np, 0);
+	if (!base) {
+		of_node_put(np);
+		return -ENOMEM;
+	}
+
+	/* Clear the SoC revision bits and rewrite the register */
+	val = readl(base + TIMER_SOC_REV_REG);
+	val = TIMER_SOC_REV_CLEAR(val);
+	writel(val, base + TIMER_SOC_REV_REG);
+
+	/* Now read it again and see what shows up */
+	val = readl(base + TIMER_SOC_REV_REG);
+	val = TIMER_SOC_REV_GET(val);
+
+	switch (val) {

arch/arm/mach-sunxi/sunxi-soc-id.c line 78

Quoted 6 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +6 -0

+	case 0:  /* revision A */
+		ret = 'A';
+	case 3:  /* revision B */
+		ret = 'B';
+	default: /* revision C */
+		ret = 'C';

What's programmed in there in the case of the rev C?

Quoted 41 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +41 -0

+	}
+
+	iounmap(base);
+	of_node_put(np);
+
+	return ret;
+}
+
+/*
+ * On the sun5i SoCs (A10S, A13), we can read the revision information
+ * from the first bits in the Security ID. The detection logic is
+ * extracted from similar code on the Allwinner vendor tree, as this
+ * is undocumented on the user manual.
+ */
+
+static const struct of_device_id sun5i_sid_compatible[] __initconst = {
+	{ .compatible = "allwinner,sun4i-a10-sid", },
+	{},
+};
+
+static int __init sun5i_get_soc_revision(void)
+{
+	struct device_node *np;
+	void __iomem *sid;
+	u32 val;
+	int ret;
+
+	/* Find the SID node */
+	np = of_find_matching_node(NULL, sun5i_sid_compatible);
+	if (!np)
+		return -ENODEV;
+
+	/* Temporarily map it for reading */
+	sid = of_iomap(np, 0);
+	if (!sid) {
+		of_node_put(np);
+		return -ENOMEM;
+	}
+
+	/* Read and extract the chip revision from the SID */
+	val = readl(sid);

arch/arm/mach-sunxi/sunxi-soc-id.c line 125

Quoted 6 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +6 -0

+	val = (val >> 8) & 0xffffff;
+
+	switch (val) {
+	case 0:        /* A10S/A13 rev A */
+	case 0x162541: /* A10S/A13 rev A */
+	case 0x162565: /* A13 rev A */

Some defines would be nice.

Also, isn't the SID supposed to identify any SoC, not just the sun5i?

Quoted 38 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +38 -0

+		ret = 'A';
+		break;
+	case 0x162542: /* A10S/A13 rev B */
+		ret = 'B';
+		break;
+	default:       /* Unknown chip revision */
+		ret = -ENODATA;
+	}
+
+	iounmap(sid);
+	of_node_put(np);
+
+	return ret;
+}
+
+int __init sunxi_soc_revision(void)
+{
+	static int revision = -ENODEV;
+
+	/* Try to query the hardware just once */
+	if (!IS_ERR_VALUE(revision))
+		return revision;
+
+	if (of_machine_is_compatible("allwinner,sun4i-a10")) {
+		revision = sun4i_get_soc_revision();
+	} else if (of_machine_is_compatible("allwinner,sun5i-a10s") ||
+		   of_machine_is_compatible("allwinner,sun5i-a13")) {
+		revision = sun5i_get_soc_revision();
+	}
+
+	return revision;
+}
+
+/* Matches for the sunxi SoCs we know of */
+static const struct of_device_id soc_matches[] __initconst = {
+	{ .compatible = "allwinner,sun4i-a10", .data = "A10 (sun4i)" },
+	{ .compatible = "allwinner,sun5i-a13", .data = "A13 (sun5i)" },
+	{ .compatible = "allwinner,sun5i-a10s", .data = "A10S (sun5i)" },

arch/arm/mach-sunxi/sunxi-soc-id.c line 168

Quoted 5 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +5 -0

+	{ .compatible = "allwinner,sun6i-a31", .data = "A31 (sun6i)" },
+	{ .compatible = "allwinner,sun7i-a20", .data = "A20 (sun7i)" },
+	{ .compatible = "allwinner,sun8i-a23", .data = "A23 (sun8i)" },
+	{ /* sentinel */ },
+};

Hmmm, no, either auto-detect it, or don't, but that's useless. We can already have the same information from the DT directly.

Quoted 5 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +5 -0

+static int __init sunxi_register_soc_device(void)
+{
+	struct soc_device_attribute *soc_dev_attr;
+	struct soc_device *soc_dev;
+	const struct of_device_id *match;

arch/arm/mach-sunxi/sunxi-soc-id.c line 182

Quoted 8 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +8 -0

+	struct device_node *root;
+	int revision;
+
+	/* Only run on sunxi SoCs that we know of */
+	root = of_find_node_by_path("/");
+	match = of_match_node(soc_matches, root);
+	if (!match)
+		goto exit;

arch/arm/mach-sunxi/sunxi-soc-id.c line 191

Quoted 9 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +9 -0

+
+	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+	if (!soc_dev_attr)
+		goto exit;
+
+	/* Read the machine name if available */
+	of_property_read_string(root, "model", &soc_dev_attr->machine);
+
+	soc_dev_attr->family = kstrdup("Allwinner A Series", GFP_KERNEL);

I think the family should be sun*i

arch/arm/mach-sunxi/sunxi-soc-id.c line 192

Quoted 2 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +1 -0

+	soc_dev_attr->soc_id = kstrdup(match->data, GFP_KERNEL);

And soc_id would be just the name of the SoC.

Quoted 14 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +14 -0

+
+	/* Revision may not always be available */
+	revision = sunxi_soc_revision();
+	if (IS_ERR_VALUE(revision))
+		soc_dev_attr->revision = kstrdup("Unknown", GFP_KERNEL);
+	else
+		soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c", revision);
+
+	soc_dev = soc_device_register(soc_dev_attr);
+	if (IS_ERR(soc_dev))
+		goto free_struct;
+
+	/*
+	 * Print an informational line mentioning the hardware details.

arch/arm/mach-sunxi/sunxi-soc-id.c line 212

Quoted 6 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +6 -0

+	 * It may come in handy during bug reports, as some early SoC
+	 * revisions have hardware quirks and do not get much testing.
+	 */
+	pr_info("SoC bus registered, running %s %s, revision %s\n",
+		soc_dev_attr->family, soc_dev_attr->soc_id,
+		soc_dev_attr->revision);

Maybe a pr_fmt would be nice here.

Quoted 9 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +9 -0

+
+	return 0;
+
+free_struct:
+	kfree(soc_dev_attr->family);
+	kfree(soc_dev_attr->soc_id);
+	kfree(soc_dev_attr->revision);
+	kfree(soc_dev_attr);
+exit:

arch/arm/mach-sunxi/sunxi-soc-id.c line 226

Quoted 5 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +5 -0

+	of_node_put(root);
+
+	return 0;
+}
+postcore_initcall(sunxi_register_soc_device)

I'm kind of reluctant to this. That would mean that it will run for every SoC.

Can't you tie it to the system controller, and have it probed as usual?

El 03/08/14 a las 09:40, Maxime Ripard escibi?:

Quoted 15 lines · Emilio L?pez

Quoted 14 lines

This commit adds SoC bus support on the sunxi platform, and exposes information such as the hardware revision to userspace and other kernel clients during init. A message with this information is also printed to the kernel log to ease future bug triaging.

Signed-off-by Emilio L?pez <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig        |   1 +
 arch/arm/mach-sunxi/Makefile       |   2 +-
 arch/arm/mach-sunxi/sunxi-soc-id.c | 226 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/sunxi-soc-id.h |   6 +
 4 files changed, 234 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-sunxi/sunxi-soc-id.c
 create mode 100644 arch/arm/mach-sunxi/sunxi-soc-id.h

Quoted 10 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 191

Quoted 8 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +8 -0

+	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+	if (!soc_dev_attr)
+		goto exit;
+
+	/* Read the machine name if available */
+	of_property_read_string(root, "model", &soc_dev_attr->machine);
+
+	soc_dev_attr->family = kstrdup("Allwinner A Series", GFP_KERNEL);

I think the family should be sun*i

Here is a list of the ones currently in use for family

"Cirrus Logic EP93xx"
"Freescale i.MX"
"Integrator"
"Marvell"
"Freescale MXS Family"
"Tegra"
"Xilinx Zynq"

There does not seem to be a real consensus on what these mean. There's a binding document on Documentation/ABI/testing/sysfs-devices-soc but it's not really detailed.

Quoted 4 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 192

Quoted 2 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +1 -0

+	soc_dev_attr->soc_id = kstrdup(match->data, GFP_KERNEL);

And soc_id would be just the name of the SoC.

According to the binding this is a serial number. Lee, could you help us decide what these fields should look like?

I'm now inclining to have eg. family=sun5i, machine=A13, keep revision the same and drop soc_id.

Hi Maxime,

Thanks for taking the time to review this :)

El 03/08/14 a las 09:40, Maxime Ripard escibi?:

Quoted 116 lines

Hi Emilio,

Quoted 113 lines · Emilio L?pez

This commit adds SoC bus support on the sunxi platform, and exposes information such as the hardware revision to userspace and other kernel clients during init. A message with this information is also printed to the kernel log to ease future bug triaging.

Signed-off-by Emilio L?pez <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig        |   1 +
 arch/arm/mach-sunxi/Makefile       |   2 +-
 arch/arm/mach-sunxi/sunxi-soc-id.c | 226 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/sunxi-soc-id.h |   6 +
 4 files changed, 234 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-sunxi/sunxi-soc-id.c
 create mode 100644 arch/arm/mach-sunxi/sunxi-soc-id.h

arch/arm/mach-sunxi/Kconfig +1 -0

index 6434e3b..4a199df 100644
@@ -5,6 +5,7 @@ menuconfig ARCH_SUNXI
 	select GENERIC_IRQ_CHIP
 	select PINCTRL
 	select PINCTRL_SUNXI
+	select SOC_BUS
 	select SUN4I_TIMER
 
 if ARCH_SUNXI

arch/arm/mach-sunxi/Makefile +1 -1

index 27b168f..589239b 100644
@@ -1,2 +1,2 @@
-obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_ARCH_SUNXI) += sunxi.o sunxi-soc-id.o
 obj-$(CONFIG_SMP) += platsmp.o

arch/arm/mach-sunxi/sunxi-soc-id.c new file +72 -0

new file mode 100644
index 0000000..c7eff1c
@@ -0,0 +1,226 @@
+/*
+ * SoC revision detection for sunxi SoCs
+ *
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sys_soc.h>
+
+#include "sunxi-soc-id.h"
+
+/*
+ * On the A10 SoC, we can read the revision information from the timer
+ * block. The detection logic is extracted from similar code on the
+ * Allwinner vendor tree, as this is undocumented on the user manual
+ */
+
+#define TIMER_SOC_REV_REG		0x13c
+#define TIMER_SOC_REV_CLEAR(val)	((val) & ~(0x3 << 6))
+#define TIMER_SOC_REV_GET(val)		(((val) >> 6) & 0x3)
+
+static const struct of_device_id sun4i_timer_compatible[] __initconst = {
+	{ .compatible = "allwinner,sun4i-a10-timer", },
+	{},
+};
+
+static int __init sun4i_get_soc_revision(void)
+{
+	struct device_node *np;
+	void __iomem *base;
+	u32 val;
+	int ret;
+
+	/* Find the timer node */
+	np = of_find_matching_node(NULL, sun4i_timer_compatible);
+	if (!np)
+		return -ENODEV;
+
+	/* Temporarily map it for reading */
+	base = of_iomap(np, 0);
+	if (!base) {
+		of_node_put(np);
+		return -ENOMEM;
+	}
+
+	/* Clear the SoC revision bits and rewrite the register */
+	val = readl(base + TIMER_SOC_REV_REG);
+	val = TIMER_SOC_REV_CLEAR(val);
+	writel(val, base + TIMER_SOC_REV_REG);
+
+	/* Now read it again and see what shows up */
+	val = readl(base + TIMER_SOC_REV_REG);
+	val = TIMER_SOC_REV_GET(val);
+
+	switch (val) {

Quoted 8 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 78

Quoted 6 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +6 -0

+	case 0:  /* revision A */
+		ret = 'A';
+	case 3:  /* revision B */
+		ret = 'B';
+	default: /* revision C */
+		ret = 'C';

What's programmed in there in the case of the rev C?

Something that's not a 3 or a 0 - I don't have any more specifics than what the Allwinner code does :(

https://github.com/linux-sunxi/linux-sunxi/blob/lichee-dev/arch/arm/mach-sun4i/core.c#L418

I just noticed that I forgot the breaks while reworking this from return to a variable, so everything is rev C right now - I'll fix that.

Quoted 41 lines

Quoted 41 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +41 -0

+	}
+
+	iounmap(base);
+	of_node_put(np);
+
+	return ret;
+}
+
+/*
+ * On the sun5i SoCs (A10S, A13), we can read the revision information
+ * from the first bits in the Security ID. The detection logic is
+ * extracted from similar code on the Allwinner vendor tree, as this
+ * is undocumented on the user manual.
+ */
+
+static const struct of_device_id sun5i_sid_compatible[] __initconst = {
+	{ .compatible = "allwinner,sun4i-a10-sid", },
+	{},
+};
+
+static int __init sun5i_get_soc_revision(void)
+{
+	struct device_node *np;
+	void __iomem *sid;
+	u32 val;
+	int ret;
+
+	/* Find the SID node */
+	np = of_find_matching_node(NULL, sun5i_sid_compatible);
+	if (!np)
+		return -ENODEV;
+
+	/* Temporarily map it for reading */
+	sid = of_iomap(np, 0);
+	if (!sid) {
+		of_node_put(np);
+		return -ENOMEM;
+	}
+
+	/* Read and extract the chip revision from the SID */
+	val = readl(sid);

Quoted 8 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 125

Quoted 6 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +6 -0

+	val = (val >> 8) & 0xffffff;
+
+	switch (val) {
+	case 0:        /* A10S/A13 rev A */
+	case 0x162541: /* A10S/A13 rev A */
+	case 0x162565: /* A13 rev A */

Some defines would be nice.

Ok

Quoted 1 line

Also, isn't the SID supposed to identify any SoC, not just the sun5i?

The Allwinner code I've seen uses the SS to detect the SoC (which luckily we don't need, as we have DT) and then reads the timer for sun4i or the SID for sun5i.

Quoted 39 lines

Quoted 39 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +38 -0

+		ret = 'A';
+		break;
+	case 0x162542: /* A10S/A13 rev B */
+		ret = 'B';
+		break;
+	default:       /* Unknown chip revision */
+		ret = -ENODATA;
+	}
+
+	iounmap(sid);
+	of_node_put(np);
+
+	return ret;
+}
+
+int __init sunxi_soc_revision(void)
+{
+	static int revision = -ENODEV;
+
+	/* Try to query the hardware just once */
+	if (!IS_ERR_VALUE(revision))
+		return revision;
+
+	if (of_machine_is_compatible("allwinner,sun4i-a10")) {
+		revision = sun4i_get_soc_revision();
+	} else if (of_machine_is_compatible("allwinner,sun5i-a10s") ||
+		   of_machine_is_compatible("allwinner,sun5i-a13")) {
+		revision = sun5i_get_soc_revision();
+	}
+
+	return revision;
+}
+
+/* Matches for the sunxi SoCs we know of */
+static const struct of_device_id soc_matches[] __initconst = {
+	{ .compatible = "allwinner,sun4i-a10", .data = "A10 (sun4i)" },
+	{ .compatible = "allwinner,sun5i-a13", .data = "A13 (sun5i)" },
+	{ .compatible = "allwinner,sun5i-a10s", .data = "A10S (sun5i)" },

Quoted 8 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 168

Quoted 5 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +5 -0

+	{ .compatible = "allwinner,sun6i-a31", .data = "A31 (sun6i)" },
+	{ .compatible = "allwinner,sun7i-a20", .data = "A20 (sun7i)" },
+	{ .compatible = "allwinner,sun8i-a23", .data = "A23 (sun8i)" },
+	{ /* sentinel */ },
+};

Hmmm, no, either auto-detect it, or don't, but that's useless. We can already have the same information from the DT directly.

I don't quite get what you're trying to say here. This is here to
a) get a fancy string saying what the SoC is (AFAIK that's not directly available on the DT)
b) only run in the listed SoCs

Quoted 5 lines

Quoted 5 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +5 -0

+static int __init sunxi_register_soc_device(void)
+{
+	struct soc_device_attribute *soc_dev_attr;
+	struct soc_device *soc_dev;
+	const struct of_device_id *match;

Quoted 8 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 182

Quoted 8 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +8 -0

+	struct device_node *root;
+	int revision;
+
+	/* Only run on sunxi SoCs that we know of */
+	root = of_find_node_by_path("/");
+	match = of_match_node(soc_matches, root);
+	if (!match)
+		goto exit;

See here

Quoted 11 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 191

Quoted 9 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +9 -0

+
+	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+	if (!soc_dev_attr)
+		goto exit;
+
+	/* Read the machine name if available */
+	of_property_read_string(root, "model", &soc_dev_attr->machine);
+
+	soc_dev_attr->family = kstrdup("Allwinner A Series", GFP_KERNEL);

I think the family should be sun*i

Here is a list of the ones currently in use for family

"Cirrus Logic EP93xx"
"Freescale i.MX"
"Integrator"
"Marvell"
"Freescale MXS Family"
"Tegra"
"Xilinx Zynq"

There does not seem to be a real consensus on what these mean. There's a binding document on Documentation/ABI/testing/sysfs-devices-soc but it's not really detailed.

Quoted 4 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 192

Quoted 2 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +1 -0

+	soc_dev_attr->soc_id = kstrdup(match->data, GFP_KERNEL);

And soc_id would be just the name of the SoC.

According to the binding this is a serial number. Lee, could you help us decide what these fields should look like?

I'm now inclining to have eg. family=sun5i, machine=A13, keep revision the same and drop soc_id.

Quoted 15 lines

Quoted 15 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +14 -0

+
+	/* Revision may not always be available */
+	revision = sunxi_soc_revision();
+	if (IS_ERR_VALUE(revision))
+		soc_dev_attr->revision = kstrdup("Unknown", GFP_KERNEL);
+	else
+		soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c", revision);
+
+	soc_dev = soc_device_register(soc_dev_attr);
+	if (IS_ERR(soc_dev))
+		goto free_struct;
+
+	/*
+	 * Print an informational line mentioning the hardware details.

Quoted 8 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 212

Quoted 6 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +6 -0

+	 * It may come in handy during bug reports, as some early SoC
+	 * revisions have hardware quirks and do not get much testing.
+	 */
+	pr_info("SoC bus registered, running %s %s, revision %s\n",
+		soc_dev_attr->family, soc_dev_attr->soc_id,
+		soc_dev_attr->revision);

Maybe a pr_fmt would be nice here.

With something like "Allwinner SoC bus"?

Quoted 10 lines

Quoted 10 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +9 -0

+
+	return 0;
+
+free_struct:
+	kfree(soc_dev_attr->family);
+	kfree(soc_dev_attr->soc_id);
+	kfree(soc_dev_attr->revision);
+	kfree(soc_dev_attr);
+exit:

Quoted 8 lines

arch/arm/mach-sunxi/sunxi-soc-id.c line 226

Quoted 5 lines

arch/arm/mach-sunxi/sunxi-soc-id.c new file +5 -0

+	of_node_put(root);
+
+	return 0;
+}
+postcore_initcall(sunxi_register_soc_device)

I'm kind of reluctant to this. That would mean that it will run for every SoC.

The overhead should be negligible - on non-sunxi, it will only check if the machine is compatible by looking at the root node and bail out as it's not the case.

Quoted 2 lines

Can't you tie it to the system controller, and have it probed as usual?

I considered tying this to init_machine, right before the DT starts to get probed. That would mean actually writing init_machine hooks calling into this for some of our machines, and getting us further from the generic DT machine nirvana though. As the quirk bits do not directly depend on this, we can probably get away with making this a normal
driver compatible with all our SoCs. Let me know which way do you prefer, and I'll be happy to oblige.

Currently, some hardware revisions of sunxi SoCs need special care on some blocks because of hardware differences and/or bugs. Unfortunately, it is unfeasible to account for these issues directly when writing the device tree, as SoC revision can vary between different units of the same device. This commit introduces a place to adjust DT compatibles as needed to work around said issues before devices are probed. To demonstrate usage, two quirks are added for the PLL2 and audio codec on sun4i.

Signed-off-by Emilio L?pez <[email protected]>

---
 arch/arm/mach-sunxi/Makefile |  2 +-
 arch/arm/mach-sunxi/quirks.c | 82 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 83 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-sunxi/quirks.c

arch/arm/mach-sunxi/Makefile +1 -1

index 589239b..7c13f99 100644
@@ -1,2 +1,2 @@
-obj-$(CONFIG_ARCH_SUNXI) += sunxi.o sunxi-soc-id.o
+obj-$(CONFIG_ARCH_SUNXI) += sunxi.o sunxi-soc-id.o quirks.o
 obj-$(CONFIG_SMP) += platsmp.o

arch/arm/mach-sunxi/quirks.c new file +72 -0

new file mode 100644
index 0000000..99cdaa0
@@ -0,0 +1,82 @@
+/*
+ * Runtime quirk handling for sunxi SoCs
+ *
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include "sunxi-soc-id.h"
+
+static int __init update_compatible_string(const char *oldc, const char *newc)
+{
+	int count = 0;
+	struct property *newprop;
+	size_t newlen = strlen(newc);
+	struct device_node *np = NULL;
+
+	for_each_compatible_node(np, NULL, oldc) {
+		newprop = kzalloc(sizeof(*newprop), GFP_KERNEL);
+		if (!newprop)
+			return -ENOMEM;
+
+		newprop->name = kstrdup("compatible", GFP_KERNEL);
+		newprop->value = kstrdup(newc, GFP_KERNEL);
+		newprop->length = newlen;
+
+		if (!newprop->name || !newprop->value) {
+			kfree(newprop);
+			return -ENOMEM;
+		}
+
+		of_update_property(np, newprop);
+		count++;
+	}
+
+	return count;
+}
+
+static void __init sun4i_pll2_quirk(void)
+{
+	/* Only revision A is affected */
+	if (sunxi_soc_revision() != 'A')
+		return;
+
+	WARN_ON(!update_compatible_string("allwinner,sun4i-a10-b-pll2",
+					  "allwinner,sun4i-a10-a-pll2"));
+}
+
+static void __init sun4i_codec_quirk(void)
+{
+	/* Only revision A is affected */
+	if (sunxi_soc_revision() != 'A')
+		return;
+
+	WARN_ON(!update_compatible_string("allwinner,sun4i-a10-b-codec",
+					  "allwinner,sun4i-a10-a-codec"));
+}
+

Quoted 11 lines

Currently, some hardware revisions of sunxi SoCs need special care on some blocks because of hardware differences and/or bugs. Unfortunately, it is unfeasible to account for these issues directly when writing the device tree, as SoC revision can vary between different units of the same device. This commit introduces a place to adjust DT compatibles as needed to work around said issues before devices are probed. To demonstrate usage, two quirks are added for the PLL2 and audio codec on sun4i.

Signed-off-by Emilio L?pez <[email protected]>

---

Quoted 5 lines

arch/arm/mach-sunxi/quirks.c new file +5 -0

+static int __init sunxi_apply_quirks(void)
+{
+	if (of_machine_is_compatible("allwinner,sun4i-a10")) {
+		sun4i_pll2_quirk();
+		sun4i_codec_quirk();

arch/arm/mach-sunxi/quirks.c line 82

Quoted 5 lines

arch/arm/mach-sunxi/quirks.c new file +5 -0

+	}
+
+	return 0;
+}
+postcore_initcall(sunxi_apply_quirks)

Have you tested it? My guess is that it wolud have to run *much* sooner, before of_platform_populate to be effective.

Hi Maxime,

El 03/08/14 a las 09:42, Maxime Ripard escibi?:

Quoted 12 lines · Emilio L?pez

Quoted 11 lines

Currently, some hardware revisions of sunxi SoCs need special care on some blocks because of hardware differences and/or bugs. Unfortunately, it is unfeasible to account for these issues directly when writing the device tree, as SoC revision can vary between different units of the same device. This commit introduces a place to adjust DT compatibles as needed to work around said issues before devices are probed. To demonstrate usage, two quirks are added for the PLL2 and audio codec on sun4i.

Signed-off-by Emilio L?pez <[email protected]>

---

(...)

Quoted 5 lines

Quoted 5 lines

arch/arm/mach-sunxi/quirks.c new file +5 -0

+static int __init sunxi_apply_quirks(void)
+{
+	if (of_machine_is_compatible("allwinner,sun4i-a10")) {
+		sun4i_pll2_quirk();
+		sun4i_codec_quirk();

Quoted 8 lines

arch/arm/mach-sunxi/quirks.c line 82

Quoted 5 lines

arch/arm/mach-sunxi/quirks.c new file +5 -0

+	}
+
+	return 0;
+}
+postcore_initcall(sunxi_apply_quirks)

Have you tested it? My guess is that it wolud have to run *much* sooner, before of_platform_populate to be effective.

I have, I was able to break my UART with it :)

of_platform_populate() is called from arch/arm/kernel/setup.c on arch_initcall. From include/linux/init.h

...

#define postcore_initcall(fn)           __define_initcall(fn, 2)
#define postcore_initcall_sync(fn)      __define_initcall(fn, 2s)
#define arch_initcall(fn)               __define_initcall(fn, 3)

...

So it should be fine.

The sun6i SMP ops are currently not marked as static, as reported by sparse. Let's mark it as such.

Signed-off-by Emilio L?pez <[email protected]>

This patch adds support for PLL2 and derivates on sun4i, sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates.

Signed-off-by Emilio L?pez <[email protected]>

---

Changes from RFC:
* Add support for A10 rev. A
* Document compatibles
* Use fixed factors

 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile                        |   1 +
 drivers/clk/sunxi/clk-a10-pll2.c                  | 243 ++++++++++++++++++++++
 3 files changed, 246 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c

Documentation/devicetree/bindings/clock/sunxi.txt +2 -0

index d3a5c3c..41ada31 100644
@@ -10,6 +10,8 @@ Required properties:
 	"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
 	"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
 	"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+	"allwinner,sun4i-a10-a-pll2-clk" - for the PLL2 clock on A10 rev. A
+	"allwinner,sun4i-a10-b-pll2-clk" - for the PLL2 clock on A10 rev. B
 	"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
 	"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
 	"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31

drivers/clk/sunxi/Makefile +1 -0

index 6850cba..dcd5709 100644
@@ -4,6 +4,7 @@
 
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
+obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \

drivers/clk/sunxi/clk-a10-pll2.c new file +217 -0

new file mode 100644
index 0000000..bcf7d0b
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define SUN4I_PLL2_ENABLE		31
+#define SUN4I_PLL2_A_VCOBIAS		0
+#define SUN4I_PLL2_A_VCOBIAS_MASK	0x1F
+#define SUN4I_PLL2_A_N			7
+#define SUN4I_PLL2_A_N_MASK		0x7F
+#define SUN4I_PLL2_B_POST_DIV		26
+#define SUN4I_PLL2_B_POST_DIV_MASK	0xF
+#define SUN4I_PLL2_B_N			8
+#define SUN4I_PLL2_B_N_MASK		0x7F
+#define SUN4I_PLL2_B_PRE_DIV		0
+#define SUN4I_PLL2_B_PRE_DIV_MASK	0x1F
+
+#define SUN4I_PLL2_OUTPUTS		4
+
+struct sun4i_pll2_clk {
+	struct clk_hw hw;
+	void __iomem *reg;
+};
+
+static inline struct sun4i_pll2_clk *to_sun4i_pll2_clk(struct clk_hw *hw)
+{
+	return container_of(hw, struct sun4i_pll2_clk, hw);
+}
+
+static unsigned long sun4i_pll2_recalc_rate_a(struct clk_hw *hw,
+					      unsigned long parent_rate)
+{
+	struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+	int vcobias, n;
+	u32 val;
+
+	val = readl(clk->reg);
+	vcobias = (val >> SUN4I_PLL2_A_VCOBIAS) & SUN4I_PLL2_A_VCOBIAS_MASK;
+	n = (val >> SUN4I_PLL2_A_N) & SUN4I_PLL2_A_N_MASK;
+
+	if (vcobias == 10 && n == 94)
+		return 22579200;
+	else if (vcobias == 9 && n == 83)
+		return 24576000;
+
+	/*
+	 * Unfortunately we don't really have much documentation on how
+	 * these factors relate mathematically
+	 */
+	return 0;
+}
+
+static unsigned long sun4i_pll2_recalc_rate_b(struct clk_hw *hw,
+					      unsigned long parent_rate)
+{
+	struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+	int n, prediv, postdiv;
+	u32 val;
+
+	val = readl(clk->reg);
+	n = (val >> SUN4I_PLL2_B_N) & SUN4I_PLL2_B_N_MASK;
+	prediv = (val >> SUN4I_PLL2_B_PRE_DIV) & SUN4I_PLL2_B_PRE_DIV_MASK;
+	postdiv = (val >> SUN4I_PLL2_B_POST_DIV) & SUN4I_PLL2_B_POST_DIV_MASK;
+
+	/* 0 is a special case and means 1 */
+	if (n == 0)
+		n = 1;
+	if (prediv == 0)
+		prediv = 1;
+	if (postdiv == 0)
+		postdiv = 1;
+
+	return ((parent_rate * n) / prediv) / postdiv;
+}
+
+static long sun4i_pll2_round_rate(struct clk_hw *hw, unsigned long rate,
+				  unsigned long *parent_rate)
+{
+	/*
+	 * There is only two interesting rates for the audio PLL, the
+	 * rest isn't really usable due to accuracy concerns. Therefore,
+	 * we specifically round to those rates here
+	 */
+	if (rate < 22579200)
+		return -EINVAL;
+
+	if (rate >= 22579200 && rate < 24576000)
+		return 22579200;
+
+	return 24576000;
+}
+
+static int sun4i_pll2_set_rate_a(struct clk_hw *hw, unsigned long rate,
+				 unsigned long parent_rate)
+{
+	struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+	u32 val = readl(clk->reg);
+
+	val &= ~(SUN4I_PLL2_A_VCOBIAS_MASK << SUN4I_PLL2_A_VCOBIAS);
+	val &= ~(SUN4I_PLL2_A_N_MASK << SUN4I_PLL2_A_N);
+
+	if (rate == 22579200)
+		val |= (10 << SUN4I_PLL2_A_VCOBIAS) | (94 << SUN4I_PLL2_A_N);
+	else if (rate == 24576000)
+		val |= (9 << SUN4I_PLL2_A_VCOBIAS) | (83 << SUN4I_PLL2_A_N);
+	else
+		return -EINVAL;
+
+	writel(val, clk->reg);
+
+	return 0;
+}
+
+static int sun4i_pll2_set_rate_b(struct clk_hw *hw, unsigned long rate,
+				 unsigned long parent_rate)
+{
+	struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+	u32 val = readl(clk->reg);
+
+	val &= ~(SUN4I_PLL2_B_N_MASK << SUN4I_PLL2_B_N);
+	val &= ~(SUN4I_PLL2_B_PRE_DIV_MASK << SUN4I_PLL2_B_PRE_DIV);
+	val &= ~(SUN4I_PLL2_B_POST_DIV_MASK << SUN4I_PLL2_B_POST_DIV);
+
+	val |= (21 << SUN4I_PLL2_B_PRE_DIV) | (4 << SUN4I_PLL2_B_POST_DIV);
+
+	if (rate == 22579200)
+		val |= (79 << SUN4I_PLL2_B_N);
+	else if (rate == 24576000)
+		val |= (86 << SUN4I_PLL2_B_N);
+	else
+		return -EINVAL;
+
+	writel(val, clk->reg);
+
+	return 0;
+}
+
+static const struct clk_ops sun4i_pll2_ops_a = {
+	.recalc_rate = sun4i_pll2_recalc_rate_a,
+	.round_rate = sun4i_pll2_round_rate,
+	.set_rate = sun4i_pll2_set_rate_a,
+};
+
+
+static const struct clk_ops sun4i_pll2_ops_b = {
+	.recalc_rate = sun4i_pll2_recalc_rate_b,
+	.round_rate = sun4i_pll2_round_rate,
+	.set_rate = sun4i_pll2_set_rate_b,
+};
+
+static const struct of_device_id pll2_matches[] __initconst = {
+	{ .compatible = "allwinner,sun4i-a10-a-pll2-clk", .data = &sun4i_pll2_ops_a },
+	{ .compatible = "allwinner,sun4i-a10-b-pll2-clk", .data = &sun4i_pll2_ops_b },
+	{ /* sentinel */ },
+};
+
+static void __init sun4i_pll2_setup(struct device_node *np)
+{
+	const char *clk_name = np->name, *parent;
+	const struct of_device_id *match;
+	struct clk_onecell_data *clk_data;
+	const struct clk_ops *pll2_ops;
+	struct sun4i_pll2_clk *pll2;
+	struct clk_gate *gate;
+	struct clk **clks;
+	void __iomem *reg;
+
+	/* Choose the correct ops for pll2 */
+	match = of_match_node(pll2_matches, np);
+	pll2_ops = match->data;
+
+	pll2 = kzalloc(sizeof(*pll2), GFP_KERNEL);
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+	clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(*clks), GFP_KERNEL);
+	if (!pll2 || !gate || !clk_data || !clks)
+		goto free_mem;
+
+	reg = of_iomap(np, 0);
+	parent = of_clk_get_parent_name(np, 0);
+	of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+
+	pll2->reg = reg;
+	gate->reg = reg;
+	gate->bit_idx = SUN4I_PLL2_ENABLE;
+
+	/* PLL2, also known as PLL2x1 */
+	of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+	clks[0] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
+					 &pll2->hw, pll2_ops,
+					 &gate->hw, &clk_gate_ops, 0);
+	WARN_ON(IS_ERR(clks[0]));
+	clk_set_rate(clks[0], 22579200);
+	parent = clk_name;
+
+	/* PLL2x2, 1/4 the rate of PLL2x8 */
+	of_property_read_string_index(np, "clock-output-names", 1, &clk_name);
+	clks[1] = clk_register_fixed_factor(NULL, clk_name, parent,
+					    CLK_SET_RATE_PARENT, 2, 1);
+	WARN_ON(IS_ERR(clks[1]));
+

Quoted 271 lines · Emilio L?pez

This patch adds support for PLL2 and derivates on sun4i, sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates.

Signed-off-by Emilio L?pez <[email protected]>

---

Changes from RFC:
* Add support for A10 rev. A
* Document compatibles
* Use fixed factors

 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile                        |   1 +
 drivers/clk/sunxi/clk-a10-pll2.c                  | 243 ++++++++++++++++++++++
 3 files changed, 246 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c

Documentation/devicetree/bindings/clock/sunxi.txt +2 -0

index d3a5c3c..41ada31 100644
@@ -10,6 +10,8 @@ Required properties:
      "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
      "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
      "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+     "allwinner,sun4i-a10-a-pll2-clk" - for the PLL2 clock on A10 rev. A
+     "allwinner,sun4i-a10-b-pll2-clk" - for the PLL2 clock on A10 rev. B
      "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
      "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
      "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31

drivers/clk/sunxi/Makefile +1 -0

index 6850cba..dcd5709 100644
@@ -4,6 +4,7 @@
 
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
+obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \

drivers/clk/sunxi/clk-a10-pll2.c new file +222 -0

new file mode 100644
index 0000000..bcf7d0b
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define SUN4I_PLL2_ENABLE            31
+#define SUN4I_PLL2_A_VCOBIAS         0
+#define SUN4I_PLL2_A_VCOBIAS_MASK    0x1F
+#define SUN4I_PLL2_A_N                       7
+#define SUN4I_PLL2_A_N_MASK          0x7F
+#define SUN4I_PLL2_B_POST_DIV                26
+#define SUN4I_PLL2_B_POST_DIV_MASK   0xF
+#define SUN4I_PLL2_B_N                       8
+#define SUN4I_PLL2_B_N_MASK          0x7F
+#define SUN4I_PLL2_B_PRE_DIV         0
+#define SUN4I_PLL2_B_PRE_DIV_MASK    0x1F
+
+#define SUN4I_PLL2_OUTPUTS           4
+
+struct sun4i_pll2_clk {
+     struct clk_hw hw;
+     void __iomem *reg;
+};
+
+static inline struct sun4i_pll2_clk *to_sun4i_pll2_clk(struct clk_hw *hw)
+{
+     return container_of(hw, struct sun4i_pll2_clk, hw);
+}
+
+static unsigned long sun4i_pll2_recalc_rate_a(struct clk_hw *hw,
+                                           unsigned long parent_rate)
+{
+     struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+     int vcobias, n;
+     u32 val;
+
+     val = readl(clk->reg);
+     vcobias = (val >> SUN4I_PLL2_A_VCOBIAS) & SUN4I_PLL2_A_VCOBIAS_MASK;
+     n = (val >> SUN4I_PLL2_A_N) & SUN4I_PLL2_A_N_MASK;
+
+     if (vcobias == 10 && n == 94)
+             return 22579200;
+     else if (vcobias == 9 && n == 83)
+             return 24576000;
+
+     /*
+      * Unfortunately we don't really have much documentation on how
+      * these factors relate mathematically
+      */
+     return 0;
+}
+
+static unsigned long sun4i_pll2_recalc_rate_b(struct clk_hw *hw,
+                                           unsigned long parent_rate)
+{
+     struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+     int n, prediv, postdiv;
+     u32 val;
+
+     val = readl(clk->reg);
+     n = (val >> SUN4I_PLL2_B_N) & SUN4I_PLL2_B_N_MASK;
+     prediv = (val >> SUN4I_PLL2_B_PRE_DIV) & SUN4I_PLL2_B_PRE_DIV_MASK;
+     postdiv = (val >> SUN4I_PLL2_B_POST_DIV) & SUN4I_PLL2_B_POST_DIV_MASK;
+
+     /* 0 is a special case and means 1 */
+     if (n == 0)
+             n = 1;
+     if (prediv == 0)
+             prediv = 1;
+     if (postdiv == 0)
+             postdiv = 1;
+
+     return ((parent_rate * n) / prediv) / postdiv;
+}
+
+static long sun4i_pll2_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *parent_rate)
+{
+     /*
+      * There is only two interesting rates for the audio PLL, the
+      * rest isn't really usable due to accuracy concerns. Therefore,
+      * we specifically round to those rates here
+      */
+     if (rate < 22579200)
+             return -EINVAL;
+
+     if (rate >= 22579200 && rate < 24576000)
+             return 22579200;
+
+     return 24576000;
+}
+
+static int sun4i_pll2_set_rate_a(struct clk_hw *hw, unsigned long rate,
+                              unsigned long parent_rate)
+{
+     struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+     u32 val = readl(clk->reg);
+
+     val &= ~(SUN4I_PLL2_A_VCOBIAS_MASK << SUN4I_PLL2_A_VCOBIAS);
+     val &= ~(SUN4I_PLL2_A_N_MASK << SUN4I_PLL2_A_N);
+
+     if (rate == 22579200)
+             val |= (10 << SUN4I_PLL2_A_VCOBIAS) | (94 << SUN4I_PLL2_A_N);
+     else if (rate == 24576000)
+             val |= (9 << SUN4I_PLL2_A_VCOBIAS) | (83 << SUN4I_PLL2_A_N);
+     else
+             return -EINVAL;
+
+     writel(val, clk->reg);
+
+     return 0;
+}
+
+static int sun4i_pll2_set_rate_b(struct clk_hw *hw, unsigned long rate,
+                              unsigned long parent_rate)
+{
+     struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+     u32 val = readl(clk->reg);
+
+     val &= ~(SUN4I_PLL2_B_N_MASK << SUN4I_PLL2_B_N);
+     val &= ~(SUN4I_PLL2_B_PRE_DIV_MASK << SUN4I_PLL2_B_PRE_DIV);
+     val &= ~(SUN4I_PLL2_B_POST_DIV_MASK << SUN4I_PLL2_B_POST_DIV);
+
+     val |= (21 << SUN4I_PLL2_B_PRE_DIV) | (4 << SUN4I_PLL2_B_POST_DIV);
+
+     if (rate == 22579200)
+             val |= (79 << SUN4I_PLL2_B_N);
+     else if (rate == 24576000)
+             val |= (86 << SUN4I_PLL2_B_N);
+     else
+             return -EINVAL;
+
+     writel(val, clk->reg);
+
+     return 0;
+}
+
+static const struct clk_ops sun4i_pll2_ops_a = {
+     .recalc_rate = sun4i_pll2_recalc_rate_a,
+     .round_rate = sun4i_pll2_round_rate,
+     .set_rate = sun4i_pll2_set_rate_a,
+};
+
+
+static const struct clk_ops sun4i_pll2_ops_b = {
+     .recalc_rate = sun4i_pll2_recalc_rate_b,
+     .round_rate = sun4i_pll2_round_rate,
+     .set_rate = sun4i_pll2_set_rate_b,
+};
+
+static const struct of_device_id pll2_matches[] __initconst = {
+     { .compatible = "allwinner,sun4i-a10-a-pll2-clk", .data = &sun4i_pll2_ops_a },
+     { .compatible = "allwinner,sun4i-a10-b-pll2-clk", .data = &sun4i_pll2_ops_b },
+     { /* sentinel */ },
+};
+
+static void __init sun4i_pll2_setup(struct device_node *np)
+{
+     const char *clk_name = np->name, *parent;
+     const struct of_device_id *match;
+     struct clk_onecell_data *clk_data;
+     const struct clk_ops *pll2_ops;
+     struct sun4i_pll2_clk *pll2;
+     struct clk_gate *gate;
+     struct clk **clks;
+     void __iomem *reg;
+
+     /* Choose the correct ops for pll2 */
+     match = of_match_node(pll2_matches, np);
+     pll2_ops = match->data;
+
+     pll2 = kzalloc(sizeof(*pll2), GFP_KERNEL);
+     gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+     clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+     clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(*clks), GFP_KERNEL);
+     if (!pll2 || !gate || !clk_data || !clks)
+             goto free_mem;
+
+     reg = of_iomap(np, 0);
+     parent = of_clk_get_parent_name(np, 0);
+     of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+
+     pll2->reg = reg;
+     gate->reg = reg;
+     gate->bit_idx = SUN4I_PLL2_ENABLE;
+
+     /* PLL2, also known as PLL2x1 */
+     of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+     clks[0] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
+                                      &pll2->hw, pll2_ops,
+                                      &gate->hw, &clk_gate_ops, 0);
+     WARN_ON(IS_ERR(clks[0]));
+     clk_set_rate(clks[0], 22579200);
+     parent = clk_name;
+
+     /* PLL2x2, 1/4 the rate of PLL2x8 */
+     of_property_read_string_index(np, "clock-output-names", 1, &clk_name);
+     clks[1] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                         CLK_SET_RATE_PARENT, 2, 1);
+     WARN_ON(IS_ERR(clks[1]));
+
+     /* PLL2x4, 1/2 the rate of PLL2x8 */
+     of_property_read_string_index(np, "clock-output-names", 2, &clk_name);
+     clks[2] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                         CLK_SET_RATE_PARENT, 4, 1);
+     WARN_ON(IS_ERR(clks[2]));

drivers/clk/sunxi/clk-a10-pll2.c line 227

Quoted 5 lines

drivers/clk/sunxi/clk-a10-pll2.c new file +5 -0

+
+     /* PLL2x8, double of PLL2 without the post divisor */
+     of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
+     clks[3] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                         CLK_SET_RATE_PARENT, 2 * 4, 1);

Why have you declared them here, instead of using fixed factors in the DT directly, like we have done in the past?

Quoted 20 lines

Quoted 20 lines

drivers/clk/sunxi/clk-a10-pll2.c new file +20 -0

+     /* PLL2, also known as PLL2x1 */
+     of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+     clks[0] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
+                                      &pll2->hw, pll2_ops,
+                                      &gate->hw, &clk_gate_ops, 0);
+     WARN_ON(IS_ERR(clks[0]));
+     clk_set_rate(clks[0], 22579200);
+     parent = clk_name;
+
+     /* PLL2x2, 1/4 the rate of PLL2x8 */
+     of_property_read_string_index(np, "clock-output-names", 1, &clk_name);
+     clks[1] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                         CLK_SET_RATE_PARENT, 2, 1);
+     WARN_ON(IS_ERR(clks[1]));
+
+     /* PLL2x4, 1/2 the rate of PLL2x8 */
+     of_property_read_string_index(np, "clock-output-names", 2, &clk_name);
+     clks[2] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                         CLK_SET_RATE_PARENT, 4, 1);
+     WARN_ON(IS_ERR(clks[2]));

Quoted 8 lines

drivers/clk/sunxi/clk-a10-pll2.c line 227

Quoted 5 lines

drivers/clk/sunxi/clk-a10-pll2.c new file +5 -0

+
+     /* PLL2x8, double of PLL2 without the post divisor */
+     of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
+     clks[3] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                         CLK_SET_RATE_PARENT, 2 * 4, 1);

Why have you declared them here, instead of using fixed factors in the DT directly, like we have done in the past?

IIRC, We have not done so for the PLL clocks. This is how it was, though it was with the more complicated divs clocks.

Quoted 7 lines

This patch adds support for PLL2 and derivates on sun4i, sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates.

Signed-off-by Emilio L?pez <[email protected]>

---

drivers/clk/sunxi/clk-a10-pll2.c line 227

Quoted 4 lines

drivers/clk/sunxi/clk-a10-pll2.c new file +4 -0

+	/* PLL2x8, double of PLL2 without the post divisor */
+	of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
+	clks[3] = clk_register_fixed_factor(NULL, clk_name, parent,
+					    CLK_SET_RATE_PARENT, 2 * 4, 1);

Why have you declared them here, instead of using fixed factors in the DT directly, like we have done in the past?

Hi,

El 03/08/14 a las 09:44, Maxime Ripard escibi?:

Quoted 8 lines · Emilio L?pez

Quoted 7 lines

This patch adds support for PLL2 and derivates on sun4i, sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates.

Signed-off-by Emilio L?pez <[email protected]>

---

(...)

Quoted 7 lines

drivers/clk/sunxi/clk-a10-pll2.c line 227

Quoted 4 lines

drivers/clk/sunxi/clk-a10-pll2.c new file +4 -0

+	/* PLL2x8, double of PLL2 without the post divisor */
+	of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
+	clks[3] = clk_register_fixed_factor(NULL, clk_name, parent,
+					    CLK_SET_RATE_PARENT, 2 * 4, 1);

Why have you declared them here, instead of using fixed factors in the DT directly, like we have done in the past?

I'd prefer to see one clock with four outputs represented as one clock with four outputs rather than one clock with one output and other three weirdly named nodes floating around.

I can only see four uses of fixed-factor-clock in our DTSI, three of which are "pass through" clocks for ahb and ar100 on sun6/8i, and a fourth one to implement the 32k that results from reducing the 24M osc on sun7i.

As a second reason, implementing it as fixed factors would be slightly incorrect, as it's only "x8" when you use the limited set of factors that Allwinner and us are using for audio.

If we were ever to support the full range of the PLL. the DT binding would suddenly be off. By using a single binding, the meaning is self-contained in the driver.

As a third reason, of_fixed_factor_clk_setup() does not set CLK_SET_RATE_PARENT, which we'd need to propagate the rate change upstream.

Quoted 20 lines

Hi,

El 03/08/14 a las 09:44, Maxime Ripard escibi?:

Quoted 8 lines · Emilio L?pez

Quoted 7 lines

This patch adds support for PLL2 and derivates on sun4i, sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates.

Signed-off-by Emilio L?pez <[email protected]>

---

(...)

Quoted 7 lines

drivers/clk/sunxi/clk-a10-pll2.c line 227

Quoted 4 lines

drivers/clk/sunxi/clk-a10-pll2.c new file +4 -0

+	/* PLL2x8, double of PLL2 without the post divisor */
+	of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
+	clks[3] = clk_register_fixed_factor(NULL, clk_name, parent,
+					    CLK_SET_RATE_PARENT, 2 * 4, 1);

Why have you declared them here, instead of using fixed factors in the DT directly, like we have done in the past?

Quoted 3 lines

I'd prefer to see one clock with four outputs represented as one clock with four outputs rather than one clock with one output and other three weirdly named nodes floating around.

Except that you have no control over these 3 other outputs, that directly derive from the only one you can control.

Plus, their name wouldn't be weirded than the one you gave in clock-output-names ;)

Quoted 4 lines

I can only see four uses of fixed-factor-clock in our DTSI, three of which are "pass through" clocks for ahb and ar100 on sun6/8i, and a fourth one to implement the 32k that results from reducing the 24M osc on sun7i.

And PLLx2, PLL2x4, PLL2x8 are really just pass-through clocks too. Once PLL2 is controlled, those will just be enabled.

Quoted 3 lines

As a second reason, implementing it as fixed factors would be slightly incorrect, as it's only "x8" when you use the limited set of factors that Allwinner and us are using for audio.

Hu? What do you mean by that?

El 04/08/14 a las 17:02, Maxime Ripard escibi?:

Quoted 21 lines · Emilio L?pez

Quoted 20 lines

Hi,

El 03/08/14 a las 09:44, Maxime Ripard escibi?:

Quoted 8 lines · Emilio L?pez

Quoted 7 lines

This patch adds support for PLL2 and derivates on sun4i, sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates.

Signed-off-by Emilio L?pez <[email protected]>

---

(...)

Quoted 7 lines

drivers/clk/sunxi/clk-a10-pll2.c line 227

Quoted 4 lines

drivers/clk/sunxi/clk-a10-pll2.c new file +4 -0

+	/* PLL2x8, double of PLL2 without the post divisor */
+	of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
+	clks[3] = clk_register_fixed_factor(NULL, clk_name, parent,
+					    CLK_SET_RATE_PARENT, 2 * 4, 1);

Why have you declared them here, instead of using fixed factors in the DT directly, like we have done in the past?

Quoted 6 lines

Quoted 3 lines

I'd prefer to see one clock with four outputs represented as one clock with four outputs rather than one clock with one output and other three weirdly named nodes floating around.

Except that you have no control over these 3 other outputs, that directly derive from the only one you can control.

You do have one degree of control, see below.

Quoted 2 lines

Plus, their name wouldn't be weirded than the one you gave in clock-output-names ;)

Allwinner chose those names on the user manual, not me :)

Quoted 7 lines

Quoted 4 lines

I can only see four uses of fixed-factor-clock in our DTSI, three of which are "pass through" clocks for ahb and ar100 on sun6/8i, and a fourth one to implement the 32k that results from reducing the 24M osc on sun7i.

And PLLx2, PLL2x4, PLL2x8 are really just pass-through clocks too. Once PLL2 is controlled, those will just be enabled.

Yes and no.

Quoted 4 lines

Quoted 3 lines

As a second reason, implementing it as fixed factors would be slightly incorrect, as it's only "x8" when you use the limited set of factors that Allwinner and us are using for audio.

Quoted 1 line

Hu? What do you mean by that?

PLL2 (aka PLL2x1) is 24 * N / pre / post
PLL2x8 is 24 * 2 * N / pre

So PLL2 * 8 == PLL2x8 only if post == 4, which holds true on our software implementation as well as AW's, but may not always hold true hardware wise.

--
2.0.3

This patch adds support for PLL2 and derivates on sun4i, sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates.

Signed-off-by Emilio L?pez <[email protected]>

---

Changes from RFC:
* Add support for A10 rev. A
* Document compatibles
* Use fixed factors

 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile                        |   1 +
 drivers/clk/sunxi/clk-a10-pll2.c                  | 243 ++++++++++++++++++++++
 3 files changed, 246 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c

Documentation/devicetree/bindings/clock/sunxi.txt +2 -0

index d3a5c3c..41ada31 100644
@@ -10,6 +10,8 @@ Required properties:
        "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
        "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
        "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+       "allwinner,sun4i-a10-a-pll2-clk" - for the PLL2 clock on A10 rev. A
+       "allwinner,sun4i-a10-b-pll2-clk" - for the PLL2 clock on A10 rev. B
        "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
        "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
        "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31

drivers/clk/sunxi/Makefile +1 -0

index 6850cba..dcd5709 100644
@@ -4,6 +4,7 @@
 
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
+obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \

drivers/clk/sunxi/clk-a10-pll2.c new file +97 -0

new file mode 100644
index 0000000..bcf7d0b
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define SUN4I_PLL2_ENABLE              31
+#define SUN4I_PLL2_A_VCOBIAS           0
+#define SUN4I_PLL2_A_VCOBIAS_MASK      0x1F
+#define SUN4I_PLL2_A_N                 7
+#define SUN4I_PLL2_A_N_MASK            0x7F
+#define SUN4I_PLL2_B_POST_DIV          26
+#define SUN4I_PLL2_B_POST_DIV_MASK     0xF
+#define SUN4I_PLL2_B_N                 8
+#define SUN4I_PLL2_B_N_MASK            0x7F
+#define SUN4I_PLL2_B_PRE_DIV           0
+#define SUN4I_PLL2_B_PRE_DIV_MASK      0x1F
+
+#define SUN4I_PLL2_OUTPUTS             4
+
+struct sun4i_pll2_clk {
+       struct clk_hw hw;
+       void __iomem *reg;
+};
+
+static inline struct sun4i_pll2_clk *to_sun4i_pll2_clk(struct clk_hw *hw)
+{
+       return container_of(hw, struct sun4i_pll2_clk, hw);
+}
+
+static unsigned long sun4i_pll2_recalc_rate_a(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+       struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+       int vcobias, n;
+       u32 val;
+
+       val = readl(clk->reg);
+       vcobias = (val >> SUN4I_PLL2_A_VCOBIAS) & SUN4I_PLL2_A_VCOBIAS_MASK;
+       n = (val >> SUN4I_PLL2_A_N) & SUN4I_PLL2_A_N_MASK;
+
+       if (vcobias == 10 && n == 94)
+               return 22579200;
+       else if (vcobias == 9 && n == 83)
+               return 24576000;
+
+       /*
+        * Unfortunately we don't really have much documentation on how
+        * these factors relate mathematically
+        */
+       return 0;
+}
+
+static unsigned long sun4i_pll2_recalc_rate_b(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+       struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+       int n, prediv, postdiv;
+       u32 val;
+
+       val = readl(clk->reg);
+       n = (val >> SUN4I_PLL2_B_N) & SUN4I_PLL2_B_N_MASK;
+       prediv = (val >> SUN4I_PLL2_B_PRE_DIV) & SUN4I_PLL2_B_PRE_DIV_MASK;
+       postdiv = (val >> SUN4I_PLL2_B_POST_DIV) & SUN4I_PLL2_B_POST_DIV_MASK;
+
+       /* 0 is a special case and means 1 */
+       if (n == 0)
+               n = 1;
+       if (prediv == 0)
+               prediv = 1;
+       if (postdiv == 0)
+               postdiv = 1;
+
+       return ((parent_rate * n) / prediv) / postdiv;
+}
+
+static long sun4i_pll2_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *parent_rate)
+{
+       /*
+        * There is only two interesting rates for the audio PLL, the
+        * rest isn't really usable due to accuracy concerns. Therefore,

drivers/clk/sunxi/clk-a10-pll2.c new file +136 -1

+
+static int sun4i_pll2_set_rate_a(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+       struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+       u32 val = readl(clk->reg);
+
+       val &= ~(SUN4I_PLL2_A_VCOBIAS_MASK << SUN4I_PLL2_A_VCOBIAS);
+       val &= ~(SUN4I_PLL2_A_N_MASK << SUN4I_PLL2_A_N);
+
+       if (rate == 22579200)
+               val |= (10 << SUN4I_PLL2_A_VCOBIAS) | (94 << SUN4I_PLL2_A_N);
+       else if (rate == 24576000)
+               val |= (9 << SUN4I_PLL2_A_VCOBIAS) | (83 << SUN4I_PLL2_A_N);
+       else
+               return -EINVAL;
+
+       writel(val, clk->reg);
+
+       return 0;
+}
+
+static int sun4i_pll2_set_rate_b(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+       struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+       u32 val = readl(clk->reg);
+
+       val &= ~(SUN4I_PLL2_B_N_MASK << SUN4I_PLL2_B_N);
+       val &= ~(SUN4I_PLL2_B_PRE_DIV_MASK << SUN4I_PLL2_B_PRE_DIV);
+       val &= ~(SUN4I_PLL2_B_POST_DIV_MASK << SUN4I_PLL2_B_POST_DIV);
+
+       val |= (21 << SUN4I_PLL2_B_PRE_DIV) | (4 << SUN4I_PLL2_B_POST_DIV);
+
+       if (rate == 22579200)
+               val |= (79 << SUN4I_PLL2_B_N);
+       else if (rate == 24576000)
+               val |= (86 << SUN4I_PLL2_B_N);
+       else
+               return -EINVAL;
+
+       writel(val, clk->reg);
+
+       return 0;
+}
+
+static const struct clk_ops sun4i_pll2_ops_a = {
+       .recalc_rate = sun4i_pll2_recalc_rate_a,
+       .round_rate = sun4i_pll2_round_rate,
+       .set_rate = sun4i_pll2_set_rate_a,
+};
+
+
+static const struct clk_ops sun4i_pll2_ops_b = {
+       .recalc_rate = sun4i_pll2_recalc_rate_b,
+       .round_rate = sun4i_pll2_round_rate,
+       .set_rate = sun4i_pll2_set_rate_b,
+};
+
+static const struct of_device_id pll2_matches[] __initconst = {
+       { .compatible = "allwinner,sun4i-a10-a-pll2-clk", .data = &sun4i_pll2_ops_a },
+       { .compatible = "allwinner,sun4i-a10-b-pll2-clk", .data = &sun4i_pll2_ops_b },
+       { /* sentinel */ },
+};
+
+static void __init sun4i_pll2_setup(struct device_node *np)
+{
+       const char *clk_name = np->name, *parent;
+       const struct of_device_id *match;
+       struct clk_onecell_data *clk_data;
+       const struct clk_ops *pll2_ops;
+       struct sun4i_pll2_clk *pll2;
+       struct clk_gate *gate;
+       struct clk **clks;
+       void __iomem *reg;
+
+       /* Choose the correct ops for pll2 */
+       match = of_match_node(pll2_matches, np);
+       pll2_ops = match->data;
+
+       pll2 = kzalloc(sizeof(*pll2), GFP_KERNEL);
+       gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+       clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+       clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(*clks), GFP_KERNEL);
+       if (!pll2 || !gate || !clk_data || !clks)
+               goto free_mem;
+
+       reg = of_iomap(np, 0);
+       parent = of_clk_get_parent_name(np, 0);
+       of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+
+       pll2->reg = reg;
+       gate->reg = reg;
+       gate->bit_idx = SUN4I_PLL2_ENABLE;
+
+       /* PLL2, also known as PLL2x1 */
+       of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+       clks[0] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
+                                        &pll2->hw, pll2_ops,
+                                        &gate->hw, &clk_gate_ops, 0);
+       WARN_ON(IS_ERR(clks[0]));
+       clk_set_rate(clks[0], 22579200);
+       parent = clk_name;
+
+       /* PLL2x2, 1/4 the rate of PLL2x8 */
+       of_property_read_string_index(np, "clock-output-names", 1, &clk_name);
+       clks[1] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                           CLK_SET_RATE_PARENT, 2, 1);
+       WARN_ON(IS_ERR(clks[1]));
+
+       /* PLL2x4, 1/2 the rate of PLL2x8 */
+       of_property_read_string_index(np, "clock-output-names", 2, &clk_name);
+       clks[2] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                           CLK_SET_RATE_PARENT, 4, 1);
+       WARN_ON(IS_ERR(clks[2]));
+
+       /* PLL2x8, double of PLL2 without the post divisor */
+       of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
+       clks[3] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                           CLK_SET_RATE_PARENT, 2 * 4, 1);
+       WARN_ON(IS_ERR(clks[3]));
+
+       clk_data->clks = clks;
+       clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
+       of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+
+       return;
+
+free_mem:
+       kfree(pll2);
+       kfree(gate);
+       kfree(clk_data);
+       kfree(clks);
+}
+CLK_OF_DECLARE(sun4i_pll2_a, "allwinner,sun4i-a10-a-pll2-clk", sun4i_pll2_setup);
+CLK_OF_DECLARE(sun4i_pll2_b, "allwinner,sun4i-a10-b-pll2-clk", sun4i_pll2_setup);
--

2.0.3

Quoted 146 lines · Emilio L?pez

This patch adds support for PLL2 and derivates on sun4i, sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates.

Signed-off-by Emilio L?pez <[email protected]>

---

Changes from RFC:
* Add support for A10 rev. A
* Document compatibles
* Use fixed factors

 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile                        |   1 +
 drivers/clk/sunxi/clk-a10-pll2.c                  | 243 ++++++++++++++++++++++
 3 files changed, 246 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c

Documentation/devicetree/bindings/clock/sunxi.txt +2 -0

index d3a5c3c..41ada31 100644
@@ -10,6 +10,8 @@ Required properties:
        "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
        "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
        "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+       "allwinner,sun4i-a10-a-pll2-clk" - for the PLL2 clock on A10 rev. A
+       "allwinner,sun4i-a10-b-pll2-clk" - for the PLL2 clock on A10 rev. B
        "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
        "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
        "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31

drivers/clk/sunxi/Makefile +1 -0

index 6850cba..dcd5709 100644
@@ -4,6 +4,7 @@
 
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
+obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \

drivers/clk/sunxi/clk-a10-pll2.c new file +97 -0

new file mode 100644
index 0000000..bcf7d0b
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define SUN4I_PLL2_ENABLE              31
+#define SUN4I_PLL2_A_VCOBIAS           0
+#define SUN4I_PLL2_A_VCOBIAS_MASK      0x1F
+#define SUN4I_PLL2_A_N                 7
+#define SUN4I_PLL2_A_N_MASK            0x7F
+#define SUN4I_PLL2_B_POST_DIV          26
+#define SUN4I_PLL2_B_POST_DIV_MASK     0xF
+#define SUN4I_PLL2_B_N                 8
+#define SUN4I_PLL2_B_N_MASK            0x7F
+#define SUN4I_PLL2_B_PRE_DIV           0
+#define SUN4I_PLL2_B_PRE_DIV_MASK      0x1F
+
+#define SUN4I_PLL2_OUTPUTS             4
+
+struct sun4i_pll2_clk {
+       struct clk_hw hw;
+       void __iomem *reg;
+};
+
+static inline struct sun4i_pll2_clk *to_sun4i_pll2_clk(struct clk_hw *hw)
+{
+       return container_of(hw, struct sun4i_pll2_clk, hw);
+}
+
+static unsigned long sun4i_pll2_recalc_rate_a(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+       struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+       int vcobias, n;
+       u32 val;
+
+       val = readl(clk->reg);
+       vcobias = (val >> SUN4I_PLL2_A_VCOBIAS) & SUN4I_PLL2_A_VCOBIAS_MASK;
+       n = (val >> SUN4I_PLL2_A_N) & SUN4I_PLL2_A_N_MASK;
+
+       if (vcobias == 10 && n == 94)
+               return 22579200;
+       else if (vcobias == 9 && n == 83)
+               return 24576000;
+
+       /*
+        * Unfortunately we don't really have much documentation on how
+        * these factors relate mathematically
+        */
+       return 0;
+}
+
+static unsigned long sun4i_pll2_recalc_rate_b(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+       struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+       int n, prediv, postdiv;
+       u32 val;
+
+       val = readl(clk->reg);
+       n = (val >> SUN4I_PLL2_B_N) & SUN4I_PLL2_B_N_MASK;
+       prediv = (val >> SUN4I_PLL2_B_PRE_DIV) & SUN4I_PLL2_B_PRE_DIV_MASK;
+       postdiv = (val >> SUN4I_PLL2_B_POST_DIV) & SUN4I_PLL2_B_POST_DIV_MASK;
+
+       /* 0 is a special case and means 1 */
+       if (n == 0)
+               n = 1;
+       if (prediv == 0)
+               prediv = 1;
+       if (postdiv == 0)
+               postdiv = 1;
+
+       return ((parent_rate * n) / prediv) / postdiv;
+}
+
+static long sun4i_pll2_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *parent_rate)
+{
+       /*
+        * There is only two interesting rates for the audio PLL, the
+        * rest isn't really usable due to accuracy concerns. Therefore,

drivers/clk/sunxi/clk-a10-pll2.c line 107

Quoted 10 lines

drivers/clk/sunxi/clk-a10-pll2.c new file +10 -0

+        * we specifically round to those rates here
+        */
+       if (rate < 22579200)
+               return -EINVAL;
+
+       if (rate >= 22579200 && rate < 24576000)
+               return 22579200;
+
+       return 24576000;
+}

These should return the actual computed rate osc*n / (pre * post) so that the error column is displayed correctly.

pll2 1 1 22571428 0

       i2s0                               1            1    22571428          0
          mclk0                           0            0    22571428          0

At 22.5 the error is 0.03%, 24.5 error is 0.01%.

So when you ask for 24.576 it returns 24.571428 and 22.5792 returns 22.571428.

Quoted 139 lines

drivers/clk/sunxi/clk-a10-pll2.c new file +136 -1

+
+static int sun4i_pll2_set_rate_a(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+       struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+       u32 val = readl(clk->reg);
+
+       val &= ~(SUN4I_PLL2_A_VCOBIAS_MASK << SUN4I_PLL2_A_VCOBIAS);
+       val &= ~(SUN4I_PLL2_A_N_MASK << SUN4I_PLL2_A_N);
+
+       if (rate == 22579200)
+               val |= (10 << SUN4I_PLL2_A_VCOBIAS) | (94 << SUN4I_PLL2_A_N);
+       else if (rate == 24576000)
+               val |= (9 << SUN4I_PLL2_A_VCOBIAS) | (83 << SUN4I_PLL2_A_N);
+       else
+               return -EINVAL;
+
+       writel(val, clk->reg);
+
+       return 0;
+}
+
+static int sun4i_pll2_set_rate_b(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+       struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
+       u32 val = readl(clk->reg);
+
+       val &= ~(SUN4I_PLL2_B_N_MASK << SUN4I_PLL2_B_N);
+       val &= ~(SUN4I_PLL2_B_PRE_DIV_MASK << SUN4I_PLL2_B_PRE_DIV);
+       val &= ~(SUN4I_PLL2_B_POST_DIV_MASK << SUN4I_PLL2_B_POST_DIV);
+
+       val |= (21 << SUN4I_PLL2_B_PRE_DIV) | (4 << SUN4I_PLL2_B_POST_DIV);
+
+       if (rate == 22579200)
+               val |= (79 << SUN4I_PLL2_B_N);
+       else if (rate == 24576000)
+               val |= (86 << SUN4I_PLL2_B_N);
+       else
+               return -EINVAL;
+
+       writel(val, clk->reg);
+
+       return 0;
+}
+
+static const struct clk_ops sun4i_pll2_ops_a = {
+       .recalc_rate = sun4i_pll2_recalc_rate_a,
+       .round_rate = sun4i_pll2_round_rate,
+       .set_rate = sun4i_pll2_set_rate_a,
+};
+
+
+static const struct clk_ops sun4i_pll2_ops_b = {
+       .recalc_rate = sun4i_pll2_recalc_rate_b,
+       .round_rate = sun4i_pll2_round_rate,
+       .set_rate = sun4i_pll2_set_rate_b,
+};
+
+static const struct of_device_id pll2_matches[] __initconst = {
+       { .compatible = "allwinner,sun4i-a10-a-pll2-clk", .data = &sun4i_pll2_ops_a },
+       { .compatible = "allwinner,sun4i-a10-b-pll2-clk", .data = &sun4i_pll2_ops_b },
+       { /* sentinel */ },
+};
+
+static void __init sun4i_pll2_setup(struct device_node *np)
+{
+       const char *clk_name = np->name, *parent;
+       const struct of_device_id *match;
+       struct clk_onecell_data *clk_data;
+       const struct clk_ops *pll2_ops;
+       struct sun4i_pll2_clk *pll2;
+       struct clk_gate *gate;
+       struct clk **clks;
+       void __iomem *reg;
+
+       /* Choose the correct ops for pll2 */
+       match = of_match_node(pll2_matches, np);
+       pll2_ops = match->data;
+
+       pll2 = kzalloc(sizeof(*pll2), GFP_KERNEL);
+       gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+       clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+       clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(*clks), GFP_KERNEL);
+       if (!pll2 || !gate || !clk_data || !clks)
+               goto free_mem;
+
+       reg = of_iomap(np, 0);
+       parent = of_clk_get_parent_name(np, 0);
+       of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+
+       pll2->reg = reg;
+       gate->reg = reg;
+       gate->bit_idx = SUN4I_PLL2_ENABLE;
+
+       /* PLL2, also known as PLL2x1 */
+       of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
+       clks[0] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
+                                        &pll2->hw, pll2_ops,
+                                        &gate->hw, &clk_gate_ops, 0);
+       WARN_ON(IS_ERR(clks[0]));
+       clk_set_rate(clks[0], 22579200);
+       parent = clk_name;
+
+       /* PLL2x2, 1/4 the rate of PLL2x8 */
+       of_property_read_string_index(np, "clock-output-names", 1, &clk_name);
+       clks[1] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                           CLK_SET_RATE_PARENT, 2, 1);
+       WARN_ON(IS_ERR(clks[1]));
+
+       /* PLL2x4, 1/2 the rate of PLL2x8 */
+       of_property_read_string_index(np, "clock-output-names", 2, &clk_name);
+       clks[2] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                           CLK_SET_RATE_PARENT, 4, 1);
+       WARN_ON(IS_ERR(clks[2]));
+
+       /* PLL2x8, double of PLL2 without the post divisor */
+       of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
+       clks[3] = clk_register_fixed_factor(NULL, clk_name, parent,
+                                           CLK_SET_RATE_PARENT, 2 * 4, 1);
+       WARN_ON(IS_ERR(clks[3]));
+
+       clk_data->clks = clks;
+       clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
+       of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+
+       return;
+
+free_mem:
+       kfree(pll2);
+       kfree(gate);
+       kfree(clk_data);
+       kfree(clks);
+}
+CLK_OF_DECLARE(sun4i_pll2_a, "allwinner,sun4i-a10-a-pll2-clk", sun4i_pll2_setup);
+CLK_OF_DECLARE(sun4i_pll2_b, "allwinner,sun4i-a10-b-pll2-clk", sun4i_pll2_setup);
--

Quoted 1 line

2.0.3

--
Jon Smirl
jonsmirl at gmail.com

The module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver.

Not-signed-off-by Emilio L?pez <[email protected]>

---

Changes from RFC:
* Document compatible used

 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile                        |  1 +
 drivers/clk/sunxi/clk-a10-mod1.c                  | 69 +++++++++++++++++++++++
 3 files changed, 71 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c

Documentation/devicetree/bindings/clock/sunxi.txt +1 -0

index d18b89b..b028ee2 100644
@@ -50,6 +50,7 @@ Required properties:
 	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
 	"allwinner,sun4i-a10-codec-clk" - for the codec clock on A10
 	"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
+	"allwinner,sun4i-a10-mod1-clk" - for the module 1 family of clocks
 	"allwinner,sun7i-a20-out-clk" - for the external output clocks
 	"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
 	"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20

drivers/clk/sunxi/Makefile +1 -0

index a7a96f8..75d113d 100644
@@ -5,6 +5,7 @@
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-codec.o
 obj-y += clk-a10-hosc.o
+obj-y += clk-a10-mod1.o
 obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 

drivers/clk/sunxi/clk-a10-mod1.c new file +59 -0

new file mode 100644
index 0000000..09afd54
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+static DEFINE_SPINLOCK(mod1_lock);
+
+#define SUN4I_MOD1_ENABLE	31
+#define SUN4I_MOD1_MUX		16
+#define SUN4I_MOD1_MUX_WIDTH	2
+#define SUN4I_MOD1_MAX_PARENTS	4
+
+static void __init sun4i_mod1_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_mux *mux;
+	struct clk_gate *gate;
+	const char *parents[4];
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	int i = 0;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!mux || !gate) {
+		kfree(mux);
+		kfree(gate);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	reg = of_iomap(node, 0);
+
+	while (i < SUN4I_MOD1_MAX_PARENTS &&
+	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+
+	gate->reg = reg;
+	gate->bit_idx = SUN4I_MOD1_ENABLE;
+	gate->lock = &mod1_lock;
+	mux->reg = reg;
+	mux->shift = SUN4I_MOD1_MUX;
+	mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;

Quoted 5 lines

The module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver.

Not-signed-off-by Emilio L?pez <[email protected]>

Why so?

It looks quite good.

Quoted 98 lines

---

Changes from RFC:
* Document compatible used

  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
  drivers/clk/sunxi/Makefile                        |  1 +
  drivers/clk/sunxi/clk-a10-mod1.c                  | 69 +++++++++++++++++++++++
  3 files changed, 71 insertions(+)

create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c

Documentation/devicetree/bindings/clock/sunxi.txt +1 -0

index d18b89b..b028ee2 100644
@@ -50,6 +50,7 @@ Required properties:
  	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
  	"allwinner,sun4i-a10-codec-clk" - for the codec clock on A10
  	"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
+	"allwinner,sun4i-a10-mod1-clk" - for the module 1 family of clocks
  	"allwinner,sun7i-a20-out-clk" - for the external output clocks
  	"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
  	"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20

drivers/clk/sunxi/Makefile +1 -0

index a7a96f8..75d113d 100644
@@ -5,6 +5,7 @@
  obj-y += clk-sunxi.o clk-factors.o
  obj-y += clk-a10-codec.o
  obj-y += clk-a10-hosc.o
+obj-y += clk-a10-mod1.o
  obj-y += clk-a10-pll2.o
  obj-y += clk-a20-gmac.o
 

drivers/clk/sunxi/clk-a10-mod1.c new file +57 -0

new file mode 100644
index 0000000..09afd54
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+static DEFINE_SPINLOCK(mod1_lock);
+
+#define SUN4I_MOD1_ENABLE	31
+#define SUN4I_MOD1_MUX		16
+#define SUN4I_MOD1_MUX_WIDTH	2
+#define SUN4I_MOD1_MAX_PARENTS	4
+
+static void __init sun4i_mod1_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_mux *mux;
+	struct clk_gate *gate;
+	const char *parents[4];
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	int i = 0;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!mux || !gate) {
+		kfree(mux);
+		kfree(gate);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	reg = of_iomap(node, 0);
+
+	while (i < SUN4I_MOD1_MAX_PARENTS &&
+	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+
+	gate->reg = reg;
+	gate->bit_idx = SUN4I_MOD1_ENABLE;
+	gate->lock = &mod1_lock;
+	mux->reg = reg;

drivers/clk/sunxi/clk-a10-mod1.c line 65

Quoted 8 lines

drivers/clk/sunxi/clk-a10-mod1.c new file +8 -0

+	mux->shift = SUN4I_MOD1_MUX;
+	mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
+	mux->lock = &mod1_lock;
+
+	clk = clk_register_composite(NULL, clk_name, parents, i,
+				     &mux->hw, &clk_mux_ops,
+				     NULL, NULL,
+				     &gate->hw, &clk_gate_ops, 0);

drivers/clk/sunxi/clk-a10-mod1.c line 69

Quoted 4 lines

drivers/clk/sunxi/clk-a10-mod1.c new file +4 -0

+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk", sun4i_mod1_clk_setup);

Why are you not using clk-sunxi for this? It has pretty much everything in place to do so already.

Hi,

El 03/08/14 a las 09:47, Maxime Ripard escibi?:

Quoted 7 lines · Emilio L?pez

Quoted 5 lines

The module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver.

Not-signed-off-by Emilio L?pez <[email protected]>

Quoted 3 lines

Why so?

It looks quite good.

Because I have not tested this with any actual mod1 clients. Once Jon or Marcus report it's ok I'll be happy to s/Not-s/S/; same with the DT bindings.

Quoted 99 lines

Quoted 99 lines

---

Changes from RFC:
* Document compatible used

 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile                        |  1 +
 drivers/clk/sunxi/clk-a10-mod1.c                  | 69 +++++++++++++++++++++++
 3 files changed, 71 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c

Documentation/devicetree/bindings/clock/sunxi.txt +1 -0

index d18b89b..b028ee2 100644
@@ -50,6 +50,7 @@ Required properties:
 	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
 	"allwinner,sun4i-a10-codec-clk" - for the codec clock on A10
 	"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
+	"allwinner,sun4i-a10-mod1-clk" - for the module 1 family of clocks
 	"allwinner,sun7i-a20-out-clk" - for the external output clocks
 	"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
 	"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20

drivers/clk/sunxi/Makefile +1 -0

index a7a96f8..75d113d 100644
@@ -5,6 +5,7 @@
 obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-codec.o
 obj-y += clk-a10-hosc.o
+obj-y += clk-a10-mod1.o
 obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 

drivers/clk/sunxi/clk-a10-mod1.c new file +57 -0

new file mode 100644
index 0000000..09afd54
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2014 Emilio L?pez
+ *
+ * Emilio L?pez <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+static DEFINE_SPINLOCK(mod1_lock);
+
+#define SUN4I_MOD1_ENABLE	31
+#define SUN4I_MOD1_MUX		16
+#define SUN4I_MOD1_MUX_WIDTH	2
+#define SUN4I_MOD1_MAX_PARENTS	4
+
+static void __init sun4i_mod1_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_mux *mux;
+	struct clk_gate *gate;
+	const char *parents[4];
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	int i = 0;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!mux || !gate) {
+		kfree(mux);
+		kfree(gate);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	reg = of_iomap(node, 0);
+
+	while (i < SUN4I_MOD1_MAX_PARENTS &&
+	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+
+	gate->reg = reg;
+	gate->bit_idx = SUN4I_MOD1_ENABLE;
+	gate->lock = &mod1_lock;
+	mux->reg = reg;

Quoted 8 lines

drivers/clk/sunxi/clk-a10-mod1.c line 65

Quoted 8 lines

drivers/clk/sunxi/clk-a10-mod1.c new file +8 -0

+	mux->shift = SUN4I_MOD1_MUX;
+	mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
+	mux->lock = &mod1_lock;
+
+	clk = clk_register_composite(NULL, clk_name, parents, i,
+				     &mux->hw, &clk_mux_ops,
+				     NULL, NULL,
+				     &gate->hw, &clk_gate_ops, 0);

We'll probably need SET_RATE_PARENT here as well

Quoted 7 lines

drivers/clk/sunxi/clk-a10-mod1.c line 69

Quoted 4 lines

drivers/clk/sunxi/clk-a10-mod1.c new file +4 -0

+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk", sun4i_mod1_clk_setup);

Why are you not using clk-sunxi for this? It has pretty much everything in place to do so already.

If this were to have a rate component we could reuse the factors infrastructure, but it doesn't, as it's just a gate and a mux.

This commit adds the PLL2 definition to the sun4i, sun5i and sun7i device trees. PLL2 is used to clock audio devices.

Signed-off-by Emilio L?pez <[email protected]>

---

Changes from RFC:
* A10 rev A is now supported via the quirk code

 arch/arm/boot/dts/sun4i-a10.dtsi  | 8 ++++++++
 arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi  | 8 ++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi  | 8 ++++++++
 4 files changed, 32 insertions(+)

arch/arm/boot/dts/sun4i-a10.dtsi +8 -0

index 459cb63..c4d4c73 100644
@@ -81,6 +81,14 @@
                        clock-output-names = "pll1";
                };
 
+               pll2: clk at 01c20008 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-a10-b-pll2-clk";
+                       reg = <0x01c20008 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
+               };
+
                pll4: clk at 01c20018 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-pll1-clk";

arch/arm/boot/dts/sun5i-a10s.dtsi +8 -0

index 24b0ad3..f35aa4d 100644
@@ -74,6 +74,14 @@
                        clock-output-names = "pll1";
                };
 
+               pll2: clk at 01c20008 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-a10-b-pll2-clk";
+                       reg = <0x01c20008 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
+               };
+
                pll4: clk at 01c20018 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-pll1-clk";

arch/arm/boot/dts/sun5i-a13.dtsi +8 -0

index bf86e65..38b2d77 100644
@@ -75,6 +75,14 @@
                        clock-output-names = "pll1";
                };
 
+               pll2: clk at 01c20008 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-a10-b-pll2-clk";
+                       reg = <0x01c20008 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
+               };
+
                pll4: clk at 01c20018 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-pll1-clk";

arch/arm/boot/dts/sun7i-a20.dtsi +8 -1

index 4011628..7a6a18c 100644
@@ -91,6 +91,14 @@
                        clock-output-names = "pll1";
                };
 
+               pll2: clk at 01c20008 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-a10-b-pll2-clk";
+                       reg = <0x01c20008 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
+               };
+
                pll4: clk at 01c20018 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun7i-a20-pll4-clk";
--

2.0.3