ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU

PATCH New Pranavkumar Sawargaonkar 4 participants 6 messages Jul 31, 2014 – Aug 22, 2014

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Arm (32-bit) arm64 KVM arm64

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Pranavkumar Sawargaonkar

author

2014-07-31 06:53 UTC #0 lore raw

PATCH v2 1/1 ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU

X-Gene u-boot runs in EL2 mode with MMU enabled hence we might have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU.

This can happen on any ARM/ARM64 board running bootloader in Hyp-mode (or EL2-mode) with MMU enabled.

This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs on each host CPU before enabling Hyp-mode (or EL2-mode) MMU.

Changelog:

V2:
- Flush Hyp-mode TLBs for both KVM ARM32 and KVM ARM64 at boot time

V1:
- Initial patch with only arm64 change

Signed-off-by Pranavkumar Sawargaonkar <[email protected]>

Signed-off-by Anup Patel <[email protected]>

---
 arch/arm/kvm/init.S       |    4 ++++
 arch/arm64/kvm/hyp-init.S |    4 ++++
 2 files changed, 8 insertions(+)

arch/arm/kvm/init.S +4 -0

index 1b9844d..ee4f744 100644
@@ -98,6 +98,10 @@ __do_hyp_init:
 	mrc	p15, 0, r0, c10, c2, 1
 	mcr	p15, 4, r0, c10, c2, 1
 
+	@ Invalidate the stale TLBs from Bootloader
+	mcr	p15, 4, r0, c8, c7, 0	@ TLBIALLH
+	dsb	ish
+
 	@ Set the HSCTLR to:
 	@  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
 	@  - Endianness: Kernel config

arch/arm64/kvm/hyp-init.S +4 -0

index d968796..c319116 100644
@@ -80,6 +80,10 @@ __do_hyp_init:
 	msr	mair_el2, x4
 	isb
 
+	/* Invalidate the stale TLBs from Bootloader */
+	tlbi	alle2
+	dsb	sy
+
 	mrs	x4, sctlr_el2
 	and	x4, x4, #SCTLR_EL2_EE	// preserve endianness of EL2
 	ldr	x5, =SCTLR_EL2_FLAGS

Signature · 1 line

1.7.9.5

Christoffer Dall

2014-08-04 12:06 UTC #1 lore raw

PATCH v2 1/1 ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU

Quoted 11 lines · Pranavkumar Sawargaonkar

X-Gene u-boot runs in EL2 mode with MMU enabled hence we might have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU.
This can happen on any ARM/ARM64 board running bootloader in Hyp-mode (or EL2-mode) with MMU enabled.
This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs on each host CPU before enabling Hyp-mode (or EL2-mode) MMU.
Changelog:

Quoted 8 lines

V2:
- Flush Hyp-mode TLBs for both KVM ARM32 and KVM ARM64 at boot time
V1:
- Initial patch with only arm64 change
Signed-off-by Pranavkumar Sawargaonkar <[email protected]>
Signed-off-by Anup Patel <[email protected]>

Reviewed-by Christoffer Dall <[email protected]>

Marc Zyngier

2014-08-22 09:03 UTC #2 lore raw

PATCH v2 1/1 ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU

Quoted 15 lines · Christoffer Dall

Quoted 14 lines · Pranavkumar Sawargaonkar
X-Gene u-boot runs in EL2 mode with MMU enabled hence we might have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU.
This can happen on any ARM/ARM64 board running bootloader in Hyp-mode (or EL2-mode) with MMU enabled.
This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs on each host CPU before enabling Hyp-mode (or EL2-mode) MMU.
Changelog:
V2:
- Flush Hyp-mode TLBs for both KVM ARM32 and KVM ARM64 at boot time

Quoted 7 lines

Quoted 5 lines
V1:
- Initial patch with only arm64 change
Signed-off-by Pranavkumar Sawargaonkar <[email protected]>
Signed-off-by Anup Patel <[email protected]>
Reviewed-by Christoffer Dall <[email protected]>

Acked-by Marc Zyngier <[email protected]>

This should probably go in quickly as a fix.

Thanks,

M.

Signature · 1 line

Jazz is not dead. It just smells funny...

Marc Zyngier

2014-08-04 13:26 UTC #3 lore raw

PATCH v2 1/1 ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU

In reply to Pranavkumar Sawargaonkar

Hi Pranav,

Quoted 44 lines · Pranavkumar Sawargaonkar

X-Gene u-boot runs in EL2 mode with MMU enabled hence we might have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU.
This can happen on any ARM/ARM64 board running bootloader in Hyp-mode (or EL2-mode) with MMU enabled.
This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs on each host CPU before enabling Hyp-mode (or EL2-mode) MMU.
Changelog:
V2:
- Flush Hyp-mode TLBs for both KVM ARM32 and KVM ARM64 at boot time
V1:
- Initial patch with only arm64 change
Signed-off-by Pranavkumar Sawargaonkar <[email protected]>
Signed-off-by Anup Patel <[email protected]>
---
 arch/arm/kvm/init.S       |    4 ++++
 arch/arm64/kvm/hyp-init.S |    4 ++++
 2 files changed, 8 insertions(+)
arch/arm/kvm/init.S +4 -0
index 1b9844d..ee4f744 100644
@@ -98,6 +98,10 @@ __do_hyp_init:
 	mrc	p15, 0, r0, c10, c2, 1
 	mcr	p15, 4, r0, c10, c2, 1
 
+	@ Invalidate the stale TLBs from Bootloader
+	mcr	p15, 4, r0, c8, c7, 0	@ TLBIALLH
+	dsb	ish
+
 	@ Set the HSCTLR to:
 	@  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
 	@  - Endianness: Kernel config
arch/arm64/kvm/hyp-init.S +0 -0
index d968796..c319116 100644

arch/arm64/kvm/hyp-init.S __do_hyp_init: · line 89

Quoted 10 lines

arch/arm64/kvm/hyp-init.S +4 -0

@@ -80,6 +80,10 @@ __do_hyp_init:
 	msr	mair_el2, x4
 	isb
 
+	/* Invalidate the stale TLBs from Bootloader */
+	tlbi	alle2
+	dsb	sy
+
 	mrs	x4, sctlr_el2
 	and	x4, x4, #SCTLR_EL2_EE	// preserve endianness of EL2
 	ldr	x5, =SCTLR_EL2_FLAGS

Reviewed-by Marc Zyngier <[email protected]>

M.

Signature · 1 line

Jazz is not dead. It just smells funny.

Mark Rutland

reviewer

2014-08-22 10:23 UTC #4 lore raw

PATCH v2 1/1 ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU

In reply to Pranavkumar Sawargaonkar

Hi Pranav,

Quoted 2 lines · Pranavkumar Sawargaonkar

X-Gene u-boot runs in EL2 mode with MMU enabled hence we might have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU.

Nit: entries

Quoted 5 lines

This can happen on any ARM/ARM64 board running bootloader in Hyp-mode (or EL2-mode) with MMU enabled.
This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs on each host CPU before enabling Hyp-mode (or EL2-mode) MMU.

I hit a similar issue intermittently on a Juno board when I boot Linux as an EFI application, where CPU0 would get stuck in a recursive exception at EL2 while initialising hyp. We don't nuke the TLBs in efi_stub_entry nor do we do so in el2_setup, so there's the possibility of stale EL2 TLB entries lying around from UEFI.

With this patch applied I'm unable to reproduce the issue (with ~30 boots so far). So:

Tested-by Mark Rutland <[email protected]>

It would be nice to see this hit mainline soon.

Thanks,
Mark.

Quoted 55 lines

Changelog:

V2:
- Flush Hyp-mode TLBs for both KVM ARM32 and KVM ARM64 at boot time

V1:
- Initial patch with only arm64 change

Signed-off-by Pranavkumar Sawargaonkar <[email protected]>

Signed-off-by Anup Patel <[email protected]>

---
 arch/arm/kvm/init.S       |    4 ++++
 arch/arm64/kvm/hyp-init.S |    4 ++++
 2 files changed, 8 insertions(+)

arch/arm/kvm/init.S +4 -0

index 1b9844d..ee4f744 100644
@@ -98,6 +98,10 @@ __do_hyp_init:
 	mrc	p15, 0, r0, c10, c2, 1
 	mcr	p15, 4, r0, c10, c2, 1
 
+	@ Invalidate the stale TLBs from Bootloader
+	mcr	p15, 4, r0, c8, c7, 0	@ TLBIALLH
+	dsb	ish
+
 	@ Set the HSCTLR to:
 	@  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
 	@  - Endianness: Kernel config

arch/arm64/kvm/hyp-init.S +4 -0

index d968796..c319116 100644
@@ -80,6 +80,10 @@ __do_hyp_init:
 	msr	mair_el2, x4
 	isb
 
+	/* Invalidate the stale TLBs from Bootloader */
+	tlbi	alle2
+	dsb	sy
+
 	mrs	x4, sctlr_el2
 	and	x4, x4, #SCTLR_EL2_EE	// preserve endianness of EL2
 	ldr	x5, =SCTLR_EL2_FLAGS

Signature · 7 lines

1.7.9.5


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Marc Zyngier

2014-08-22 10:41 UTC #5 lore raw

PATCH v2 1/1 ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU

Quoted 20 lines · Mark Rutland

Hi Pranav,
Quoted 2 lines · Pranavkumar Sawargaonkar
X-Gene u-boot runs in EL2 mode with MMU enabled hence we might have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU.
Nit: entries
Quoted 5 lines
This can happen on any ARM/ARM64 board running bootloader in Hyp-mode (or EL2-mode) with MMU enabled.
This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs on each host CPU before enabling Hyp-mode (or EL2-mode) MMU.
I hit a similar issue intermittently on a Juno board when I boot Linux as an EFI application, where CPU0 would get stuck in a recursive exception at EL2 while initialising hyp. We don't nuke the TLBs in efi_stub_entry nor do we do so in el2_setup, so there's the possibility of stale EL2 TLB entries lying around from UEFI.

Quoted 6 lines

With this patch applied I'm unable to reproduce the issue (with ~30 boots so far). So:
Tested-by Mark Rutland <[email protected]>
It would be nice to see this hit mainline soon.

Thanks for testing. I guess this is a candidate for stable as well.

M.

Signature · 1 line

Jazz is not dead. It just smells funny...