video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
PATCH 1/1 video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
Instead of waiting for DC triple buffer to be cleared, this patch changes to wait for a relevant DP sync flow end interrupt to come when disabling sync BG flows. In this way, we align the implement to the freescale internal IPUv3 driver. After applying this patch, an uboot hang up issue at the arch_preboot_os() stage, where we disable a relevant ipu display channel, is not observed any more on some MX6DL platforms.
--- drivers/video/ipu.h | 8 ++++++++ drivers/video/ipu_disp.c | 27 ++++++++------------------- drivers/video/ipu_regs.h | 3 +++ 3 files changed, 19 insertions(+), 19 deletions(-)
drivers/video/ipu.h +8 -0
@@ -176,6 +176,14 @@ typedef union { } ipu_channel_params_t;/* +* Enumeration of IPU interrupts. +*/ +enum ipu_irq_line { +IPU_IRQ_DP_SF_END =448 +3 , +IPU_IRQ_DC_FC_1 =448 +9 , +}; + +/* * Bitfield of Display Interface signal polarities. */ typedef struct {
drivers/video/ipu_disp.c +8 -19
@@ -666,13 +666,16 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)uint32_t csc;uint32_t dc_chan =0 ;int timeout =50 ; +int irq =0 ; dc_swap = swap;if (channel ==MEM_DC_SYNC ) { dc_chan =1 ; + irq =IPU_IRQ_DC_FC_1 ; }else if (channel ==MEM_BG_SYNC ) { dc_chan =5 ; + irq =IPU_IRQ_DP_SF_END ; }else if (channel ==MEM_FG_SYNC ) {/* Disable FG channel */ dc_chan =5 ;
@@ -723,25 +726,11 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) reg ^=DC_WR_CH_CONF_PROG_DI_ID ;__raw_writel (reg,DC_WR_CH_CONF (dc_chan)); }else { - timeout =50 ; - -/* Wait for DC triple buffer to empty */ -if (g_dc_di_assignment[dc_chan] ==0 ) -while ((__raw_readl (DC_STAT ) &0x00000002 ) - !=0x00000002 ) { -udelay (2000 ); - timeout -=2 ; -if (timeout <=0 ) -break ; - } -else if (g_dc_di_assignment[dc_chan] ==1 ) -while ((__raw_readl (DC_STAT ) &0x00000020 ) - !=0x00000020 ) { -udelay (2000 ); - timeout -=2 ; -if (timeout <=0 ) -break ; - } +/* Make sure that we leave@the irq starting edge */ +__raw_writel (IPUIRQ_2_MASK (irq),IPUIRQ_2_STATREG (irq)); +do { + reg =__raw_readl (IPUIRQ_2_STATREG (irq)); + }while (!(reg &IPUIRQ_2_MASK (irq))); reg =__raw_readl (DC_WR_CH_CONF (dc_chan)); reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK ;
drivers/video/ipu_regs.h +3 -0
@@ -313,9 +313,12 @@ struct ipu_dmfc {#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \ IPU_STAT_REG_BASE)) +#define IPU_INT_STAT (n) (&IPU_STAT->int_stat[(n) - 1])#define IPU_CHA_CUR_BUF (ch) (&IPU_STAT->cur_buf[ch / 32])#define IPU_CHA_BUF0_RDY (ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])#define IPU_CHA_BUF1_RDY (ch) (&IPU_STAT->ch_buf1_rdy[ch / 32]) +#define IPUIRQ_2_STATREG (irq) (IPU_INT_STAT(1) + ((irq) / 32)) +#define IPUIRQ_2_MASK (irq) (1UL << ((irq) & 0x1F))#define IPU_INT_CTRL (n) (&IPU_CM_REG->int_ctrl[(n) - 1])
Signature · 1 line
1.7.9.5
PATCH 1/1 video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
Hi,
Quoted 8 lines · On Fri, 28 Feb 2014 15:12:25 +0800 Liu Ying <[email protected]> wrote:
Instead of waiting for DC triple buffer to be cleared, this patch changes to wait for a relevant DP sync flow end interrupt to come when disabling sync BG flows. In this way, we align the implement to the freescale internal IPUv3 driver. After applying this patch, an uboot hang up issue at the
arch_preboot_os()stage, where we disable a relevant ipu display channel, is not observed any more on some MX6DL platforms.
Quoted 6 lines
Signed-off-by Liu Ying <[email protected]>--- drivers/video/ipu.h | 8 ++++++++ drivers/video/ipu_disp.c | 27 ++++++++------------------- drivers/video/ipu_regs.h | 3 +++ 3 files changed, 19 insertions(+), 19 deletions(-)
applied to u-boot-video/master. Thanks!
Anatolij