Skip to contentSkip to conversation

perf/x86/uncore: export basic memory events for IVT IMC PMU

PATCH In review Stephane Eranian 3 participants 5 messages Aug 12, 2014 – Aug 13, 2014

Subsystems (2)
lore
Share & tools
lore
#0 lore raw

PATCH 1/1 perf/x86/uncore: export basic memory events for IVT IMC PMU

This patch exposes two basic events for Ivytown IMC uncore PMU:

- cas_count_read: number of full-cache line reads to memory controller
- cas_count_write: number of full-cache line writes to memory controller

Those events use the same encoding as for SNB-EP, so reuse the same event table. See specification in:

http://www.intel.com/content/dam/www/public/us/en/documents/manuals/xeon-e5-2600-v2-uncore-manual.pdf

By aggregating all the read and write events from all the memory controllers of each processor socket, one can determine the total memory bandwidth utilization.

---
 arch/x86/kernel/cpu/perf_event_intel_uncore.c |    1 +
 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/perf_event_intel_uncore.c +1 -0
index cfc6f9d..800e087 100644
@@ -1391,6 +1391,7 @@ static struct intel_uncore_type ivt_uncore_imc = {
 	.fixed_ctr_bits	= 48,
 	.fixed_ctr	= SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
 	.fixed_ctl	= SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+	.event_descs	= snbep_uncore_imc_events,
 	IVT_UNCORE_PCI_COMMON_INIT(),
 };
 
Signature · 1 line
1.7.9.5
maintainer
#1 lore raw
Quoted 8 lines · Stephane Eranian
 arch/x86/kernel/cpu/perf_event_intel_uncore.c |    1 +
 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/perf_event_intel_uncore.c +0 -0
index cfc6f9d..800e087 100644

arch/x86/kernel/cpu/perf_event_intel_uncore.c static struct intel_uncore_type ivt_uncore_imc = { · line 1396

Quoted 6 lines
arch/x86/kernel/cpu/perf_event_intel_uncore.c +1 -0
@@ -1391,6 +1391,7 @@ static struct intel_uncore_type ivt_uncore_imc = {
 	.fixed_ctr_bits	= 48,
 	.fixed_ctr	= SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
 	.fixed_ctl	= SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+	.event_descs	= snbep_uncore_imc_events,
 	IVT_UNCORE_PCI_COMMON_INIT(),
 };

I changed that to the below; seeing how I have the uncore splitup patches.

Also, I'm very tempted to do a s/ivt/ivbep/ on that whole thing. We really should not mix all these stupid names.

---
Subject: perf/x86/uncore: export basic memory events for IVT IMC PMU
From: Stephane Eranian <[email protected]>
Date: Tue, 12 Aug 2014 08:00:31 +0200

This patch exposes two basic events for Ivytown IMC uncore PMU:

- cas_count_read: number of full-cache line reads to memory controller
- cas_count_write: number of full-cache line writes to memory controller

Those events use the same encoding as for SNB-EP, so reuse the same event table. See specification in:

http://www.intel.com/content/dam/www/public/us/en/documents/manuals/xeon-e5-2600-v2-uncore-manual.pdf

By aggregating all the read and write events from all the memory controllers of each processor socket, one can determine the total memory bandwidth utilization.

---
 arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c |    1 +
 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c +1 -0
@@ -1422,6 +1422,7 @@ static struct intel_uncore_type ivt_unco
 	.fixed_ctr_bits	= 48,
 	.fixed_ctr	= SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
 	.fixed_ctl	= SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+	.event_descs	= snbep_uncore_imc_events,
 	IVT_UNCORE_PCI_COMMON_INIT(),
 };
 
maintainer
#2 lore raw
Quoted 2 lines · Peter Zijlstra

Also, I'm very tempted to do a s/ivt/ivbep/ on that whole thing. We really should not mix all these stupid names.

---
Subject: perf/x86/uncore: Rename IvyTown to IvyBridge-EP
From: Peter Zijlstra <[email protected]>
Date: Tue Aug 12 09:15:25 CEST 2014

Keeping track of all the various CPU names is hard enough; adding extra silly names for no reason is just not helping. If we know the base arch name (IvyBridge) then we can do the client/server parts with the well known {,EP,EX} postfixes, no need to remember endless amounts of unrelated and pointless names for this.

---
 arch/x86/kernel/cpu/perf_event_intel_uncore.c       |    8 
 arch/x86/kernel/cpu/perf_event_intel_uncore.h       |    4 
 arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c |  336 ++++++++++----------
 3 files changed, 174 insertions(+), 174 deletions(-)
arch/x86/kernel/cpu/perf_event_intel_uncore.c +4 -4
@@ -880,8 +880,8 @@ static int __init uncore_pci_init(void)
 	case 45: /* Sandy Bridge-EP */
 		ret = snbep_uncore_pci_init();
 		break;
-	case 62: /* IvyTown */
-		ret = ivt_uncore_pci_init();
+	case 62: /* Ivy Bridge-EP */
+		ret = ivbep_uncore_pci_init();
 		break;
 	case 42: /* Sandy Bridge */
 		ret = snb_uncore_pci_init();
@@ -1187,8 +1187,8 @@ static int __init uncore_cpu_init(void)
 	case 47: /* Westmere-EX aka. Xeon E7 */
 		nhmex_uncore_cpu_init();
 		break;
-	case 62: /* IvyTown */
-		ivt_uncore_cpu_init();
+	case 62: /* Ivy Bridge-EP */
+		ivbep_uncore_cpu_init();
 		break;
 
 	default:
arch/x86/kernel/cpu/perf_event_intel_uncore.h +2 -2
@@ -330,8 +330,8 @@ void nhm_uncore_cpu_init(void);
 /* perf_event_intel_uncore_snbep.c */
 int snbep_uncore_pci_init(void);
 void snbep_uncore_cpu_init(void);
-int ivt_uncore_pci_init(void);
-void ivt_uncore_cpu_init(void);
+int ivbep_uncore_pci_init(void);
+void ivbep_uncore_cpu_init(void);
 
 /* perf_event_intel_uncore_nhmex.c */
 void nhmex_uncore_cpu_init(void);
arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c +168 -168

682 lines not on this page · raw message

#3 lore raw
In reply to Peter Zijlstra
Quoted 4 lines · Peter Zijlstra
Quoted 3 lines · Stephane Eranian
 arch/x86/kernel/cpu/perf_event_intel_uncore.c |    1 +
 1 file changed, 1 insertion(+)
Quoted 15 lines

arch/x86/kernel/cpu/perf_event_intel_uncore.c static struct intel_uncore_type ivt_uncore_imc = { · line 1396

Quoted 11 lines
arch/x86/kernel/cpu/perf_event_intel_uncore.c +1 -0
index cfc6f9d..800e087 100644
@@ -1391,6 +1391,7 @@ static struct intel_uncore_type ivt_uncore_imc = {
      .fixed_ctr_bits = 48,
      .fixed_ctr      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
      .fixed_ctl      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+     .event_descs    = snbep_uncore_imc_events,
      IVT_UNCORE_PCI_COMMON_INIT(),
 };

I changed that to the below; seeing how I have the uncore splitup patches.

Looks good to me.

Quoted 3 lines

Also, I'm very tempted to do a s/ivt/ivbep/ on that whole thing. We really should not mix all these stupid names.

That's okay with me.

Thanks.

Quoted 38 lines

---
Subject: perf/x86/uncore: export basic memory events for IVT IMC PMU
From: Stephane Eranian <[email protected]>
Date: Tue, 12 Aug 2014 08:00:31 +0200

This patch exposes two basic events for Ivytown IMC uncore PMU:

- cas_count_read: number of full-cache line reads to memory controller
- cas_count_write: number of full-cache line writes to memory controller

Those events use the same encoding as for SNB-EP, so reuse the same event table. See specification in:

http://www.intel.com/content/dam/www/public/us/en/documents/manuals/xeon-e5-2600-v2-uncore-manual.pdf

By aggregating all the read and write events from all the memory controllers of each processor socket, one can determine the total memory bandwidth utilization.

---
 arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c |    1 +
 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c +1 -0
@@ -1422,6 +1422,7 @@ static struct intel_uncore_type ivt_unco
        .fixed_ctr_bits = 48,
        .fixed_ctr      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
        .fixed_ctl      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+       .event_descs    = snbep_uncore_imc_events,
        IVT_UNCORE_PCI_COMMON_INIT(),
 };
 
#4 lore raw

[tip:perf/core] perf/x86/uncore: Export basic memory events for IVT IMC PMU

In reply to Stephane Eranian
perf/x86/uncore: Export basic memory events for IVT IMC PMU
Commit-ID:  85a16ef66cc8a053de80aadf13722a2c1254d346
Gitweb:     http://git.kernel.org/tip/85a16ef66cc8a053de80aadf13722a2c1254d346
Author:     Stephane Eranian <[email protected]>
AuthorDate: Tue, 12 Aug 2014 08:00:31 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Wed, 13 Aug 2014 07:51:17 +0200

perf/x86/uncore: Export basic memory events for IVT IMC PMU

This patch exposes two basic events for Ivytown IMC uncore PMU:

- cas_count_read: number of full-cache line reads to memory controller
- cas_count_write: number of full-cache line writes to memory controller

Those events use the same encoding as for SNB-EP, so reuse the same event table. See specification in:

http://www.intel.com/content/dam/www/public/us/en/documents/manuals/xeon-e5-2600-v2-uncore-manual.pdf

By aggregating all the read and write events from all the memory controllers of each processor socket, one can determine the total memory bandwidth utilization.

---
 arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c | 1 +
 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c +1 -0
index 30468f4..00bd048 100644
@@ -1422,6 +1422,7 @@ static struct intel_uncore_type ivt_uncore_imc = {
 	.fixed_ctr_bits	= 48,
 	.fixed_ctr	= SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
 	.fixed_ctl	= SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+	.event_descs	= snbep_uncore_imc_events,
 	IVT_UNCORE_PCI_COMMON_INIT(),
 };