ARM generic idle states

CPU suspend is the standard kernel interface to be used to enter low-power states on ARM64 systems. Current cpu_suspend implementation by default assumes that all low power states are losing the CPU context, so the CPU registers must be saved and cleaned to DRAM upon state entry. Furthermore, the current cpu_suspend() implementation assumes that if the CPU suspend back-end method returns when called, this has to be considered an error regardless of the return code (which can be successful) since the CPU was not expected to return from a code path that is different from cpu_resume code path - eg returning from the reset vector.

All in all this means that the current API does not cope well with low-power states that preserve the CPU context when entered (ie retention states), since first of all the context is saved for nothing on state entry for those states and a successful state entry can return as a normal function return, which is considered an error by the current CPU suspend implementation.

This patch refactors the cpu_suspend() API so that it can be split in two separate functionalities. The arm64 cpu_suspend API just provides a wrapper around CPU suspend operation hook. A new function is introduced (for architecture code use only) for states that require context saving upon entry:

__cpu_suspend(unsigned long arg, int (*fn)(unsigned long))

__cpu_suspend() saves the context on function entry and calls the so called suspend finisher (ie fn) to complete the suspend operation. The finisher is not expected to return, unless it fails in which case the error is propagated back to the __cpu_suspend caller.

The API refactoring results in the following pseudo code call sequence for a suspending CPU, when triggered from a kernel subsystem:

/*
* int cpu_suspend(unsigned long idx)
* @idx: idle state index
*/
{
-> cpu_suspend(idx)

	|---> CPU operations suspend hook called, if present
		|--> if (retention_state)
			|--> direct suspend back-end call (eg PSCI suspend)
		     else
			|--> __cpu_suspend(idx, &back_end_finisher);
}

By refactoring the cpu_suspend API this way, the CPU operations back-end has a chance to detect whether idle states require state saving or not and can call the required suspend operations accordingly either through simple function call or indirectly through __cpu_suspend() which carries out state saving and suspend finisher dispatching to complete idle state entry.

Signed-off-by Lorenzo Pieralisi <[email protected]>

CPU suspend is the standard kernel interface to be used to enter low-power states on ARM64 systems. Current cpu_suspend implementation by default assumes that all low power states are losing the CPU context, so the CPU registers must be saved and cleaned to DRAM upon state entry. Furthermore, the current cpu_suspend() implementation assumes that if the CPU suspend back-end method returns when called, this has to be considered an error regardless of the return code (which can be successful) since the CPU was not expected to return from a code path that is different from cpu_resume code path - eg returning from the reset vector.

All in all this means that the current API does not cope well with low-power states that preserve the CPU context when entered (ie retention states), since first of all the context is saved for nothing on state entry for those states and a successful state entry can return as a normal function return, which is considered an error by the current CPU suspend implementation.

This patch refactors the cpu_suspend() API so that it can be split in two separate functionalities. The arm64 cpu_suspend API just provides a wrapper around CPU suspend operation hook. A new function is introduced (for architecture code use only) for states that require context saving upon entry:

__cpu_suspend(unsigned long arg, int (*fn)(unsigned long))

__cpu_suspend() saves the context on function entry and calls the so called suspend finisher (ie fn) to complete the suspend operation. The finisher is not expected to return, unless it fails in which case the error is propagated back to the __cpu_suspend caller.

The API refactoring results in the following pseudo code call sequence for a suspending CPU, when triggered from a kernel subsystem:

/*
* int cpu_suspend(unsigned long idx)
* @idx: idle state index
*/
{
-> cpu_suspend(idx)

	|---> CPU operations suspend hook called, if present
		|--> if (retention_state)
			|--> direct suspend back-end call (eg PSCI suspend)
		     else
			|--> __cpu_suspend(idx, &back_end_finisher);
}

By refactoring the cpu_suspend API this way, the CPU operations back-end has a chance to detect whether idle states require state saving or not and can call the required suspend operations accordingly either through simple function call or indirectly through __cpu_suspend() which carries out state saving and suspend finisher dispatching to complete idle state entry.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm64/include/asm/suspend.h |  1 +
 arch/arm64/kernel/sleep.S        | 47 +++++++++++++++++++++++++++++-----------
 arch/arm64/kernel/suspend.c      | 47 ++++++++++++++++++++++++----------------
 3 files changed, 63 insertions(+), 32 deletions(-)

+===========================================
+4 - Examples
+===========================================

Documentation/devicetree/bindings/arm/idle-states.txt new file +5 -0

+
+Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
+
+cpus {
+	#size-cells = <0>;

Hi Lorenzo,

Quoted 8 lines · Lorenzo Pieralisi

+===========================================
+4 - Examples
+===========================================

Documentation/devicetree/bindings/arm/idle-states.txt new file +5 -0

+
+Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
+
+cpus {
+	#size-cells = <0>;

Documentation/devicetree/bindings/arm/idle-states.txt line 342

Quoted 10 lines

Documentation/devicetree/bindings/arm/idle-states.txt new file +10 -0

+	#address-cells = <2>;
+
+	CPU0: cpu at 0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+				   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+	};

Sorry for jumping in late. I havent gone through all the patches yet or followed on previous discussions, if somebody could answer this or point me to the discussion, it would be great.
Why is the cpu defining the possible cluster idle states? Would it be better that cluster states form a separate node, something like this -

	CLUSTER0: cluster at 0 {
		...
		cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
		cluster-idle-states = <&CLUTER_RETENTION_0, &CLUSTER_SLEEP_0>;
		};
	};	

Allowing for something like this to be defined -

	super_cluster0: cluster at 101 {
		...
		clusters = <&CLUSTER0  &CLUSTER1>;
		cluster-idle-states = <&SOC_RETENTION, &SOC_SLEEP>;
		};
	};

And each cluster-idle-state follows the general idle definition as provided in this document, and an indicator what the compising components should idle at, for this idle state to be available.

	CLUSTER_SLEEP_0: cluster-sleep at 0 {
		...
		/* sleep definition for cluster0's retention */
		min-idle-state = <CPU_SLEEP_0>;
	};

	SOC_SLEEP: cluster-sleep at 101 {
		...
		min-idle-state = <&CLUSTER_SLEEP_0>;
	};

Opens up the idle state for a lot of heirarchical possibilities, which if you think, is generally how the SoC is.

ARM based platforms implement a variety of power management schemes that allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing the OS to hardcode the state parameters in platform specific static tables whose size grows as the number of platforms supported in the kernel increases and hampers device drivers standardization.

Therefore, this patch aims at standardizing idle state device tree bindings for ARM platforms. Bindings define idle state parameters inclusive of entry methods and state latencies, to allow operating systems to retrieve the configuration entries from the device tree and initialize the related power management drivers, paving the way for common code in the kernel to deal with idle states and removing the need for static data in current and previous kernel versions.

ARM64 platforms require the DT to define an entry-method property for idle states.

On system implementing PSCI as an enable-method to enter low-power states the PSCI CPU suspend method requires the power_state parameter to be passed to the PSCI CPU suspend function.

This parameter is specific to a power state and platform specific, therefore must be provided by firmware to the OS in order to enable proper call sequence.

Thus, this patch also adds a property in the PSCI bindings that describes how the PSCI CPU suspend power_state parameter should be defined in DT in all device nodes that rely on PSCI CPU suspend method usage.

Acked-by Daniel Lezcano <[email protected]>

Acked-by Nicolas Pitre <[email protected]>

Reviewed-by Rob Herring <[email protected]>

Reviewed-by Sebastian Capella <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

---

Documentation/devicetree/bindings/arm/cpus.txt     |   8 +
.../devicetree/bindings/arm/idle-states.txt        | 679 +++++++++++++++++++++
Documentation/devicetree/bindings/arm/psci.txt     |  14 +-
3 files changed, 700 insertions(+), 1 deletion(-)

create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt

Documentation/devicetree/bindings/arm/cpus.txt +6 -0

index 298e2f6..6fd0f15 100644
@@ -219,6 +219,12 @@ nodes to be present and contain the properties described below.
 		Value type: <phandle>
 		Definition: Specifies the ACC[2] node associated with this CPU.
 
+	- cpu-idle-states
+		Usage: Optional
+		Value type: <prop-encoded-array>
+		Definition:
+			# List of phandles to idle state nodes supported
+			  by this cpu [3].
 

Example 1 (dual-cluster big.LITTLE system 32-bit):

Documentation/devicetree/bindings/arm/cpus.txt +0 -1

@@ -415,3 +421,5 @@ cpus {
--

[1] arm/msm/qcom,saw2.txt
[2] arm/msm/qcom,kpss-acc.txt
+[3] ARM Linux kernel documentation - idle states bindings

Documentation/devicetree/bindings/arm/cpus.txt +1 -0

+    Documentation/devicetree/bindings/arm/idle-states.txt

Documentation/devicetree/bindings/arm/idle-states.txt new file +313 -0

new file mode 100644
index 0000000..37375c7
@@ -0,0 +1,679 @@
+==========================================
+ARM idle states binding description
+==========================================
+
+==========================================
+1 - Introduction
+==========================================
+
+ARM systems contain HW capable of managing power consumption dynamically,
+where cores can be put in different low-power states (ranging from simple
+wfi to power gating) according to OS PM policies. The CPU states representing
+the range of dynamic idle states that a processor can enter at run-time, can be
+specified through device tree bindings representing the parameters required
+to enter/exit specific idle states on a given processor.
+
+According to the Server Base System Architecture document (SBSA, [3]), the
+power states an ARM CPU can be put into are identified by the following list:
+
+- Running
+- Idle_standby
+- Idle_retention
+- Sleep
+- Off
+
+The power states described in the SBSA document define the basic CPU states on
+top of which ARM platforms implement power management schemes that allow an OS
+PM implementation to put the processor in different idle states (which include
+states listed above; "off" state is not an idle state since it does not have
+wake-up capabilities, hence it is not considered in this document).
+
+Idle state parameters (eg entry latency) are platform specific and need to be
+characterized with bindings that provide the required information to OS PM
+code so that it can build the required tables and use them at runtime.
+
+The device tree binding definition for ARM idle states is the subject of this
+document.
+
+===========================================
+2 - idle-states definitions
+===========================================
+
+Idle states are characterized for a specific system through a set of
+timing and energy related properties, that underline the HW behaviour
+triggered upon idle states entry and exit.
+
+The following diagram depicts the CPU execution phases and related timing
+properties required to enter and exit an idle state:
+
+..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
+	    |          |           |          |          |
+
+	    |<------ entry ------->|
+	    |       latency        |
+					      |<- exit ->|
+					      |  latency |
+	    |<-------- min-residency -------->|
+		       |<-------  wakeup-latency ------->|
+
+		Diagram 1: CPU idle state execution phases
+
+EXEC:	Normal CPU execution.
+
+PREP:	Preparation phase before committing the hardware to idle mode
+	like cache flushing. This is abortable on pending wake-up
+	event conditions. The abort latency is assumed to be negligible
+	(i.e. less than the ENTRY + EXIT duration). If aborted, CPU
+	goes back to EXEC. This phase is optional. If not abortable,
+	this should be included in the ENTRY phase instead.
+
+ENTRY:	The hardware is committed to idle mode. This period must run
+	to completion up to IDLE before anything else can happen.
+
+IDLE:	This is the actual energy-saving idle period. This may last
+	between 0 and infinite time, until a wake-up event occurs.
+
+EXIT:	Period during which the CPU is brought back to operational
+	mode (EXEC).
+
+entry-latency: Worst case latency required to enter the idle state. The
+exit-latency may be guaranteed only after entry-latency has passed.
+
+min-residency: Minimum period, including preparation and entry, for a given
+idle state to be worthwhile energywise.
+
+wakeup-latency: Maximum delay between the signaling of a wake-up event and the
+CPU being able to execute normal code again. If not specified, this is assumed
+to be entry-latency + exit-latency.
+
+These timing parameters can be used by an OS in different circumstances.
+
+An idle CPU requires the expected min-residency time to select the most
+appropriate idle state based on the expected expiry time of the next IRQ
+(ie wake-up) that causes the CPU to return to the EXEC phase.
+
+An operating system scheduler may need to compute the shortest wake-up delay
+for CPUs in the system by detecting how long will it take to get a CPU out
+of an idle state, eg:
+
+wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
+
+In other words, the scheduler can make its scheduling decision by selecting
+(eg waking-up) the CPU with the shortest wake-up latency.
+The wake-up latency must take into account the entry latency if that period
+has not expired. The abortable nature of the PREP period can be ignored
+if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
+the worst case since it depends on the CPU operating conditions, ie caches
+state).
+
+An OS has to reliably probe the wakeup-latency since some devices can enforce
+latency constraints guarantees to work properly, so the OS has to detect the
+worst case wake-up latency it can incur if a CPU is allowed to enter an
+idle state, and possibly to prevent that to guarantee reliable device
+functioning.
+
+The min-residency time parameter deserves further explanation since it is
+expressed in time units but must factor in energy consumption coefficients.
+
+The energy consumption of a cpu when it enters a power state can be roughly
+characterised by the following graph:
+
+               |
+               |
+               |
+           e   |
+           n   |                                      /---
+           e   |                               /------
+           r   |                        /------
+           g   |                  /-----
+           y   |           /------
+               |       ----
+               |      /|
+               |     / |
+               |    /  |
+               |   /   |
+               |  /    |
+               | /     |
+               |/      |
+          -----|-------+----------------------------------
+              0|       1                              time(ms)
+
+		Graph 1: Energy vs time example
+
+The graph is split in two parts delimited by time 1ms on the X-axis.
+The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
+and denotes the energy costs incurred whilst entering and leaving the idle
+state.
+The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
+shallower slope and essentially represents the energy consumption of the idle
+state.
+
+min-residency is defined for a given idle state as the minimum expected
+residency time for a state (inclusive of preparation and entry) after
+which choosing that state become the most energy efficient option. A good
+way to visualise this, is by taking the same graph above and comparing some
+states energy consumptions plots.
+
+For sake of simplicity, let's consider a system with two idle states IDLE1,
+and IDLE2:
+
+          |
+          |
+          |
+          |                                                  /-- IDLE1
+       e  |                                              /---
+       n  |                                         /----
+       e  |                                     /---
+       r  |                                /-----/--------- IDLE2
+       g  |                    /-------/---------
+       y  |        ------------    /---|
+          |       /           /----    |
+          |      /        /---         |
+          |     /    /----             |
+          |    / /---                  |
+          |   ---                      |
+          |  /                         |
+          | /                          |
+          |/                           |                  time
+       ---/----------------------------+------------------------
+          |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
+                                       |
+                                IDLE2-min-residency
+
+		Graph 2: idle states min-residency example
+
+In graph 2 above, that takes into account idle states entry/exit energy
+costs, it is clear that if the idle state residency time (ie time till next
+wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
+choice energywise.
+
+This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
+than IDLE2.
+
+However, the lower power consumption (ie shallower energy curve slope) of idle
+state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
+efficient.
+
+The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
+shallower states in a system with multiple idle states) is defined
+IDLE2-min-residency and corresponds to the time when energy consumption of
+IDLE1 and IDLE2 states breaks even.
+
+The definitions provided in this section underpin the idle states
+properties specification that is the subject of the following sections.
+
+===========================================
+3 - idle-states node
+===========================================
+
+ARM processor idle states are defined within the idle-states node, which is
+a direct child of the cpus node [1] and provides a container where the
+processor idle states, defined as device tree nodes, are listed.
+
+- idle-states node
+
+	Usage: Optional - On ARM systems, it is a container of processor idle
+			  states nodes. If the system does not provide CPU
+			  power management capabilities or the processor just
+			  supports idle_standby an idle-states node is not
+			  required.
+
+	Description: idle-states node is a container node, where its
+		     subnodes describe the CPU idle states.
+
+	Node name must be "idle-states".
+
+	The idle-states node's parent node must be the cpus node.
+
+	The idle-states node's child nodes can be:
+
+	- one or more state nodes
+
+	Any other configuration is considered invalid.
+
+	An idle-states node defines the following properties:
+
+	- entry-method
+		Value type: <stringlist>
+		Usage and definition depend on ARM architecture version.
+			# On ARM v8 64-bit this property is required and must
+			  be one of:
+			   - "psci" (see bindings in [2])
+			# On ARM 32-bit systems this property is optional
+
+The nodes describing the idle states (state) can only be defined within the
+idle-states node, any other configuration is considered invalid and therefore
+must be ignored.
+
+===========================================
+4 - state node
+===========================================
+
+A state node represents an idle state description and must be defined as
+follows:
+
+- state node
+
+	Description: must be child of the idle-states node
+
+	The state node name shall follow standard device tree naming
+	rules ([5], 2.2.1 "Node names"), in particular state nodes which
+	are siblings within a single common parent must be given a unique name.
+
+	The idle state entered by executing the wfi instruction (idle_standby
+	SBSA,[3][4]) is considered standard on all ARM platforms and therefore
+	must not be listed.
+
+	With the definitions provided above, the following list represents
+	the valid properties for a state node:
+
+	- compatible
+		Usage: Required
+		Value type: <stringlist>
+		Definition: Must be "arm,idle-state".
+
+	- local-timer-stop
+		Usage: See definition
+		Value type: <none>
+		Definition: if present the CPU local timer control logic is
+			    lost on state entry, otherwise it is retained.
+
+	- entry-latency-us
+		Usage: Required
+		Value type: <prop-encoded-array>
+		Definition: u32 value representing worst case latency in
+			    microseconds required to enter the idle state.
+			    The exit-latency-us duration may be guaranteed
+			    only after entry-latency-us has passed.
+
+	- exit-latency-us
+		Usage: Required
+		Value type: <prop-encoded-array>
+		Definition: u32 value representing worst case latency
+			    in microseconds required to exit the idle state.
+
+	- min-residency-us
+		Usage: Required
+		Value type: <prop-encoded-array>
+		Definition: u32 value representing minimum residency duration
+			    in microseconds, inclusive of preparation and
+			    entry, for this idle state to be considered
+			    worthwhile energy wise (refer to section 2 of
+			    this document for a complete description).
+
+	- wakeup-latency-us:
+		Usage: Optional
+		Value type: <prop-encoded-array>
+		Definition: u32 value representing maximum delay between the
+			    signaling of a wake-up event and the CPU being
+			    able to execute normal code again. If omitted,
+			    this is assumed to be equal to:
+
+				entry-latency-us + exit-latency-us
+

Documentation/devicetree/bindings/arm/idle-states.txt new file +356 -0

+
+===========================================
+4 - Examples
+===========================================
+
+Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <2>;
+
+	CPU0: cpu at 0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x0>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+				   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU1: cpu at 1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x1>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+				   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU2: cpu at 100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x100>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+				   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU3: cpu at 101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x101>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+				   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU4: cpu at 10000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10000>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+				   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU5: cpu at 10001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10001>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+				   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU6: cpu at 10100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10100>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+				   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU7: cpu at 10101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a57";
+		reg = <0x0 0x10101>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+				   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU8: cpu at 100000000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x1 0x0>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+				   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU9: cpu at 100000001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x1 0x1>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+				   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU10: cpu at 100000100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x1 0x100>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+				   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU11: cpu at 100000101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x1 0x101>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+				   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU12: cpu at 100010000 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x1 0x10000>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+				   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU13: cpu at 100010001 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x1 0x10001>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+				   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU14: cpu at 100010100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x1 0x10100>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+				   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU15: cpu at 100010101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a53";
+		reg = <0x1 0x10101>;
+		enable-method = "psci";
+		cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+				   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+	};
+
+	idle-states {
+		entry-method = "arm,psci";
+
+		CPU_RETENTION_0_0: cpu-retention-0-0 {
+			compatible = "arm,idle-state";
+			arm,psci-suspend-param = <0x0010000>;
+			entry-latency-us = <20>;
+			exit-latency-us = <40>;
+			min-residency-us = <80>;
+		};
+
+		CLUSTER_RETENTION_0: cluster-retention-0 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			arm,psci-suspend-param = <0x1010000>;
+			entry-latency-us = <50>;
+			exit-latency-us = <100>;
+			min-residency-us = <250>;
+			wakeup-latency-us = <130>;
+		};
+
+		CPU_SLEEP_0_0: cpu-sleep-0-0 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			arm,psci-suspend-param = <0x0010000>;
+			entry-latency-us = <250>;
+			exit-latency-us = <500>;
+			min-residency-us = <950>;
+		};
+
+		CLUSTER_SLEEP_0: cluster-sleep-0 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			arm,psci-suspend-param = <0x1010000>;
+			entry-latency-us = <600>;
+			exit-latency-us = <1100>;
+			min-residency-us = <2700>;
+			wakeup-latency-us = <1500>;
+		};
+
+		CPU_RETENTION_1_0: cpu-retention-1-0 {
+			compatible = "arm,idle-state";
+			arm,psci-suspend-param = <0x0010000>;
+			entry-latency-us = <20>;
+			exit-latency-us = <40>;
+			min-residency-us = <90>;
+		};
+
+		CLUSTER_RETENTION_1: cluster-retention-1 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			arm,psci-suspend-param = <0x1010000>;
+			entry-latency-us = <50>;
+			exit-latency-us = <100>;
+			min-residency-us = <270>;
+			wakeup-latency-us = <100>;
+		};
+
+		CPU_SLEEP_1_0: cpu-sleep-1-0 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			arm,psci-suspend-param = <0x0010000>;
+			entry-latency-us = <70>;
+			exit-latency-us = <100>;
+			min-residency-us = <300>;
+			wakeup-latency-us = <150>;
+		};
+
+		CLUSTER_SLEEP_1: cluster-sleep-1 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			arm,psci-suspend-param = <0x1010000>;
+			entry-latency-us = <500>;
+			exit-latency-us = <1200>;
+			min-residency-us = <3500>;
+			wakeup-latency-us = <1300>;
+		};
+	};
+
+};
+
+Example 2 (ARM 32-bit, 8-cpu system, two clusters):
+
+cpus {
+	#size-cells = <0>;
+	#address-cells = <1>;
+
+	CPU0: cpu at 0 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a15";
+		reg = <0x0>;
+		cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU1: cpu at 1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a15";
+		reg = <0x1>;
+		cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU2: cpu at 2 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a15";
+		reg = <0x2>;
+		cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU3: cpu at 3 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a15";
+		reg = <0x3>;
+		cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+	};
+
+	CPU4: cpu at 100 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x100>;
+		cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU5: cpu at 101 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x101>;
+		cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU6: cpu at 102 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x102>;
+		cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+	};
+
+	CPU7: cpu at 103 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a7";
+		reg = <0x103>;
+		cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+	};
+
+	idle-states {
+		CPU_SLEEP_0_0: cpu-sleep-0-0 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			entry-latency-us = <200>;
+			exit-latency-us = <100>;
+			min-residency-us = <400>;
+			wakeup-latency-us = <250>;
+		};
+
+		CLUSTER_SLEEP_0: cluster-sleep-0 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			entry-latency-us = <500>;
+			exit-latency-us = <1500>;
+			min-residency-us = <2500>;
+			wakeup-latency-us = <1700>;
+		};
+
+		CPU_SLEEP_1_0: cpu-sleep-1-0 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			entry-latency-us = <300>;
+			exit-latency-us = <500>;
+			min-residency-us = <900>;
+			wakeup-latency-us = <600>;
+		};
+
+		CLUSTER_SLEEP_1: cluster-sleep-1 {
+			compatible = "arm,idle-state";
+			local-timer-stop;
+			entry-latency-us = <800>;
+			exit-latency-us = <2000>;
+			min-residency-us = <6500>;
+			wakeup-latency-us = <2300>;
+		};
+	};
+
+};
+
+===========================================
+5 - References
+===========================================
+
+[1] ARM Linux Kernel documentation - CPUs bindings
+    Documentation/devicetree/bindings/arm/cpus.txt
+
+[2] ARM Linux Kernel documentation - PSCI bindings
+    Documentation/devicetree/bindings/arm/psci.txt
+
+[3] ARM Server Base System Architecture (SBSA)
+    http://infocenter.arm.com/help/index.jsp
+
+[4] ARM Architecture Reference Manuals
+    http://infocenter.arm.com/help/index.jsp
+
+[5] ePAPR standard
+    https://www.power.org/documentation/epapr-version-1-1/

Documentation/devicetree/bindings/arm/psci.txt +10 -0

index b4a58f3..5aa40ed 100644
@@ -50,6 +50,16 @@ Main node optional properties:
 
 - migrate       : Function ID for MIGRATE operation
 
+Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
+state nodes, as per bindings in [1]) must specify the following properties:
+
+- arm,psci-suspend-param
+		Usage: Required for state nodes[1] if the corresponding
+                       idle-states node entry-method property is set
+                       to "psci".
+		Value type: <u32>
+		Definition: power_state parameter to pass to the PSCI
+			    suspend call.
 

Example:

Documentation/devicetree/bindings/arm/psci.txt +0 -1

@@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
 		migrate		= <0x95c10003>;
 	};
 
-

Case 2: PSCI v0.2 only

	psci {

Documentation/devicetree/bindings/arm/psci.txt +0 -0

@@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
 
...

	};

Documentation/devicetree/bindings/arm/psci.txt +3 -0

+
+[1] Kernel documentation - ARM idle states bindings
+    Documentation/devicetree/bindings/arm/idle-states.txt

Signature · 1 line

1.9.1

Quoted 114 lines

+===========================================
+3 - idle-states node
+===========================================

Documentation/devicetree/bindings/arm/idle-states.txt new file +111 -0

+
+ARM processor idle states are defined within the idle-states node, which is
+a direct child of the cpus node [1] and provides a container where the
+processor idle states, defined as device tree nodes, are listed.
+
+- idle-states node
+
+      Usage: Optional - On ARM systems, it is a container of processor idle
+                        states nodes. If the system does not provide CPU
+                        power management capabilities or the processor just
+                        supports idle_standby an idle-states node is not
+                        required.
+
+      Description: idle-states node is a container node, where its
+                   subnodes describe the CPU idle states.
+
+      Node name must be "idle-states".
+
+      The idle-states node's parent node must be the cpus node.
+
+      The idle-states node's child nodes can be:
+
+      - one or more state nodes
+
+      Any other configuration is considered invalid.
+
+      An idle-states node defines the following properties:
+
+      - entry-method
+              Value type: <stringlist>
+              Usage and definition depend on ARM architecture version.
+                      # On ARM v8 64-bit this property is required and must
+                        be one of:
+                         - "psci" (see bindings in [2])
+                      # On ARM 32-bit systems this property is optional
+
+The nodes describing the idle states (state) can only be defined within the
+idle-states node, any other configuration is considered invalid and therefore
+must be ignored.
+
+===========================================
+4 - state node
+===========================================
+
+A state node represents an idle state description and must be defined as
+follows:
+
+- state node
+
+      Description: must be child of the idle-states node
+
+      The state node name shall follow standard device tree naming
+      rules ([5], 2.2.1 "Node names"), in particular state nodes which
+      are siblings within a single common parent must be given a unique name.
+
+      The idle state entered by executing the wfi instruction (idle_standby
+      SBSA,[3][4]) is considered standard on all ARM platforms and therefore
+      must not be listed.
+
+      With the definitions provided above, the following list represents
+      the valid properties for a state node:
+
+      - compatible
+              Usage: Required
+              Value type: <stringlist>
+              Definition: Must be "arm,idle-state".
+
+      - local-timer-stop
+              Usage: See definition
+              Value type: <none>
+              Definition: if present the CPU local timer control logic is
+                          lost on state entry, otherwise it is retained.
+
+      - entry-latency-us
+              Usage: Required
+              Value type: <prop-encoded-array>
+              Definition: u32 value representing worst case latency in
+                          microseconds required to enter the idle state.
+                          The exit-latency-us duration may be guaranteed
+                          only after entry-latency-us has passed.
+
+      - exit-latency-us
+              Usage: Required
+              Value type: <prop-encoded-array>
+              Definition: u32 value representing worst case latency
+                          in microseconds required to exit the idle state.
+
+      - min-residency-us
+              Usage: Required
+              Value type: <prop-encoded-array>
+              Definition: u32 value representing minimum residency duration
+                          in microseconds, inclusive of preparation and
+                          entry, for this idle state to be considered
+                          worthwhile energy wise (refer to section 2 of
+                          this document for a complete description).
+
+      - wakeup-latency-us:
+              Usage: Optional
+              Value type: <prop-encoded-array>
+              Definition: u32 value representing maximum delay between the
+                          signaling of a wake-up event and the CPU being
+                          able to execute normal code again. If omitted,
+                          this is assumed to be equal to:
+
+                              entry-latency-us + exit-latency-us
+
+                          It is important to supply this value on systems
+                          where the duration of PREP phase (see diagram 1,
+                          section 2) is non-neglibigle.
+                          In such systems entry-latency-us + exit-latency-us
+                          will exceed wakeup-latency-us by this duration.

Documentation/devicetree/bindings/arm/idle-states.txt line 323

Quoted 5 lines

Documentation/devicetree/bindings/arm/idle-states.txt new file +5 -0

+
+      In addition to the properties listed above, a state node may require
+      additional properties specifics to the entry-method defined in the
+      idle-states node, please refer to the entry-method bindings
+      documentation for properties definitions.

How are the different idle-states node differenciated?
Say, I want to choose a different entry point function for each of these node sepately.

Also, not all targets may support all idle states. If we do not want to enter retention on one target, while an other target might, there is no way to know what the idle state node is to set up the correct entry function.

ARM based platforms implement a variety of power management schemes that allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing the OS to hardcode the state parameters in platform specific static tables whose size grows as the number of platforms supported in the kernel increases and hampers device drivers standardization.

Therefore, this patch aims at standardizing idle state device tree bindings for ARM platforms. Bindings define idle state parameters inclusive of entry methods and state latencies, to allow operating systems to retrieve the configuration entries from the device tree and initialize the related power management drivers, paving the way for common code in the kernel to deal with idle states and removing the need for static data in current and previous kernel versions.

ARM64 platforms require the DT to define an entry-method property for idle states.

On system implementing PSCI as an enable-method to enter low-power states the PSCI CPU suspend method requires the power_state parameter to be passed to the PSCI CPU suspend function.

This parameter is specific to a power state and platform specific, therefore must be provided by firmware to the OS in order to enable proper call sequence.

Thus, this patch also adds a property in the PSCI bindings that describes how the PSCI CPU suspend power_state parameter should be defined in DT in all device nodes that rely on PSCI CPU suspend method usage.

Acked-by Daniel Lezcano <[email protected]>

Acked-by Nicolas Pitre <[email protected]>

Reviewed-by Rob Herring <[email protected]>

Reviewed-by Sebastian Capella <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.txt     |   8 +
 .../devicetree/bindings/arm/idle-states.txt        | 679 +++++++++++++++++++++
 Documentation/devicetree/bindings/arm/psci.txt     |  14 +-
 3 files changed, 700 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt

On most common ARM systems, the low-power states a CPU can be put into are not discoverable in HW and require device tree bindings to describe power down suspend operations and idle states parameters.

In order to enable DT based idle states and configure idle drivers, this patch implements the bulk infrastructure required to parse the device tree idle states bindings and initialize the corresponding CPUidle driver states data.

The parsing API accepts a start index that defines the first idle state that should be initialized by the parsing code in order to give new and legacy driver flexibility over which states should be parsed using the new DT mechanism.

The idle states list is obtained from the first cpu in the driver cpumask, which implicitly means the parsing code expects idle states (and related list of phandles) to be the same for all CPUs in the CPUidle driver mask. The kernel does not check this assumption, it must be enforced by the bootloader to ensure correct system behaviour.

Quoted 14 lines · Lorenzo Pieralisi

On most common ARM systems, the low-power states a CPU can be put into are not discoverable in HW and require device tree bindings to describe power down suspend operations and idle states parameters.

In order to enable DT based idle states and configure idle drivers, this patch implements the bulk infrastructure required to parse the device tree idle states bindings and initialize the corresponding CPUidle driver states data.

The parsing API accepts a start index that defines the first idle state that should be initialized by the parsing code in order to give new and legacy driver flexibility over which states should be parsed using the new DT mechanism.

Quoted 5 lines

The idle states list is obtained from the first cpu in the driver cpumask, which implicitly means the parsing code expects idle states (and related list of phandles) to be the same for all CPUs in the CPUidle driver mask. The kernel does not check this assumption, it must be enforced by the bootloader to ensure correct system behaviour.

Can we make the kernel a little less reliant on bootloader to ensure correct system behaviour please? If assumptions are assumed by the kernel, it should at least print a warning and simply ignore the information when such assumption are not respected.

drivers/cpuidle/dt_idle_states.c line 103

Quoted 6 lines

drivers/cpuidle/dt_idle_states.c new file +6 -0

+	/*
+	 * We get the idle states for the first logical cpu in the
+	 * driver mask. The kernel does not check idle states on all
+	 * cpus in the driver mask, they are assumed to be the same
+	 * by default.
+	 */

What if they're not?

Quoted 22 lines · Nicolas Pitre

Quoted 14 lines · Lorenzo Pieralisi

On most common ARM systems, the low-power states a CPU can be put into are not discoverable in HW and require device tree bindings to describe power down suspend operations and idle states parameters.

In order to enable DT based idle states and configure idle drivers, this patch implements the bulk infrastructure required to parse the device tree idle states bindings and initialize the corresponding CPUidle driver states data.

The parsing API accepts a start index that defines the first idle state that should be initialized by the parsing code in order to give new and legacy driver flexibility over which states should be parsed using the new DT mechanism.

Quoted 5 lines

The idle states list is obtained from the first cpu in the driver cpumask, which implicitly means the parsing code expects idle states (and related list of phandles) to be the same for all CPUs in the CPUidle driver mask. The kernel does not check this assumption, it must be enforced by the bootloader to ensure correct system behaviour.

Quoted 4 lines

Can we make the kernel a little less reliant on bootloader to ensure correct system behaviour please? If assumptions are assumed by the kernel, it should at least print a warning and simply ignore the information when such assumption are not respected.

I think the check adds complexity (it means stashing the idle states phandles for the first cpu, loop through the cpus in the mask and compare the phandles to the ones stashed for the first cpu for all cpus in the driver mask) for not much.

I was told that it is not up to the kernel to validate the DT, but if you want I can implement the check even though I really think it is overkill.

On Wed, 13 Aug 2014, Lorenzo Pieralisi wrote:

Quoted 11 lines

Quoted 10 lines

Quoted 5 lines

The idle states list is obtained from the first cpu in the driver cpumask, which implicitly means the parsing code expects idle states (and related list of phandles) to be the same for all CPUs in the CPUidle driver mask. The kernel does not check this assumption, it must be enforced by the bootloader to ensure correct system behaviour.

Can we make the kernel a little less reliant on bootloader to ensure correct system behaviour please? If assumptions are assumed by the kernel, it should at least print a warning and simply ignore the information when such assumption are not respected.

Quoted 8 lines

I think the check adds complexity (it means stashing the idle states phandles for the first cpu, loop through the cpus in the mask and compare the phandles to the ones stashed for the first cpu for all cpus in the driver mask) for not much.

I was told that it is not up to the kernel to validate the DT, but if you want I can implement the check even though I really think it is overkill.

DT validation is not the same as resiliance against messed-up DT content. If the kernel is going to boot regardless then this is fine. If the kernel is going to crash, or work suboptimally without returning a clue because some implicit assumptions are not respected then this is bad.

And people _will_ mess up their DT from time to time.

So if you tell me a messed-up DT won't bear much consequences then I'm fine with that.

Quoted 2 lines · Nicolas Pitre

So if you tell me a messed-up DT won't bear much consequences then I'm fine with that.

Nico, on second thoughts, since Ashwin raised the point too and I think that at these early stages it might turn out useful, I gave coding the check a go. I tried to make the check self contained so that we can yank it out if we do not want it in the final version or we will want to remove it later.

Here the refreshed patch is:

-- >8 --
Subject: [PATCH] drivers: cpuidle: implement DT based idle states
infrastructure

On most common ARM systems, the low-power states a CPU can be put into are not discoverable in HW and require device tree bindings to describe power down suspend operations and idle states parameters.

In order to enable DT based idle states and configure idle drivers, this patch implements the bulk infrastructure required to parse the device tree idle states bindings and initialize the corresponding CPUidle driver states data.

The parsing API accepts a start index that defines the first idle state that should be initialized by the parsing code in order to give new and legacy driver flexibility over which states should be parsed using the new DT mechanism.

The idle states list is obtained from the first cpu in the driver cpumask, which implicitly means the parsing code expects idle states (and related list of phandles) to be the same for all CPUs in the CPUidle driver mask. The kernel does not check this assumption, it must be enforced by the bootloader to ensure correct system behaviour.

Quoted 30 lines · Lorenzo Pieralisi

Quoted 2 lines · Nicolas Pitre

So if you tell me a messed-up DT won't bear much consequences then I'm fine with that.

Nico, on second thoughts, since Ashwin raised the point too and I think that at these early stages it might turn out useful, I gave coding the check a go. I tried to make the check self contained so that we can yank it out if we do not want it in the final version or we will want to remove it later.

Here the refreshed patch is:

-- >8 --
Subject: [PATCH] drivers: cpuidle: implement DT based idle states
infrastructure

On most common ARM systems, the low-power states a CPU can be put into are not discoverable in HW and require device tree bindings to describe power down suspend operations and idle states parameters.

In order to enable DT based idle states and configure idle drivers, this patch implements the bulk infrastructure required to parse the device tree idle states bindings and initialize the corresponding CPUidle driver states data.

The parsing API accepts a start index that defines the first idle state that should be initialized by the parsing code in order to give new and legacy driver flexibility over which states should be parsed using the new DT mechanism.

Quoted 5 lines

The idle states list is obtained from the first cpu in the driver cpumask, which implicitly means the parsing code expects idle states (and related list of phandles) to be the same for all CPUs in the CPUidle driver mask. The kernel does not check this assumption, it must be enforced by the bootloader to ensure correct system behaviour.

Is this last sentence still true?

Here the refreshed patch is:

-- >8 --
Subject: [PATCH] drivers: cpuidle: implement DT based idle states
infrastructure

On most common ARM systems, the low-power states a CPU can be put into are not discoverable in HW and require device tree bindings to describe power down suspend operations and idle states parameters.

In order to enable DT based idle states and configure idle drivers, this patch implements the bulk infrastructure required to parse the device tree idle states bindings and initialize the corresponding CPUidle driver states data.

The parsing API accepts a start index that defines the first idle state that should be initialized by the parsing code in order to give new and legacy driver flexibility over which states should be parsed using the new DT mechanism.

The idle states list is obtained from the first cpu in the driver cpumask, which implicitly means the parsing code expects idle states (and related list of phandles) to be the same for all CPUs in the CPUidle driver mask. The kernel does not check this assumption, it must be enforced by the bootloader to ensure correct system behaviour.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 drivers/cpuidle/Kconfig          |   3 +
 drivers/cpuidle/Makefile         |   1 +
 drivers/cpuidle/dt_idle_states.c | 175 +++++++++++++++++++++++++++++++++++++++
 drivers/cpuidle/dt_idle_states.h |   5 ++
 4 files changed, 184 insertions(+)
 create mode 100644 drivers/cpuidle/dt_idle_states.c
 create mode 100644 drivers/cpuidle/dt_idle_states.h

The CPUidle subsystem on ARM64 machines requires the idle states implementation back-end to initialize idle states parameter upon boot. This patch adds a hook in the CPU operations structure that should be initialized by the CPU operations back-end in order to provide a function that initializes cpu idle states.

This patch also adds the infrastructure to arm64 kernel required to export the CPU operations based initialization interface, so that drivers (ie CPUidle) can use it when they are initialized at probe time.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm64/include/asm/cpu_ops.h |  3 +++
 arch/arm64/include/asm/cpuidle.h | 13 +++++++++++++
 arch/arm64/kernel/Makefile       |  1 +
 arch/arm64/kernel/cpuidle.c      | 29 +++++++++++++++++++++++++++++
 4 files changed, 46 insertions(+)
 create mode 100644 arch/arm64/include/asm/cpuidle.h
 create mode 100644 arch/arm64/kernel/cpuidle.c

This patch implements the cpu_suspend cpu operations method through the PSCI CPU SUSPEND API. The PSCI implementation translates the idle state index passed by the cpu_suspend core call into a valid PSCI state according to the PSCI states initialized at boot through the cpu_init_idle() CPU operations hook.

The PSCI CPU suspend operation hook checks if the PSCI state is a standby state. If it is, it calls the PSCI suspend implementation straight away, without saving any context. If the state is a power down state the kernel calls the __cpu_suspend API (that saves the CPU context) and passed the PSCI suspend finisher as a parameter so that PSCI can be called by the __cpu_suspend implementation after saving and flushing the context as last function before power down.

For power down states, entry point is set to cpu_resume physical address, that represents the default kernel execution address following a CPU reset.

Reviewed-by Ashwin Chaugule <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm64/kernel/psci.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

This patch implements a generic CPU idle driver for ARM64 machines.

It relies on the DT idle states infrastructure to initialize idle states count and respective parameters. Current code assumes the driver is managing idle states on all possible CPUs but can be easily generalized to support heterogenous systems and build cpumasks at runtime using MIDRs or DT cpu nodes compatible properties.

The driver relies on the arm64 CPU operations to call the idle initialization hook used to parse and save suspend back-end specific idle states information upon probing.

Idle state index 0 is always initialized as a simple wfi state, ie always considered present and functional on all ARM64 platforms.

Idle state indices higher than 0 trigger idle state entry by calling the cpu_suspend function, that triggers the suspend operation through the CPU operations suspend back-end hook. cpu_suspend passes the idle state index as a parameter so that the CPU operations suspend back-end can retrieve the required idle state data by using the idle state index to execute a look-up on its internal data structures.

Reviewed-by Ashwin Chaugule <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 drivers/cpuidle/Kconfig         |   5 ++
 drivers/cpuidle/Kconfig.arm64   |  14 +++++
 drivers/cpuidle/Makefile        |   4 ++
 drivers/cpuidle/cpuidle-arm64.c | 131 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 154 insertions(+)
 create mode 100644 drivers/cpuidle/Kconfig.arm64
 create mode 100644 drivers/cpuidle/cpuidle-arm64.c

drivers/cpuidle/Kconfig +5 -0

index 8deb934..c5029c1 100644
@@ -33,6 +33,11 @@ depends on ARM
 source "drivers/cpuidle/Kconfig.arm"
 endmenu
 
+menu "ARM64 CPU Idle Drivers"
+depends on ARM64
+source "drivers/cpuidle/Kconfig.arm64"
+endmenu
+
 menu "MIPS CPU Idle Drivers"
 depends on MIPS
 source "drivers/cpuidle/Kconfig.mips"

drivers/cpuidle/Kconfig.arm64 new file +14 -0

new file mode 100644
index 0000000..d0a08ed
@@ -0,0 +1,14 @@
+#
+# ARM64 CPU Idle drivers
+#
+
+config ARM64_CPUIDLE
+	bool "Generic ARM64 CPU idle Driver"
+	select ARM64_CPU_SUSPEND
+	select DT_IDLE_STATES
+	help
+	  Select this to enable generic cpuidle driver for ARM64.
+	  It provides a generic idle driver whose idle states are configured
+	  at run-time through DT nodes. The CPUidle suspend backend is
+	  initialized by calling the CPU operations init idle hook
+	  provided by architecture code.

drivers/cpuidle/Makefile +4 -0

index 002b653..4d177b9 100644
@@ -23,6 +23,10 @@ obj-$(CONFIG_ARM_EXYNOS_CPUIDLE)        += cpuidle-exynos.o
 obj-$(CONFIG_MIPS_CPS_CPUIDLE)		+= cpuidle-cps.o
 
 ###############################################################################
+# ARM64 drivers
+obj-$(CONFIG_ARM64_CPUIDLE)		+= cpuidle-arm64.o
+
+###############################################################################
 # POWERPC drivers
 obj-$(CONFIG_PSERIES_CPUIDLE)		+= cpuidle-pseries.o
 obj-$(CONFIG_POWERNV_CPUIDLE)		+= cpuidle-powernv.o

drivers/cpuidle/cpuidle-arm64.c new file +28 -0

new file mode 100644
index 0000000..25ec622
@@ -0,0 +1,131 @@
+/*
+ * ARM64 generic CPU idle driver.
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "CPUidle arm64: " fmt
+
+#include <linux/cpuidle.h>
+#include <linux/cpumask.h>
+#include <linux/cpu_pm.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+
+#include <asm/cpuidle.h>
+#include <asm/suspend.h>
+
+#include "dt_idle_states.h"
+
+/*
+ * arm_enter_idle_state - Programs CPU to enter the specified state

Quoted 123 lines · Lorenzo Pieralisi

This patch implements a generic CPU idle driver for ARM64 machines.

It relies on the DT idle states infrastructure to initialize idle states count and respective parameters. Current code assumes the driver is managing idle states on all possible CPUs but can be easily generalized to support heterogenous systems and build cpumasks at runtime using MIDRs or DT cpu nodes compatible properties.

The driver relies on the arm64 CPU operations to call the idle initialization hook used to parse and save suspend back-end specific idle states information upon probing.

Idle state index 0 is always initialized as a simple wfi state, ie always considered present and functional on all ARM64 platforms.

Idle state indices higher than 0 trigger idle state entry by calling the cpu_suspend function, that triggers the suspend operation through the CPU operations suspend back-end hook. cpu_suspend passes the idle state index as a parameter so that the CPU operations suspend back-end can retrieve the required idle state data by using the idle state index to execute a look-up on its internal data structures.

Reviewed-by Ashwin Chaugule <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 drivers/cpuidle/Kconfig         |   5 ++
 drivers/cpuidle/Kconfig.arm64   |  14 +++++
 drivers/cpuidle/Makefile        |   4 ++
 drivers/cpuidle/cpuidle-arm64.c | 131 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 154 insertions(+)
 create mode 100644 drivers/cpuidle/Kconfig.arm64
 create mode 100644 drivers/cpuidle/cpuidle-arm64.c

drivers/cpuidle/Kconfig +5 -0

index 8deb934..c5029c1 100644
@@ -33,6 +33,11 @@ depends on ARM
 source "drivers/cpuidle/Kconfig.arm"
 endmenu
 
+menu "ARM64 CPU Idle Drivers"
+depends on ARM64
+source "drivers/cpuidle/Kconfig.arm64"
+endmenu
+
 menu "MIPS CPU Idle Drivers"
 depends on MIPS
 source "drivers/cpuidle/Kconfig.mips"

drivers/cpuidle/Kconfig.arm64 new file +14 -0

new file mode 100644
index 0000000..d0a08ed
@@ -0,0 +1,14 @@
+#
+# ARM64 CPU Idle drivers
+#
+
+config ARM64_CPUIDLE
+	bool "Generic ARM64 CPU idle Driver"
+	select ARM64_CPU_SUSPEND
+	select DT_IDLE_STATES
+	help
+	  Select this to enable generic cpuidle driver for ARM64.
+	  It provides a generic idle driver whose idle states are configured
+	  at run-time through DT nodes. The CPUidle suspend backend is
+	  initialized by calling the CPU operations init idle hook
+	  provided by architecture code.

drivers/cpuidle/Makefile +4 -0

index 002b653..4d177b9 100644
@@ -23,6 +23,10 @@ obj-$(CONFIG_ARM_EXYNOS_CPUIDLE)        += cpuidle-exynos.o
 obj-$(CONFIG_MIPS_CPS_CPUIDLE)		+= cpuidle-cps.o
 
 ###############################################################################
+# ARM64 drivers
+obj-$(CONFIG_ARM64_CPUIDLE)		+= cpuidle-arm64.o
+
+###############################################################################
 # POWERPC drivers
 obj-$(CONFIG_PSERIES_CPUIDLE)		+= cpuidle-pseries.o
 obj-$(CONFIG_POWERNV_CPUIDLE)		+= cpuidle-powernv.o

drivers/cpuidle/cpuidle-arm64.c new file +33 -0

new file mode 100644
index 0000000..25ec622
@@ -0,0 +1,131 @@
+/*
+ * ARM64 generic CPU idle driver.
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "CPUidle arm64: " fmt
+
+#include <linux/cpuidle.h>
+#include <linux/cpumask.h>
+#include <linux/cpu_pm.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+
+#include <asm/cpuidle.h>
+#include <asm/suspend.h>
+
+#include "dt_idle_states.h"
+
+/*
+ * arm_enter_idle_state - Programs CPU to enter the specified state
+ *
+ * dev: cpuidle device
+ * drv: cpuidle driver
+ * idx: state index
+ *

drivers/cpuidle/cpuidle-arm64.c line 38

Quoted 5 lines

drivers/cpuidle/cpuidle-arm64.c new file +5 -0

+ * Called from the CPUidle framework to program the device to the
+ * specified target state selected by the governor.
+ */
+static int arm_enter_idle_state(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int idx)

Nitpick: for consistency, I would either prefix it arm64 or drop the prefix entirely (it's a static function anyway).

drivers/cpuidle/cpuidle-arm64.c line 62

Quoted 1 line

drivers/cpuidle/cpuidle-arm64.c new file +1 -0

+struct cpuidle_driver arm64_idle_driver = {

Should this be static?

Otherwise:

Reviewed-by Catalin Marinas <[email protected]>

drivers/cpuidle/cpuidle-arm64.c new file +21 -0

+static int __init arm64_idle_init(void)
+{
+	int i, ret;
+	struct cpuidle_driver *drv = &arm64_idle_driver;
+
+	drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
+	if (!drv->cpumask)
+		return -ENOMEM;
+
+	cpumask_copy(drv->cpumask, cpu_possible_mask);
+	/*
+	 * Initialize idle states data, starting at index 1.
+	 * This driver is DT only, if no DT idle states are detected (ret == 0)
+	 * let the driver initialization fail accordingly since there is no
+	 * reason to initialize the idle driver if only wfi is supported.
+	 */
+	ret = dt_init_idle_driver(drv, 1);
+	if (ret <= 0)
+		goto free_mem;
+	/*
+	 * Call arch CPU operations in order to initialize

Quoted 30 lines · Lorenzo Pieralisi

drivers/cpuidle/cpuidle-arm64.c new file +30 -0

+static int __init arm64_idle_init(void)
+{
+	int i, ret;
+	struct cpuidle_driver *drv = &arm64_idle_driver;
+
+	drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
+	if (!drv->cpumask)
+		return -ENOMEM;
+
+	cpumask_copy(drv->cpumask, cpu_possible_mask);
+	/*
+	 * Initialize idle states data, starting at index 1.
+	 * This driver is DT only, if no DT idle states are detected (ret == 0)
+	 * let the driver initialization fail accordingly since there is no
+	 * reason to initialize the idle driver if only wfi is supported.
+	 */
+	ret = dt_init_idle_driver(drv, 1);
+	if (ret <= 0)
+		goto free_mem;
+	/*
+	 * Call arch CPU operations in order to initialize
+	 * idle states suspend back-end specific data
+	 */
+	for_each_cpu(i, drv->cpumask) {
+		ret = cpu_init_idle(i);
+		if (ret)
+			goto free_mem;
+	}
+
+	for (i = 1; i < drv->state_count; i++)

drivers/cpuidle/cpuidle-arm64.c line 120

Quoted 1 line

drivers/cpuidle/cpuidle-arm64.c new file +1 -0

+		drv->states[i].enter = arm_enter_idle_state;

BTW, I've seen this pattern a few times already. Do you think it would be useful to change the dt_init_idle_driver() API to take a function pointer as argument and populate it there? The only drawback would be if we want different functions based on the states that have been populated (not sure whether we'll need the flexibility in the future). Either way, my ack on this patch stands.

With the introduction of DT based idle states, CPUidle drivers for ARM can now initialize idle states data through properties in the device tree.

This patch adds code to the big.LITTLE CPUidle driver to dynamically initialize idle states data through the updated device tree source file.

Cc Chander Kashyap <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 23 +++++++++++++++++++++++
 drivers/cpuidle/Kconfig.arm                |  1 +
 drivers/cpuidle/cpuidle-big_little.c       | 23 ++++++++++++++++++++++-
 3 files changed, 46 insertions(+), 1 deletion(-)

With the introduction of DT based idle states, CPUidle drivers for ARM can now initialize idle states data through properties in the device tree.

This patch adds code to the Exynos CPUidle driver to dynamically initialize idle states data through the updated device tree source files.

Cc Chander Kashyap <[email protected]>

Cc Kukjin Kim <[email protected]>

Cc Tomasz Figa <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>

---

arch/arm/boot/dts/exynos4210.dtsi | 11 +++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 11 +++++++++++
drivers/cpuidle/Kconfig.arm       |  1 +
drivers/cpuidle/cpuidle-exynos.c  | 27 ++++++++++++++++++++++++---
4 files changed, 47 insertions(+), 3 deletions(-)

arch/arm/boot/dts/exynos4210.dtsi +11 -0

index eab7c7b..69fd1a0 100644
@@ -48,12 +48,23 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0x900>;
+			cpu-idle-states = <&CLUSTER_SLEEP_0>;
 		};
 
 		cpu at 901 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0x901>;
+			cpu-idle-states = <&CLUSTER_SLEEP_0>;
+		};
+
+		idle-states {
+			CLUSTER_SLEEP_0: cluster-sleep-0 {
+				compatible = "arm,idle-state";
+				entry-latency-us = <1000>;
+				exit-latency-us = <300>;
+				min-residency-us = <100000>;
+			};
 		};
 	};
 

arch/arm/boot/dts/exynos5250.dtsi +11 -0

index 492e1ef..3a758ff 100644
@@ -63,12 +63,23 @@
 			compatible = "arm,cortex-a15";
 			reg = <0>;
 			clock-frequency = <1700000000>;
+			cpu-idle-states = <&CLUSTER_SLEEP_0>;
 		};
 		cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1700000000>;
+			cpu-idle-states = <&CLUSTER_SLEEP_0>;
+		};
+
+		idle-states {
+			CLUSTER_SLEEP_0: cluster-sleep-0 {
+				compatible = "arm,idle-state";
+				entry-latency-us = <1000>;
+				exit-latency-us = <300>;
+				min-residency-us = <100000>;
+			};
 		};
 	};
 

drivers/cpuidle/Kconfig.arm +0 -0

index e339c7f..04cc229 100644
@@ -55,6 +55,7 @@ config ARM_AT91_CPUIDLE

config ARM_EXYNOS_CPUIDLE
bool "Cpu Idle Driver for the Exynos processors" depends on ARCH_EXYNOS

drivers/cpuidle/Kconfig.arm +1 -0

+	select DT_IDLE_STATES

help
Select this to enable cpuidle for Exynos processors

drivers/cpuidle/cpuidle-exynos.c +3 -0

index ba9b34b..6dff982 100644
@@ -13,11 +13,14 @@
 #include <linux/export.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 
 #include <asm/proc-fns.h>
 #include <asm/suspend.h>
 #include <asm/cpuidle.h>
 
+#include "dt_idle_states.h"
+
 static void (*exynos_enter_aftr)(void);
 
 static int exynos_enter_lowpower(struct cpuidle_device *dev,

@@ -58,17 +61,35 @@ static struct cpuidle_driver exynos_idle_driver = {
 
 static int exynos_cpuidle_probe(struct platform_device *pdev)
 {

drivers/cpuidle/cpuidle-exynos.c +16 -1

+
+	/* Start at index 1, index 0 standard WFI */
+	ret = dt_init_idle_driver(drv, 1);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to initialize idle states\n");
+		goto free_mem;
+	}
+
+	for (i = 1; i < drv->state_count; i++)
+		drv->states[i].enter = exynos_enter_lowpower;
+
+	ret = cpuidle_register(drv, NULL);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register cpuidle driver\n");
-		return ret;
+		goto free_mem;
 	}
 
 	return 0;
+free_mem:
+	kfree(drv->cpumask);
+	return ret;
 }
 
 static struct platform_driver exynos_cpuidle_driver = {

Signature · 1 line

1.9.1

Quoted 6 lines

static int exynos_cpuidle_probe(struct platform_device *pdev) {

drivers/cpuidle/cpuidle-exynos.c +2 -1

-	int ret;
+	int ret, i;
+	struct cpuidle_driver *drv = &exynos_idle_driver;

drivers/cpuidle/cpuidle-exynos.c static struct cpuidle_driver exynos_idle_driver = { · line 71

Quoted 6 lines

	exynos_enter_aftr = (void *)(pdev->dev.platform_data);

drivers/cpuidle/cpuidle-exynos.c +3 -1

-	ret = cpuidle_register(&exynos_idle_driver, NULL);
+	drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
+	if (!drv->cpumask)
+		return -ENOMEM;

drv->cpumask would not have any cpu set. I dont see it being modified elsewhere.

Quoted 29 lines

drivers/cpuidle/cpuidle-exynos.c +12 -0

+
+	/* Start at index 1, index 0 standard WFI */
+	ret = dt_init_idle_driver(drv, 1);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to initialize idle states\n");
+		goto free_mem;
+	}
+
+	for (i = 1; i < drv->state_count; i++)
+		drv->states[i].enter = exynos_enter_lowpower;
+
+	ret = cpuidle_register(drv, NULL);

	if (ret) {
		dev_err(&pdev->dev, "failed to register cpuidle driver\n");

drivers/cpuidle/cpuidle-exynos.c +1 -1

-		return ret;
+		goto free_mem;

	}

	return 0;

drivers/cpuidle/cpuidle-exynos.c +3 -0

+free_mem:
+	kfree(drv->cpumask);
+	return ret;

}

static struct platform_driver exynos_cpuidle_driver = {

Signature · 1 line

1.9.1

On Fri, Aug 15, 2014 at 10:12:33PM +0100, Lina Iyer wrote:

[...]

Quoted 6 lines

Quoted 6 lines

static int exynos_cpuidle_probe(struct platform_device *pdev) {

drivers/cpuidle/cpuidle-exynos.c +2 -1

-	int ret;
+	int ret, i;
+	struct cpuidle_driver *drv = &exynos_idle_driver;

Quoted 8 lines

drivers/cpuidle/cpuidle-exynos.c static struct cpuidle_driver exynos_idle_driver = { · line 71

Quoted 6 lines

	exynos_enter_aftr = (void *)(pdev->dev.platform_data);

drivers/cpuidle/cpuidle-exynos.c +3 -1

-	ret = cpuidle_register(&exynos_idle_driver, NULL);
+	drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
+	if (!drv->cpumask)
+		return -ENOMEM;

drv->cpumask would not have any cpu set. I dont see it being modified elsewhere.

Gah, I should have missed that while refactoring, I can just compile test this patch so it went unnoticed. Fixed (by copying the possible mask to drv->cpumask).

Thank you !
Lorenzo

Quoted 31 lines

Quoted 30 lines

drivers/cpuidle/cpuidle-exynos.c +12 -0

+
+	/* Start at index 1, index 0 standard WFI */
+	ret = dt_init_idle_driver(drv, 1);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to initialize idle states\n");
+		goto free_mem;
+	}
+
+	for (i = 1; i < drv->state_count; i++)
+		drv->states[i].enter = exynos_enter_lowpower;
+
+	ret = cpuidle_register(drv, NULL);

	if (ret) {
		dev_err(&pdev->dev, "failed to register cpuidle driver\n");

drivers/cpuidle/cpuidle-exynos.c +1 -1

-		return ret;
+		goto free_mem;

	}

	return 0;

drivers/cpuidle/cpuidle-exynos.c +3 -0

+free_mem:
+	kfree(drv->cpumask);
+	return ret;

}

static struct platform_driver exynos_cpuidle_driver = { --
1.9.1

Quoted 19 lines · Lorenzo Pieralisi

On Fri, Aug 15, 2014 at 10:12:33PM +0100, Lina Iyer wrote:

[...]

Quoted 14 lines

drivers/cpuidle/cpuidle-exynos.c static struct cpuidle_driver exynos_idle_driver = { · line 71

Quoted 12 lines

static int exynos_cpuidle_probe(struct platform_device *pdev) {

drivers/cpuidle/cpuidle-exynos.c +2 -1

-	int ret;
+	int ret, i;
+	struct cpuidle_driver *drv = &exynos_idle_driver;

	exynos_enter_aftr = (void *)(pdev->dev.platform_data);

drivers/cpuidle/cpuidle-exynos.c +3 -1

-	ret = cpuidle_register(&exynos_idle_driver, NULL);
+	drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
+	if (!drv->cpumask)
+		return -ENOMEM;

drv->cpumask would not have any cpu set. I dont see it being modified elsewhere.

Quoted 6 lines

Gah, I should have missed that while refactoring, I can just compile test this patch so it went unnoticed. Fixed (by copying the possible mask to drv->cpumask).

Thank you !
Lorenzo

Noticed that in the big.little exynos driver as well.

With the introduction of DT based idle states, CPUidle drivers for ARM can now initialize idle states data through properties in the device tree.

This patch adds code to the Exynos CPUidle driver to dynamically initialize idle states data through the updated device tree source files.

Cc Chander Kashyap <[email protected]>

Cc Kukjin Kim <[email protected]>

Cc Tomasz Figa <[email protected]>

Signed-off-by Lorenzo Pieralisi <[email protected]>