ARM: imx: correct gpu2d_axi and gpu3d_axi clock setting
Subsystems (3)
PATCH 1/1 ARM: imx: correct gpu2d_axi and gpu3d_axi clock setting
On i.MX6Q, gpu2d_axi and gpu3d_axi are either from AXI or AHB clock, but on i.MX6DL, gpu2d_axi and gpu3d_axi are from mmdc_ch0_axi_podf, and they can NOT be gated by mmdc_ch0_axi 's clock gate, the mux option register field(CCM_CBCMR) is marked as "Reserved" now on i.MX6DL RM, so correct these two clks setting.
--- arch/arm/mach-imx/clk-imx6q.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
arch/arm/mach-imx/clk-imx6q.c +8 -2
@@ -194,6 +194,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_PLL3_80M ] =imx_clk_fixed_factor ("pll3_80m" ,"pll3_usb_otg" ,1 ,6 ); clk[IMX6QDL_CLK_PLL3_60M ] =imx_clk_fixed_factor ("pll3_60m" ,"pll3_usb_otg" ,1 ,8 ); clk[IMX6QDL_CLK_TWD ] =imx_clk_fixed_factor ("twd" ,"arm" ,1 ,2 ); +if (cpu_is_imx6dl ()) { + clk[IMX6QDL_CLK_GPU2D_AXI ] =imx_clk_fixed_factor ("gpu2d_axi" ,"mmdc_ch0_axi_podf" ,1 ,1 ); + clk[IMX6QDL_CLK_GPU3D_AXI ] =imx_clk_fixed_factor ("gpu3d_axi" ,"mmdc_ch0_axi_podf" ,1 ,1 ); + } clk[IMX6QDL_CLK_PLL4_POST_DIV ] =clk_register_divider_table (NULL ,"pll4_post_div" ,"pll4_audio" ,CLK_SET_RATE_PARENT , base +0x70 ,19 ,2 ,0 , post_div_table, &imx_ccm_lock); clk[IMX6QDL_CLK_PLL4_AUDIO_DIV ] =clk_register_divider (NULL ,"pll4_audio_div" ,"pll4_post_div" ,CLK_SET_RATE_PARENT , base +0x170 ,15 ,1 ,0 , &imx_ccm_lock);
@@ -217,8 +221,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_ESAI_SEL ] =imx_clk_mux ("esai_sel" , base +0x20 ,19 ,2 , audio_sels,ARRAY_SIZE (audio_sels)); clk[IMX6QDL_CLK_ASRC_SEL ] =imx_clk_mux ("asrc_sel" , base +0x30 ,7 ,2 , audio_sels,ARRAY_SIZE (audio_sels)); clk[IMX6QDL_CLK_SPDIF_SEL ] =imx_clk_mux ("spdif_sel" , base +0x30 ,20 ,2 , audio_sels,ARRAY_SIZE (audio_sels)); - clk[IMX6QDL_CLK_GPU2D_AXI ] =imx_clk_mux ("gpu2d_axi" , base +0x18 ,0 ,1 , gpu_axi_sels,ARRAY_SIZE (gpu_axi_sels)); - clk[IMX6QDL_CLK_GPU3D_AXI ] =imx_clk_mux ("gpu3d_axi" , base +0x18 ,1 ,1 , gpu_axi_sels,ARRAY_SIZE (gpu_axi_sels)); +if (cpu_is_imx6q ()) { + clk[IMX6QDL_CLK_GPU2D_AXI ] =imx_clk_mux ("gpu2d_axi" , base +0x18 ,0 ,1 , gpu_axi_sels,ARRAY_SIZE (gpu_axi_sels)); + clk[IMX6QDL_CLK_GPU3D_AXI ] =imx_clk_mux ("gpu3d_axi" , base +0x18 ,1 ,1 , gpu_axi_sels,ARRAY_SIZE (gpu_axi_sels)); + } clk[IMX6QDL_CLK_GPU2D_CORE_SEL ] =imx_clk_mux ("gpu2d_core_sel" , base +0x18 ,16 ,2 , gpu2d_core_sels,ARRAY_SIZE (gpu2d_core_sels)); clk[IMX6QDL_CLK_GPU3D_CORE_SEL ] =imx_clk_mux ("gpu3d_core_sel" , base +0x18 ,4 ,2 , gpu3d_core_sels,ARRAY_SIZE (gpu3d_core_sels)); clk[IMX6QDL_CLK_GPU3D_SHADER_SEL ] =imx_clk_mux ("gpu3d_shader_sel" , base +0x18 ,8 ,2 , gpu3d_shader_sels,ARRAY_SIZE (gpu3d_shader_sels));
Signature · 1 line
1.7.9.5
Shawn Guo
AppliedPATCH 1/1 ARM: imx: correct gpu2d_axi and gpu3d_axi clock setting
Quoted 8 lines · Anson Huang
On i.MX6Q,
gpu2d_axiandgpu3d_axiare either from AXI or AHB clock, but on i.MX6DL,gpu2d_axiandgpu3d_axiare frommmdc_ch0_axi_podf, and they can NOT be gated bymmdc_ch0_axi's clock gate, the mux option registerfield(CCM_CBCMR)is marked as "Reserved" now on i.MX6DL RM, so correct these two clks setting.Signed-off-by Anson Huang <[email protected]>
Applied, thanks.