net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

PATCH Superseded Fabio Estevam 4 participants 5 messages Aug 21, 2014 – Aug 22, 2014 Network drivers

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Fabio Estevam

author

2014-08-21 17:10 UTC #0 lore raw

PATCH v4 1/1 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is set in the last BD, which causes FEC transmission to fail.

As explained by Ye Li:

"The TDAR bit is set when the descriptors are all out from TX ring, but the descriptor properly is in transmitting not READY. These are two signals, and in Ic simulation, we found the TDAR always clear prior than the READY bit of last BD. In mx6solox, we use a latest version of FEC IP. It looks the intrinsic behave of TDAR bit is changed in this FEC version, not any bug in mx6sx."

Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm for the other SoCs.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v3:
- Place invalidate_dcache_range in the correct location Changes since v2:
- Poll FEC_TBD_READY after polling TDAR

Signed-off-by Fabio Estevam <[email protected]>

---
 drivers/net/fec_mxc.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

drivers/net/fec_mxc.c +12 -3

index 4cefda4..675d53c 100644
@@ -711,13 +711,22 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 			break;
 	}
 
-	if (!timeout)
+	if (!timeout) {
 		ret = -EINVAL;
+		goto out;
+	}
 
-	invalidate_dcache_range(addr, addr + size);
-	if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
+	timeout = FEC_XFER_TIMEOUT;
+	while (--timeout) {
+		invalidate_dcache_range(addr, addr + size);
+		if (!(readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY))
+			break;
+	}
+
+	if (!timeout)
 		ret = -EINVAL;
 
+out:
 	debug("fec_send: status 0x%x index %d ret %i\n",
 			readw(&fec->tbd_base[fec->tbd_index].status),
 			fec->tbd_index, ret);

Signature · 1 line

1.9.1

Marek Vasut

2014-08-21 17:18 UTC #1 lore raw

PATCH v4 1/1 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

Quoted 8 lines · Fabio Estevam

When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is set in the last BD, which causes FEC transmission to fail.
As explained by Ye Li:
"The TDAR bit is set when the descriptors are all out from TX ring, but the descriptor properly is in transmitting not READY.

Again, I do not understand this sentence :-(

Quoted 3 lines

These are two signals,
and in Ic simulation, we found the TDAR always clear prior than the READY bit of last BD.

And this is the behavior of which version of the FEC IP, the "old" one or the one present in MX6slx ?

Quoted 8 lines

In mx6solox, we use a latest version of FEC IP. It looks
the intrinsic behave of TDAR bit is changed in this FEC version, not any bug in mx6sx."
Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm for the other SoCs.
Signed-off-by Fabio Estevam <[email protected]>

[...]

Best regards,
Marek Vasut

Li Ye-B37916

2014-08-22 03:02 UTC #2 lore raw

PATCH v4 1/1 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

Hi Marek,

Quoted 10 lines · Marek Vasut

Quoted 8 lines · Fabio Estevam
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is set in the last BD, which causes FEC transmission to fail.
As explained by Ye Li:
"The TDAR bit is set when the descriptors are all out from TX ring, but the descriptor properly is in transmitting not READY.
Again, I do not understand this sentence :-(

When transmitting data, FEC internal DMA reads the TX descriptor and move the data from the buffer pointed by TX descriptor to FEC internal FIFO. All TX descriptors are managed in a ring.
We found the TDAR is cleared at DMA starting last descriptor of the ring, not at DMA having last descriptor finished. So this bit clears earlier than the READY bit of last descriptor. The delay is the time for the data sending of last descriptor.

Quoted 5 lines

Quoted 3 lines
These are two signals,
and in Ic simulation, we found the TDAR always clear prior than the READY bit of last BD.
And this is the behavior of which version of the FEC IP, the "old" one or the one present in MX6slx ?

This is the behavior of current FEC IP on mx6sx. For old ones, we did not do simulation for them, but it seems the TDAR clear at the last TX descriptor finished.

Quoted 4 lines

Quoted 4 lines
In mx6solox, we use a latest version of FEC IP. It looks
the intrinsic behave of TDAR bit is changed in this FEC version, not any bug in mx6sx."

Quoted 8 lines

Quoted 4 lines
Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm for the other SoCs.
Signed-off-by Fabio Estevam <[email protected]>
[...]
Best regards,
Marek Vasut

Best regards,
Ye Li

Marek Vasut

2014-08-22 10:26 UTC #3 lore raw

PATCH v4 1/1 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

Quoted 26 lines · On Friday, August 22, 2014 at 05:02:37 AM, Li Ye-B37916 wrote:

Hi Marek,
Quoted 11 lines · Marek Vasut
Quoted 8 lines · Fabio Estevam
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is set in the last BD, which causes FEC transmission to fail.
As explained by Ye Li:
"The TDAR bit is set when the descriptors are all out from TX ring, but the descriptor properly is in transmitting not READY.
Again, I do not understand this sentence :-(
When transmitting data, FEC internal DMA reads the TX descriptor and move the data from the buffer pointed by TX descriptor to FEC internal FIFO. All TX descriptors are managed in a ring. We found the TDAR is cleared at DMA starting last descriptor of the ring, not at DMA having last descriptor finished. So this bit clears earlier than the READY bit of last descriptor. The delay is the time for the data sending of last descriptor.
Quoted 4 lines
Quoted 3 lines
These are two signals,
and in Ic simulation, we found the TDAR always clear prior than the READY bit of last BD.

Quoted 6 lines

Quoted 2 lines
And this is the behavior of which version of the FEC IP, the "old" one or the one present in MX6slx ?
This is the behavior of current FEC IP on mx6sx. For old ones, we did not do simulation for them, but it seems the TDAR clear at the last TX descriptor finished.

Thanks for clarification. Fabio, can you please document this with a big comment in the code ?

Best regards,
Marek Vasut

Fabio Estevam

2014-08-22 21:03 UTC #4 lore raw

PATCH v4 1/1 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

Hi Marek,

Quoted 2 lines · Marek Vasut

Thanks for clarification. Fabio, can you please document this with a big comment in the code ?

Yes, I can do that in v6.

Does the below version look good?