enable HiP04 SoC

Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM framework to manage power on HiP04 SoC.

Changelog:
v16:
* Parse bootwrapper parameters in command line instead.

v13:
* Restore power down operation in MCPM.
* Fix disabling snoop filter issue in MCPM.
v12:
* Use wfi as power down state in MCPM.
* Remove wait_for_powerdown() in MCPM because wfi is used now.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/mach-hisi/Makefile   |   1 +
 arch/arm/mach-hisi/platmcpm.c | 374 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 375 insertions(+)
 create mode 100644 arch/arm/mach-hisi/platmcpm.c

arch/arm/mach-hisi/Makefile +1 -0

index ee2506b..d64831e 100644
@@ -3,4 +3,5 @@
 #
 
 obj-y	+= hisilicon.o
+obj-$(CONFIG_MCPM)		+= platmcpm.o
 obj-$(CONFIG_SMP)		+= platsmp.o hotplug.o headsmp.o

arch/arm/mach-hisi/platmcpm.c new file +74 -0

new file mode 100644
index 0000000..fc17973
@@ -0,0 +1,374 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/memblock.h>
+#include <linux/of_address.h>
+
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+
+#include "core.h"
+
+/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
+ * 1 -- unreset; 0 -- reset
+ */
+#define CORE_RESET_BIT(x)		(1 << x)
+#define NEON_RESET_BIT(x)		(1 << (x + 4))
+#define CORE_DEBUG_RESET_BIT(x)		(1 << (x + 9))
+#define CLUSTER_L2_RESET_BIT		(1 << 8)
+#define CLUSTER_DEBUG_RESET_BIT		(1 << 13)
+
+/*
+ * bits definition in SC_CPU_RESET_STATUS[x]
+ * 1 -- reset status; 0 -- unreset status
+ */
+#define CORE_RESET_STATUS(x)		(1 << x)
+#define NEON_RESET_STATUS(x)		(1 << (x + 4))
+#define CORE_DEBUG_RESET_STATUS(x)	(1 << (x + 9))
+#define CLUSTER_L2_RESET_STATUS		(1 << 8)
+#define CLUSTER_DEBUG_RESET_STATUS	(1 << 13)
+#define CORE_WFI_STATUS(x)		(1 << (x + 16))
+#define CORE_WFE_STATUS(x)		(1 << (x + 20))
+#define CORE_DEBUG_ACK(x)		(1 << (x + 24))
+
+#define SC_CPU_RESET_REQ(x)		(0x520 + (x << 3))	/* reset */
+#define SC_CPU_RESET_DREQ(x)		(0x524 + (x << 3))	/* unreset */
+#define SC_CPU_RESET_STATUS(x)		(0x1520 + (x << 3))
+
+#define FAB_SF_MODE			0x0c
+#define FAB_SF_INVLD			0x10
+
+/* bits definition in FB_SF_INVLD */
+#define FB_SF_INVLD_START		(1 << 8)
+
+#define HIP04_MAX_CLUSTERS		4
+#define HIP04_MAX_CPUS_PER_CLUSTER	4
+
+#define POLL_MSEC	10
+#define TIMEOUT_MSEC	1000
+
+struct hip04_secondary_cpu_data {
+	u32	bootwrapper_phys;
+	u32	bootwrapper_size;
+	u32	bootwrapper_magic;
+	u32	relocation_entry;
+	u32	relocation_size;
+};
+
+static void __iomem *relocation, *sysctrl, *fabric;
+static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
+static DEFINE_SPINLOCK(boot_lock);
+static struct hip04_secondary_cpu_data hip04_boot;
+static u32 fabric_phys_addr;
+
+static int __init hip04_parse_bootwrapper(char *p)
+{
+	int data[4];

arch/arm/mach-hisi/platmcpm.c new file +10 -0

+	return 0;
+}
+early_param("bootwrapper", hip04_parse_bootwrapper);
+
+static int __init hip04_parse_relocation(char *p)
+{
+	int data[3];
+
+	get_options(p, ARRAY_SIZE(data), &data[0]);
+	if (!data[0] || (data[0] < 2)) {

arch/arm/mach-hisi/platmcpm.c new file +42 -0

+{
+	int i;
+
+	for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
+		if (hip04_cpu_table[cluster][i])
+			return false;
+	return true;
+}
+
+static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
+{
+	unsigned long data;
+
+	if (!fabric)
+		BUG();
+	data = readl_relaxed(fabric + FAB_SF_MODE);
+	if (on)
+		data |= 1 << cluster;
+	else
+		data &= ~(1 << cluster);
+	writel_relaxed(data, fabric + FAB_SF_MODE);
+	while (1) {
+		if (data == readl_relaxed(fabric + FAB_SF_MODE))
+			break;
+	}
+	return;
+}
+
+static int hip04_mcpm_power_up(unsigned int cpu, unsigned int cluster)
+{
+	unsigned long data, mask;
+
+	if (!relocation || !sysctrl)
+		return -ENODEV;
+	if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
+		return -EINVAL;
+
+	spin_lock_irq(&boot_lock);
+
+	if (hip04_cpu_table[cluster][cpu])
+		goto out;
+

arch/arm/mach-hisi/platmcpm.c new file +30 -0

+			mask = CLUSTER_DEBUG_RESET_STATUS;
+			data = readl_relaxed(sysctrl + \
+					     SC_CPU_RESET_STATUS(cluster));
+		} while (data & mask);
+	}
+
+	data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+	       CORE_DEBUG_RESET_BIT(cpu);
+	writel_relaxed(data, sysctrl + SC_CPU_RESET_DREQ(cluster));
+out:
+	hip04_cpu_table[cluster][cpu]++;
+	spin_unlock_irq(&boot_lock);
+
+	return 0;
+}
+
+static void hip04_mcpm_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	bool skip_wfi = false;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	__mcpm_cpu_going_down(cpu, cluster);
+
+	spin_lock(&boot_lock);
+	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+	hip04_cpu_table[cluster][cpu]--;

arch/arm/mach-hisi/platmcpm.c new file +10 -0

+
+	__mcpm_cpu_down(cpu, cluster);
+
+	if (!skip_wfi)
+		wfi();
+}
+
+static int hip04_mcpm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int data, tries, count;

arch/arm/mach-hisi/platmcpm.c new file +61 -0

+	return 0;
+err:
+	spin_unlock(&boot_lock);
+	return -ETIMEDOUT;
+}
+
+static void hip04_mcpm_powered_up(void)
+{
+	if (!relocation)
+		return;
+	spin_lock(&boot_lock);
+	writel_relaxed(0, relocation);
+	writel_relaxed(0, relocation + 4);
+	writel_relaxed(0, relocation + 8);
+	writel_relaxed(0, relocation + 12);
+	spin_unlock(&boot_lock);
+}
+
+static void __naked hip04_mcpm_power_up_setup(unsigned int affinity_level)
+{
+	asm volatile ("			\n"
+"	cmp	r0, #0			\n"
+"	bxeq	lr			\n"
+	/* calculate fabric phys address */
+"	adr	r2, 2f			\n"
+"	ldmia	r2, {r1, r3}		\n"
+"	sub	r0, r2, r1		\n"
+"	ldr	r2, [r0, r3]		\n"
+	/* get cluster id from MPIDR */
+"	mrc	p15, 0, r0, c0, c0, 5	\n"
+"	ubfx	r1, r0, #8, #8		\n"
+	/* 1 << cluster id */
+"	mov	r0, #1			\n"
+"	mov	r3, r0, lsl r1		\n"
+"	ldr	r0, [r2, #"__stringify(FAB_SF_MODE)"]	\n"
+"	tst	r0, r3			\n"
+"	bxne	lr			\n"
+"	orr	r1, r0, r3		\n"
+"	str	r1, [r2, #"__stringify(FAB_SF_MODE)"]	\n"
+"1:	ldr	r0, [r2, #"__stringify(FAB_SF_MODE)"]	\n"
+"	tst	r0, r3			\n"
+"	beq	1b			\n"
+"	bx	lr			\n"
+
+"	.align	2			\n"
+"2:	.word	.			\n"
+"	.word	fabric_phys_addr	\n"
+	);
+}
+
+static const struct mcpm_platform_ops hip04_mcpm_ops = {
+	.power_up		= hip04_mcpm_power_up,
+	.power_down		= hip04_mcpm_power_down,
+	.wait_for_powerdown	= hip04_mcpm_wait_for_powerdown,
+	.powered_up		= hip04_mcpm_powered_up,
+};
+
+static bool __init hip04_cpu_table_init(void)
+{
+	unsigned int mpidr, cpu, cluster;
+

arch/arm/mach-hisi/platmcpm.c new file +48 -0

+	hip04_cpu_table[cluster][cpu] = 1;
+	return true;
+}
+
+static int __init hip04_mcpm_init(void)
+{
+	struct device_node *np, *np_fab;
+	struct resource fab_res;
+	int ret = -ENODEV;
+
+	if (!hip04_boot.bootwrapper_phys || !hip04_boot.relocation_entry) {
+		pr_err("fail to find bootwrapper or relocation param\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
+	if (!np)
+		goto err;
+	np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
+	if (!np_fab)
+		goto err;
+
+	relocation = ioremap(hip04_boot.relocation_entry,
+			     hip04_boot.relocation_size);
+	if (!relocation) {
+		pr_err("failed to map relocation space\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+	sysctrl = of_iomap(np, 0);
+	if (!sysctrl) {
+		pr_err("failed to get sysctrl base\n");
+		ret = -ENOMEM;
+		goto err_sysctrl;
+	}
+	ret = of_address_to_resource(np_fab, 0, &fab_res);
+	if (ret) {
+		pr_err("failed to get fabric base phys\n");
+		goto err_fabric;
+	}
+	fabric_phys_addr = fab_res.start;
+	sync_cache_w(&fabric_phys_addr);
+	fabric = of_iomap(np_fab, 0);
+	if (!fabric) {
+		pr_err("failed to get fabric base\n");
+		ret = -ENOMEM;
+		goto err_fabric;

arch/arm/mach-hisi/platmcpm.c new file +9 -0

+	return ret;
+err_fabric:
+	iounmap(sysctrl);
+err_sysctrl:
+	iounmap(relocation);
+err:
+	return ret;
+}
+early_initcall(hip04_mcpm_init);

Signature · 1 line

1.9.1

Sorry for the delay -- I was on vacation.

Quoted 3 lines · Haojian Zhuang

Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM framework to manage power on HiP04 SoC.

Quoted 3 lines

Changelog:
v16:
* Parse bootwrapper parameters in command line instead.

What is that about? I don't particularly like to see bootloader handshake details passed to the kernel via the kernel command line mechanism. Given this looks like special memory regions, can't they be specified via the device tree instead?

Quoted 8 lines

v13:
* Restore power down operation in MCPM.
* Fix disabling snoop filter issue in MCPM.
v12:
* Use wfi as power down state in MCPM.
* Remove wait_for_powerdown() in MCPM because wfi is used now.

Signed-off-by Haojian Zhuang <[email protected]>

More comments below.

Quoted 101 lines

---
 arch/arm/mach-hisi/Makefile   |   1 +
 arch/arm/mach-hisi/platmcpm.c | 374 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 375 insertions(+)
 create mode 100644 arch/arm/mach-hisi/platmcpm.c

arch/arm/mach-hisi/Makefile +1 -0

index ee2506b..d64831e 100644
@@ -3,4 +3,5 @@
 #
 
 obj-y        += hisilicon.o
+obj-$(CONFIG_MCPM)           += platmcpm.o
 obj-$(CONFIG_SMP)            += platsmp.o hotplug.o headsmp.o

arch/arm/mach-hisi/platmcpm.c new file +79 -0

new file mode 100644
index 0000000..fc17973
@@ -0,0 +1,374 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/memblock.h>
+#include <linux/of_address.h>
+
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+
+#include "core.h"
+
+/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
+ * 1 -- unreset; 0 -- reset
+ */
+#define CORE_RESET_BIT(x)            (1 << x)
+#define NEON_RESET_BIT(x)            (1 << (x + 4))
+#define CORE_DEBUG_RESET_BIT(x)              (1 << (x + 9))
+#define CLUSTER_L2_RESET_BIT         (1 << 8)
+#define CLUSTER_DEBUG_RESET_BIT              (1 << 13)
+
+/*
+ * bits definition in SC_CPU_RESET_STATUS[x]
+ * 1 -- reset status; 0 -- unreset status
+ */
+#define CORE_RESET_STATUS(x)         (1 << x)
+#define NEON_RESET_STATUS(x)         (1 << (x + 4))
+#define CORE_DEBUG_RESET_STATUS(x)   (1 << (x + 9))
+#define CLUSTER_L2_RESET_STATUS              (1 << 8)
+#define CLUSTER_DEBUG_RESET_STATUS   (1 << 13)
+#define CORE_WFI_STATUS(x)           (1 << (x + 16))
+#define CORE_WFE_STATUS(x)           (1 << (x + 20))
+#define CORE_DEBUG_ACK(x)            (1 << (x + 24))
+
+#define SC_CPU_RESET_REQ(x)          (0x520 + (x << 3))      /* reset */
+#define SC_CPU_RESET_DREQ(x)         (0x524 + (x << 3))      /* unreset */
+#define SC_CPU_RESET_STATUS(x)               (0x1520 + (x << 3))
+
+#define FAB_SF_MODE                  0x0c
+#define FAB_SF_INVLD                 0x10
+
+/* bits definition in FB_SF_INVLD */
+#define FB_SF_INVLD_START            (1 << 8)
+
+#define HIP04_MAX_CLUSTERS           4
+#define HIP04_MAX_CPUS_PER_CLUSTER   4
+
+#define POLL_MSEC    10
+#define TIMEOUT_MSEC 1000
+
+struct hip04_secondary_cpu_data {
+     u32     bootwrapper_phys;
+     u32     bootwrapper_size;
+     u32     bootwrapper_magic;
+     u32     relocation_entry;
+     u32     relocation_size;
+};
+
+static void __iomem *relocation, *sysctrl, *fabric;
+static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
+static DEFINE_SPINLOCK(boot_lock);
+static struct hip04_secondary_cpu_data hip04_boot;
+static u32 fabric_phys_addr;
+
+static int __init hip04_parse_bootwrapper(char *p)
+{
+     int data[4];
+
+     get_options(p, ARRAY_SIZE(data), &data[0]);
+     if (!data[0] || (data[0] < 3)) {
+             pr_err("fail to parse bootwrapper parameters\n");
+             return -EINVAL;

arch/arm/mach-hisi/platmcpm.c line 84

Quoted 5 lines

arch/arm/mach-hisi/platmcpm.c new file +5 -0

+     }
+     hip04_boot.bootwrapper_phys = data[1];
+     hip04_boot.bootwrapper_size = data[2];
+     hip04_boot.bootwrapper_magic = data[3];
+     memblock_reserve(data[1], data[2]);

What if memblock_reserve() fails? You should at least avoid initializing hip04_boot in that case.

Quoted 15 lines

arch/arm/mach-hisi/platmcpm.c new file +15 -0

+     return 0;
+}
+early_param("bootwrapper", hip04_parse_bootwrapper);
+
+static int __init hip04_parse_relocation(char *p)
+{
+     int data[3];
+
+     get_options(p, ARRAY_SIZE(data), &data[0]);
+     if (!data[0] || (data[0] < 2)) {
+             pr_err("fail to parse relocation parameters\n");
+             return -EINVAL;
+     }
+     hip04_boot.relocation_entry = data[1];
+     hip04_boot.relocation_size = data[2];

arch/arm/mach-hisi/platmcpm.c line 104

Quoted 5 lines

arch/arm/mach-hisi/platmcpm.c new file +5 -0

+     return 0;
+}
+early_param("relocation", hip04_parse_relocation);
+
+static bool hip04_cluster_down(unsigned int cluster)

I'd suggest renaming this into hip04_cluster_is_down() as it only returns a state and performs no action.

Quoted 46 lines

arch/arm/mach-hisi/platmcpm.c new file +46 -0

+{
+     int i;
+
+     for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
+             if (hip04_cpu_table[cluster][i])
+                     return false;
+     return true;
+}
+
+static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
+{
+     unsigned long data;
+
+     if (!fabric)
+             BUG();
+     data = readl_relaxed(fabric + FAB_SF_MODE);
+     if (on)
+             data |= 1 << cluster;
+     else
+             data &= ~(1 << cluster);
+     writel_relaxed(data, fabric + FAB_SF_MODE);
+     while (1) {
+             if (data == readl_relaxed(fabric + FAB_SF_MODE))
+                     break;
+     }
+     return;
+}
+
+static int hip04_mcpm_power_up(unsigned int cpu, unsigned int cluster)
+{
+     unsigned long data, mask;
+
+     if (!relocation || !sysctrl)
+             return -ENODEV;
+     if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
+             return -EINVAL;
+
+     spin_lock_irq(&boot_lock);
+
+     if (hip04_cpu_table[cluster][cpu])
+             goto out;
+
+     /* Make secondary core out of reset. */
+     writel_relaxed(hip04_boot.bootwrapper_phys, relocation);
+     writel_relaxed(hip04_boot.bootwrapper_magic, relocation + 4);
+     writel_relaxed(virt_to_phys(mcpm_entry_point), relocation + 8);

arch/arm/mach-hisi/platmcpm.c line 156

Quoted 6 lines

arch/arm/mach-hisi/platmcpm.c new file +6 -0

+     writel_relaxed(0, relocation + 12);
+
+     if (hip04_cluster_down(cluster)) {
+             data = CLUSTER_DEBUG_RESET_BIT;
+             writel_relaxed(data, sysctrl + SC_CPU_RESET_DREQ(cluster));
+             do {

Inserting a cpu_relax() right here wouldn't hurt.

Quoted 35 lines

arch/arm/mach-hisi/platmcpm.c new file +35 -0

+                     mask = CLUSTER_DEBUG_RESET_STATUS;
+                     data = readl_relaxed(sysctrl + \
+                                          SC_CPU_RESET_STATUS(cluster));
+             } while (data & mask);
+     }
+
+     data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+            CORE_DEBUG_RESET_BIT(cpu);
+     writel_relaxed(data, sysctrl + SC_CPU_RESET_DREQ(cluster));
+out:
+     hip04_cpu_table[cluster][cpu]++;
+     spin_unlock_irq(&boot_lock);
+
+     return 0;
+}
+
+static void hip04_mcpm_power_down(void)
+{
+     unsigned int mpidr, cpu, cluster;
+     bool skip_wfi = false;
+
+     mpidr = read_cpuid_mpidr();
+     cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+     cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+     __mcpm_cpu_going_down(cpu, cluster);
+
+     spin_lock(&boot_lock);
+     BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+     hip04_cpu_table[cluster][cpu]--;
+     if (hip04_cpu_table[cluster][cpu] == 1) {
+             /* A power_up request went ahead of us. */
+             skip_wfi = true;
+     } else if (hip04_cpu_table[cluster][cpu] > 1) {
+             pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);

arch/arm/mach-hisi/platmcpm.c line 196

Quoted 5 lines

arch/arm/mach-hisi/platmcpm.c new file +5 -0

+             BUG();
+     }
+     spin_unlock(&boot_lock);
+
+     v7_exit_coherency_flush(louis);

If this is the last man, the whole cache must be flushed with v7_exit_coherency_flush(all).

Quoted 14 lines

arch/arm/mach-hisi/platmcpm.c new file +14 -0

+
+     __mcpm_cpu_down(cpu, cluster);
+
+     if (!skip_wfi)
+             wfi();
+}
+
+static int hip04_mcpm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
+{
+     unsigned int data, tries, count;
+
+     BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
+            cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
+

arch/arm/mach-hisi/platmcpm.c line 216

Quoted 6 lines

arch/arm/mach-hisi/platmcpm.c new file +6 -0

+     count = TIMEOUT_MSEC / POLL_MSEC;
+     spin_lock(&boot_lock);
+     for (tries = 0; tries < count; tries++) {
+             data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
+             if (!(data & CORE_WFI_STATUS(cpu))) {
+                     msleep(POLL_MSEC);

You can't sleep while holding a lock.

arch/arm/mach-hisi/platmcpm.c line 228

Quoted 12 lines

arch/arm/mach-hisi/platmcpm.c new file +12 -0

+                     continue;
+             }
+     }
+     if (tries >= count)
+             goto err;
+     data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+            CORE_DEBUG_RESET_BIT(cpu);
+     writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
+     for (tries = 0; tries < count; tries++) {
+             data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
+             if (!(data & CORE_RESET_STATUS(cpu))) {
+                     msleep(POLL_MSEC);

Same here.

Also I don't really like the way this MCPM method is abused to shut down a CPU because the target CPU can't do it on its own. We're getting back to this again and I suppose this is because the hardware is not able to do otherwise. However this mysterious CORE_WFI_STATUS bit made its apparition lately, so one may speculate that the hardware might be able to do more than it may seem. The lack of (english) documentation is really making a more optimal implementation impossible at this point. So I'll give in and let this pass but not without a sufficiently comprehensive comment in the code to that effect.

Now... around msleep calls you have to drop and reacquire the lock. And when the lock is reacquired you should check that the CPU count is still 0 and bail out otherwise so not to mess up with a concurrent cpu_up(). This won't be enough to prevent a race against asynchronous wake-ups though, but you are not doing any of that yet. That too would need to be documented in that comment.

arch/arm/mach-hisi/platmcpm.c line 236

Quoted 8 lines

arch/arm/mach-hisi/platmcpm.c new file +8 -0

+                     continue;
+             }
+     }
+     if (tries >= count)
+             goto err;
+     if (hip04_cluster_down(cluster))
+             hip04_set_snoop_filter(cluster, 0);
+     spin_unlock(&boot_lock);

Oh, and that ought to be spin_lock_irq()/spin_unlock_irq() here.

Quoted 61 lines

arch/arm/mach-hisi/platmcpm.c new file +61 -0

+     return 0;
+err:
+     spin_unlock(&boot_lock);
+     return -ETIMEDOUT;
+}
+
+static void hip04_mcpm_powered_up(void)
+{
+     if (!relocation)
+             return;
+     spin_lock(&boot_lock);
+     writel_relaxed(0, relocation);
+     writel_relaxed(0, relocation + 4);
+     writel_relaxed(0, relocation + 8);
+     writel_relaxed(0, relocation + 12);
+     spin_unlock(&boot_lock);
+}
+
+static void __naked hip04_mcpm_power_up_setup(unsigned int affinity_level)
+{
+     asm volatile ("                 \n"
+"    cmp     r0, #0                  \n"
+"    bxeq    lr                      \n"
+     /* calculate fabric phys address */
+"    adr     r2, 2f                  \n"
+"    ldmia   r2, {r1, r3}            \n"
+"    sub     r0, r2, r1              \n"
+"    ldr     r2, [r0, r3]            \n"
+     /* get cluster id from MPIDR */
+"    mrc     p15, 0, r0, c0, c0, 5   \n"
+"    ubfx    r1, r0, #8, #8          \n"
+     /* 1 << cluster id */
+"    mov     r0, #1                  \n"
+"    mov     r3, r0, lsl r1          \n"
+"    ldr     r0, [r2, #"__stringify(FAB_SF_MODE)"]   \n"
+"    tst     r0, r3                  \n"
+"    bxne    lr                      \n"
+"    orr     r1, r0, r3              \n"
+"    str     r1, [r2, #"__stringify(FAB_SF_MODE)"]   \n"
+"1:  ldr     r0, [r2, #"__stringify(FAB_SF_MODE)"]   \n"
+"    tst     r0, r3                  \n"
+"    beq     1b                      \n"
+"    bx      lr                      \n"
+
+"    .align  2                       \n"
+"2:  .word   .                       \n"
+"    .word   fabric_phys_addr        \n"
+     );
+}
+
+static const struct mcpm_platform_ops hip04_mcpm_ops = {
+     .power_up               = hip04_mcpm_power_up,
+     .power_down             = hip04_mcpm_power_down,
+     .wait_for_powerdown     = hip04_mcpm_wait_for_powerdown,
+     .powered_up             = hip04_mcpm_powered_up,
+};
+
+static bool __init hip04_cpu_table_init(void)
+{
+     unsigned int mpidr, cpu, cluster;
+

arch/arm/mach-hisi/platmcpm.c line 307

Quoted 10 lines

arch/arm/mach-hisi/platmcpm.c new file +10 -0

+     mpidr = read_cpuid_mpidr();
+     cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+     cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+     if (cluster >= HIP04_MAX_CLUSTERS ||
+         cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
+             pr_err("%s: boot CPU is out of bound!\n", __func__);
+             return false;
+     }
+     hip04_set_snoop_filter(0, 1);

This should be hip04_set_snoop_filter(cluster, 1).

Quoted 54 lines

arch/arm/mach-hisi/platmcpm.c new file +54 -0

+     hip04_cpu_table[cluster][cpu] = 1;
+     return true;
+}
+
+static int __init hip04_mcpm_init(void)
+{
+     struct device_node *np, *np_fab;
+     struct resource fab_res;
+     int ret = -ENODEV;
+
+     if (!hip04_boot.bootwrapper_phys || !hip04_boot.relocation_entry) {
+             pr_err("fail to find bootwrapper or relocation param\n");
+             ret = -EINVAL;
+             goto err;
+     }
+
+     np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
+     if (!np)
+             goto err;
+     np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
+     if (!np_fab)
+             goto err;
+
+     relocation = ioremap(hip04_boot.relocation_entry,
+                          hip04_boot.relocation_size);
+     if (!relocation) {
+             pr_err("failed to map relocation space\n");
+             ret = -ENOMEM;
+             goto err;
+     }
+     sysctrl = of_iomap(np, 0);
+     if (!sysctrl) {
+             pr_err("failed to get sysctrl base\n");
+             ret = -ENOMEM;
+             goto err_sysctrl;
+     }
+     ret = of_address_to_resource(np_fab, 0, &fab_res);
+     if (ret) {
+             pr_err("failed to get fabric base phys\n");
+             goto err_fabric;
+     }
+     fabric_phys_addr = fab_res.start;
+     sync_cache_w(&fabric_phys_addr);
+     fabric = of_iomap(np_fab, 0);
+     if (!fabric) {
+             pr_err("failed to get fabric base\n");
+             ret = -ENOMEM;
+             goto err_fabric;
+     }
+
+     if (!hip04_cpu_table_init())
+             return -EINVAL;
+     ret = mcpm_platform_register(&hip04_mcpm_ops);
+     if (!ret) {

arch/arm/mach-hisi/platmcpm.c line 365

Quoted 4 lines

arch/arm/mach-hisi/platmcpm.c new file +4 -0

+             mcpm_sync_init(hip04_mcpm_power_up_setup);
+             pr_info("HiP04 MCPM initialized\n");
+     }
+     mcpm_smp_set_ops();

This mcpm_smp_set_ops() should be called only if MCPM registration is successful i.e. right after mcpm_sync_init inside the if conditional above.

Quoted 13 lines

arch/arm/mach-hisi/platmcpm.c new file +9 -1

+     return ret;
+err_fabric:
+     iounmap(sysctrl);
+err_sysctrl:
+     iounmap(relocation);
+err:
+     return ret;
+}
+early_initcall(hip04_mcpm_init);
--

1.9.1

Quoted 11 lines · Nicolas Pitre

Sorry for the delay -- I was on vacation.

Quoted 6 lines · Haojian Zhuang

Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM framework to manage power on HiP04 SoC.

Changelog:
v16:
* Parse bootwrapper parameters in command line instead.

Quoted 5 lines

What is that about? I don't particularly like to see bootloader handshake details passed to the kernel via the kernel command line mechanism. Given this looks like special memory regions, can't they be specified via the device tree instead?

Others don't agree put them into DTS file. So I move them into command line.

Quoted 18 lines · Haojian Zhuang

Quoted 16 lines · Nicolas Pitre

Sorry for the delay -- I was on vacation.

Quoted 6 lines · Haojian Zhuang

Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM framework to manage power on HiP04 SoC.

Changelog:
v16:
* Parse bootwrapper parameters in command line instead.

What is that about? I don't particularly like to see bootloader handshake details passed to the kernel via the kernel command line mechanism. Given this looks like special memory regions, can't they be specified via the device tree instead?

Quoted 1 line

Others don't agree put them into DTS file. So I move them into command line.

Could you give me a pointer to the discussion around that please?

Nicolas

Quoted 25 lines · Nicolas Pitre

Quoted 12 lines · Haojian Zhuang

Quoted 11 lines · Nicolas Pitre

Sorry for the delay -- I was on vacation.

Quoted 6 lines · Haojian Zhuang

Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM framework to manage power on HiP04 SoC.

Changelog:
v16:
* Parse bootwrapper parameters in command line instead.

Quoted 7 lines

Quoted 5 lines

What is that about? I don't particularly like to see bootloader handshake details passed to the kernel via the kernel command line mechanism. Given this looks like special memory regions, can't they be specified via the device tree instead?

Others don't agree put them into DTS file. So I move them into command line.

Could you give me a pointer to the discussion around that please?

Quoted 1 line

Nicolas

http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/275944.html

Mark challenged what's relationship between bootwrapper address and system controller.

Actually code in bootwrapper is like trampoline. And it's a software protocol, not hardware description. So I moved them into command line instead.

Quoted 26 lines · Haojian Zhuang

Quoted 25 lines · Nicolas Pitre

Quoted 12 lines · Haojian Zhuang

Quoted 11 lines · Nicolas Pitre

Sorry for the delay -- I was on vacation.

Quoted 6 lines · Haojian Zhuang

Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM framework to manage power on HiP04 SoC.

Changelog:
v16:
* Parse bootwrapper parameters in command line instead.

Quoted 7 lines

Quoted 5 lines

What is that about? I don't particularly like to see bootloader handshake details passed to the kernel via the kernel command line mechanism. Given this looks like special memory regions, can't they be specified via the device tree instead?

Others don't agree put them into DTS file. So I move them into command line.

Could you give me a pointer to the discussion around that please?

Quoted 6 lines

Quoted 1 line

Nicolas

http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/275944.html

Mark challenged what's relationship between bootwrapper address and system controller.

There is no relation, obviously. Hence this doesn't belong in the system controller node. That doesn't mean it should not be in DT at all.

Quoted 3 lines

Actually code in bootwrapper is like trampoline. And it's a software protocol, not hardware description. So I moved them into command line instead.

There are many examples for software protocols being specified in DT already. The first that comes to my mind is the "boot method = spin table" which has nothing to do with hardware. PSCI bindings are about another software-only thing.

Nicolas

Quoted 49 lines · Nicolas Pitre

Quoted 26 lines · Haojian Zhuang

Quoted 25 lines · Nicolas Pitre

Quoted 12 lines · Haojian Zhuang

Quoted 11 lines · Nicolas Pitre

Sorry for the delay -- I was on vacation.

Quoted 6 lines · Haojian Zhuang

Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM framework to manage power on HiP04 SoC.

Changelog:
v16:
* Parse bootwrapper parameters in command line instead.

Quoted 7 lines

Quoted 5 lines

What is that about? I don't particularly like to see bootloader handshake details passed to the kernel via the kernel command line mechanism. Given this looks like special memory regions, can't they be specified via the device tree instead?

Others don't agree put them into DTS file. So I move them into command line.

Could you give me a pointer to the discussion around that please?

Quoted 6 lines

Quoted 1 line

Nicolas

http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/275944.html

Mark challenged what's relationship between bootwrapper address and system controller.

There is no relation, obviously. Hence this doesn't belong in the system controller node. That doesn't mean it should not be in DT at all.

Quoted 3 lines

Actually code in bootwrapper is like trampoline. And it's a software protocol, not hardware description. So I moved them into command line instead.

There are many examples for software protocols being specified in DT already. The first that comes to my mind is the "boot method = spin table" which has nothing to do with hardware. PSCI bindings are about another software-only thing.

Quoted 1 line

Nicolas

bootwrapper {
        compatible = "hisilicon,hip04-bootwrapper";
        boot-method = <0x10c00000, 0x10000, 0xa5a5a5a5, 0xe0000100, 0x1000>;
};

I changed them into this format. Could you help to review?

Quoted 50 lines · Haojian Zhuang

Quoted 49 lines · Nicolas Pitre

Quoted 26 lines · Haojian Zhuang

Quoted 25 lines · Nicolas Pitre

Quoted 12 lines · Haojian Zhuang

Quoted 11 lines · Nicolas Pitre

Sorry for the delay -- I was on vacation.

Quoted 6 lines · Haojian Zhuang

Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM framework to manage power on HiP04 SoC.

Changelog:
v16:
* Parse bootwrapper parameters in command line instead.

Quoted 7 lines

Quoted 5 lines

What is that about? I don't particularly like to see bootloader handshake details passed to the kernel via the kernel command line mechanism. Given this looks like special memory regions, can't they be specified via the device tree instead?

Others don't agree put them into DTS file. So I move them into command line.

Could you give me a pointer to the discussion around that please?

Quoted 6 lines

Quoted 1 line

Nicolas

http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/275944.html

Mark challenged what's relationship between bootwrapper address and system controller.

There is no relation, obviously. Hence this doesn't belong in the system controller node. That doesn't mean it should not be in DT at all.

Quoted 3 lines

Actually code in bootwrapper is like trampoline. And it's a software protocol, not hardware description. So I moved them into command line instead.

There are many examples for software protocols being specified in DT already. The first that comes to my mind is the "boot method = spin table" which has nothing to do with hardware. PSCI bindings are about another software-only thing.

Quoted 8 lines

Quoted 1 line

Nicolas

bootwrapper {
        compatible = "hisilicon,hip04-bootwrapper";
        boot-method = <0x10c00000, 0x10000, 0xa5a5a5a5, 0xe0000100, 0x1000>;
};

I changed them into this format. Could you help to review?

Unfortunately I'm not really knowledgeable about best device tree syntax and practices. You'll have to nag someone else for reviewing this.

One thing though, do you really need to put some magic number there? Is it likely to change? If not this could be hardcoded in the code and only describe the special memory region in DT.

Nicolas

HiP04 GIC is the variate of ARM GICv2.

ARM GICv2 supports 8 cores. HiP04 GIC extends to support 16 cores. It results that bit fields in GIC_DIST_TARGET & GIC_DIST_SOFTINT are different from ARM GICv2. And the maximium IRQ is downgrade from 1020 to 510.

Since different register offset & bitfields definitation breaks compartible with ARM GICv2, create a new hip04 irq driver.

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/irqchip/Makefile    |   1 +
 drivers/irqchip/irq-hip04.c | 429 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 430 insertions(+)
 create mode 100644 drivers/irqchip/irq-hip04.c

drivers/irqchip/Makefile +1 -0

index c57e642..23dcf45 100644
@@ -2,6 +2,7 @@ obj-$(CONFIG_IRQCHIP)			+= irqchip.o
 
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
+obj-$(CONFIG_ARCH_HIP04)		+= irq-hip04.o
 obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o

drivers/irqchip/irq-hip04.c new file +16 -0

new file mode 100644
index 0000000..751a7ee
@@ -0,0 +1,429 @@
+/*
+ * Hisilicon HiP04 INTC
+ *
+ * Copyright (C) 2002-2014 ARM Limited.
+ * Copyright (c) 2013-2014 Hisilicon Ltd.
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Interrupt architecture for the HIP04 INTC:
+ *
+ * o There is one Interrupt Distributor, which receives interrupts
+ *   from system devices and sends them to the Interrupt Controllers.
+ *

drivers/irqchip/irq-hip04.c new file +141 -0

+
+	/*
+	 * Ensure that stores to Normal memory are visible to the
+	 * other CPUs before they observe us issuing the IPI.
+	 */
+	dmb(ishst);
+
+	/* this always happens on GIC0 */
+	writel_relaxed(map << 8 | irq, hip04_data.dist_base + GIC_DIST_SOFTINT);
+
+	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
+}
+#endif
+
+static int hip04_irq_domain_map(struct irq_domain *d, unsigned int irq,
+				irq_hw_number_t hw)
+{
+	if (hw < 32) {
+		irq_set_percpu_devid(irq);
+		irq_set_chip_and_handler(irq, &hip04_irq_chip,
+					 handle_percpu_devid_irq);
+		set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
+	} else {
+		irq_set_chip_and_handler(irq, &hip04_irq_chip,
+					 handle_fasteoi_irq);
+		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	}
+	irq_set_chip_data(irq, d->host_data);
+	return 0;
+}
+
+static int hip04_irq_domain_xlate(struct irq_domain *d,
+				  struct device_node *controller,
+				  const u32 *intspec, unsigned int intsize,
+				  unsigned long *out_hwirq,
+				  unsigned int *out_type)
+{
+	unsigned long ret = 0;
+
+	if (d->of_node != controller)
+		return -EINVAL;
+	if (intsize < 3)
+		return -EINVAL;
+
+	/* Get the interrupt number and add 16 to skip over SGIs */
+	*out_hwirq = intspec[1] + 16;
+
+	/* For SPIs, we need to add 16 more to get the irq ID number */
+	if (!intspec[0])
+		*out_hwirq += 16;
+
+	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
+
+	return ret;
+}
+
+#ifdef CONFIG_SMP
+static int hip04_irq_secondary_init(struct notifier_block *nfb,
+				    unsigned long action,
+				    void *hcpu)
+{
+	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
+		hip04_irq_cpu_init(&hip04_data);
+	return NOTIFY_OK;
+}
+
+/*
+ * Notifier for enabling the INTC CPU interface. Set an arbitrarily high
+ * priority because the GIC needs to be up before the ARM generic timers.
+ */
+static struct notifier_block hip04_irq_cpu_notifier = {
+	.notifier_call	= hip04_irq_secondary_init,
+	.priority	= 100,
+};
+#endif
+
+static const struct irq_domain_ops hip04_irq_domain_ops = {
+	.map	= hip04_irq_domain_map,
+	.xlate	= hip04_irq_domain_xlate,
+};
+
+static int __init
+hip04_of_init(struct device_node *node, struct device_node *parent)
+{
+	irq_hw_number_t hwirq_base = 16;
+	int nr_irqs, irq_base, i;
+
+	if (WARN_ON(!node))
+		return -ENODEV;
+
+	hip04_data.dist_base = of_iomap(node, 0);
+	WARN(!hip04_data.dist_base, "fail to map hip04 intc dist registers\n");
+
+	hip04_data.cpu_base = of_iomap(node, 1);
+	WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n");
+
+	/*
+	 * Initialize the CPU interface map to all CPUs.
+	 * It will be refined as each CPU probes its ID.
+	 */
+	for (i = 0; i < NR_HIP04_CPU_IF; i++)
+		hip04_cpu_map[i] = 0xff;
+
+	/*
+	 * Find out how many interrupts are supported.
+	 * The HIP04 INTC only supports up to 510 interrupt sources.
+	 */
+	nr_irqs = readl_relaxed(hip04_data.dist_base + GIC_DIST_CTR) & 0x1f;
+	nr_irqs = (nr_irqs + 1) * 32;
+	if (nr_irqs > HIP04_MAX_IRQS)
+		nr_irqs = HIP04_MAX_IRQS;
+	hip04_data.nr_irqs = nr_irqs;
+
+	nr_irqs -= hwirq_base; /* calculate # of irqs to allocate */
+
+	irq_base = irq_alloc_descs(-1, hwirq_base, nr_irqs, numa_node_id());
+	if (IS_ERR_VALUE(irq_base)) {
+		pr_err("failed to allocate IRQ numbers\n");
+		return -EINVAL;
+	}
+
+	hip04_data.domain = irq_domain_add_legacy(node, nr_irqs, irq_base,
+						  hwirq_base,
+						  &hip04_irq_domain_ops,
+						  &hip04_data);
+
+	if (WARN_ON(!hip04_data.domain))
+		return -EINVAL;
+
+#ifdef CONFIG_SMP
+	set_smp_cross_call(hip04_raise_softirq);
+	register_cpu_notifier(&hip04_irq_cpu_notifier);
+#endif
+	set_handle_irq(hip04_handle_irq);
+
+	hip04_irq_dist_init(&hip04_data);
+	hip04_irq_cpu_init(&hip04_data);
+
+	return 0;
+}
+IRQCHIP_DECLARE(hip04_intc, "hisilicon,hip04-intc", hip04_of_init);

Hi,

to me this looks much better than the version integrated into irq-gic.c and is reasonably small and self-contained.

See for comments below...

Quoted 50 lines · Haojian Zhuang

HiP04 GIC is the variate of ARM GICv2.

ARM GICv2 supports 8 cores. HiP04 GIC extends to support 16 cores. It results that bit fields in GIC_DIST_TARGET & GIC_DIST_SOFTINT are different from ARM GICv2. And the maximium IRQ is downgrade from 1020 to 510.

Since different register offset & bitfields definitation breaks compartible with ARM GICv2, create a new hip04 irq driver.

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/irqchip/Makefile    |   1 +
 drivers/irqchip/irq-hip04.c | 429 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 430 insertions(+)
 create mode 100644 drivers/irqchip/irq-hip04.c

drivers/irqchip/Makefile +1 -0

index c57e642..23dcf45 100644
@@ -2,6 +2,7 @@ obj-$(CONFIG_IRQCHIP)                 += irqchip.o
 
 obj-$(CONFIG_ARCH_BCM2835)           += irq-bcm2835.o
 obj-$(CONFIG_ARCH_EXYNOS)            += exynos-combiner.o
+obj-$(CONFIG_ARCH_HIP04)             += irq-hip04.o
 obj-$(CONFIG_ARCH_MMP)                       += irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)             += irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS)                       += irq-mxs.o

drivers/irqchip/irq-hip04.c new file +16 -0

new file mode 100644
index 0000000..751a7ee
@@ -0,0 +1,429 @@
+/*
+ * Hisilicon HiP04 INTC
+ *
+ * Copyright (C) 2002-2014 ARM Limited.
+ * Copyright (c) 2013-2014 Hisilicon Ltd.
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Interrupt architecture for the HIP04 INTC:
+ *
+ * o There is one Interrupt Distributor, which receives interrupts
+ *   from system devices and sends them to the Interrupt Controllers.
+ *

drivers/irqchip/irq-hip04.c line 26

Quoted 10 lines

drivers/irqchip/irq-hip04.c new file +10 -0

+ * o There is one CPU Interface per CPU, which sends interrupts sent
+ *   by the Distributor, and interrupts generated locally, to the
+ *   associated CPU. The base address of the CPU interface is usually
+ *   aliased so that the same address points to different chips depending
+ *   on the CPU it is accessed from.
+ *
+ * Note that IRQs 0-31 are special - they are local to each CPU.
+ * As such, the enable set/clear, pending set/clear and active bit
+ * registers are banked per-cpu for these sources.
+ */

I'd find it more useful to have a reference to the GIC code here and only list the delta of the two drivers.
Since you removed (almost) any references to GIC, to an uninitiated reader it's not obvious that this is in fact a stripped and tweaked GIC.

So you could copy some of the rationale from the commit message into here, something along the lines of:
---------
This is derived from irq-gic.c to support the HiSilicon HiP04 interrupt controller, which is similar to the GIC, but deviates at some points. Support for power management, non-banked registers, cascaded GICs (and multiple controllers in general) and bigLittle support has been removed from the GIC driver.
Affinity related functions have been adjusted to match the HiSilicon hardware implementation.
---------

By the way, you removed CONFIG_CPU_PM support, is there any reason for that? I don't see an issue code-wise with keeping this in.

drivers/irqchip/irq-hip04.c line 276

Quoted 6 lines

drivers/irqchip/irq-hip04.c new file +5 -0

+
+void hip04_cpu_if_down(void)
+{
+     writel_relaxed(0, hip04_data.cpu_base + GIC_CPU_CTRL);
+}

Where is this used? The GIC counterpart is only called by some VExpress code, does your platform need a similar call? Otherwise (and since you don't seem to provide a public prototype) this function can be removed.

drivers/irqchip/irq-hip04.c line 288

Quoted 13 lines

drivers/irqchip/irq-hip04.c new file +12 -0

+
+#ifdef CONFIG_SMP
+static void hip04_raise_softirq(const struct cpumask *mask, unsigned int irq)
+{
+     int cpu;
+     unsigned long flags, map = 0;
+
+     raw_spin_lock_irqsave(&irq_controller_lock, flags);
+
+     /* Convert our logical CPU mask into a physical one. */
+     for_each_cpu(cpu, mask)
+             map |= hip04_cpu_map[cpu];

Are we sure that mask does not contain any CPU number higher than NR_HIP04_CPU_IF?

early_init_dt_add_memory_arch() accepts base & size parameters as u64 type. memblock_add() accepts base & size parameters as phys_addr_t type. But phys_addr_t isn't equal to u64. In 32-bit system, phys_addr_t is 32-bit long. If 64-bit memory address is specified in DTS file, it'll be truncated into 32-bit address.

So create two values to store base & size first as phys_addr_t type. Then compare them with u64 base & u64 size. If they don't match, discard them.

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/of/fdt.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

drivers/of/fdt.c +2 -0

index c4cddf0..10d5382 100644
@@ -878,6 +878,8 @@ int __init early_init_dt_scan_chosen(unsigned long node, const char *uname,
 void __init __weak early_init_dt_add_memory_arch(u64 base, u64 size)
 {
 	const u64 phys_offset = __pa(PAGE_OFFSET);
+	phys_addr_t mbase, msize;
+
 	base &= PAGE_MASK;
 	size &= PAGE_MASK;
 	if (base + size < phys_offset) {