mx6: imx-regs: Provide a structure for GPC registers

PATCH New Fabio Estevam 5 participants 17 messages Aug 25, 2014 – Sep 9, 2014

Subsystems (3)

Arm (32-bit) Arm i.MX and Layerscape PCI

lore

Share & tools

lore

Fabio Estevam

author

2014-08-25 17:26 UTC #0 lore raw

PATCH v3 1/3 mx6: imx-regs: Provide a structure for GPC registers

Introduce a structure for accessing the General Power Controller block (GPC) registers.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v2:
- None
Changes since v1:
- None

 arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm/include/asm/arch-mx6/imx-regs.h +13 -0

index 2631beb..22614fc 100644
@@ -419,6 +419,19 @@ struct iomuxc {
 	u32 gpr[14];
 };
 
+struct gpc {
+	u32	cntr;
+	u32	pgr;
+	u32	imr1;
+	u32	imr2;
+	u32	imr3;
+	u32	imr4;
+	u32	isr1;
+	u32	isr2;
+	u32	isr3;
+	u32	isr4;
+};
+
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16

Signature · 1 line

1.9.1

Fabio Estevam

author

2014-08-25 17:26 UTC #1 lore raw

PATCH v3 2/3 pcie_imx: Add mx6solox support

Let PCI on mx6solox also be supported.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v2:
- Configure lvds1_clk_sel in run-time
Changes since v1:
- Put the definition of gpc inside CONFIG_MX6SX ifdef
- Use setbits_le32 to configure register CNTR
- Improve comments in the code

 arch/arm/cpu/armv7/mx6/clock.c        | 17 +++++++++++----
 arch/arm/include/asm/arch-mx6/iomux.h |  9 ++++++++
 drivers/pci/pcie_imx.c                | 40 +++++++++++++++++++++++++++++++----
 3 files changed, 58 insertions(+), 8 deletions(-)

arch/arm/cpu/armv7/mx6/clock.c +13 -4

index 820b8d5..18608de 100644
@@ -509,6 +509,7 @@ int enable_pcie_clock(void)
 	struct anatop_regs *anatop_regs =
 		(struct anatop_regs *)ANATOP_BASE_ADDR;
 	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 lvds1_clk_sel;
 
 	/*
 	 * Here be dragons!

@@ -518,17 +519,25 @@ int enable_pcie_clock(void)
 	 * marked as ANATOP_MISC1 is actually documented in the PMU section
 	 * of the datasheet as PMU_MISC1.
 	 *
-	 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
-	 * enable clock OUTPUT. This is important for PCI express link that
-	 * is clocked from the i.MX6.
+	 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
+	 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
+	 * for PCI express link that is clocked from the i.MX6.
 	 */
 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN		(1 << 12)
 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN		(1 << 10)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF	0xa
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF	0xb
+
+	if (is_cpu_type(MXC_CPU_MX6SX))
+		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
+	else
+		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
+
 	clrsetbits_le32(&anatop_regs->ana_misc1,
 			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
-			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 
 	/* PCIe reference clock sourced from AXI. */
 	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);

arch/arm/include/asm/arch-mx6/iomux.h +9 -0

index f54db69..9b3a91f 100644
@@ -19,6 +19,12 @@
 #define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
 
 /*
+ * IOMUXC_GPR5 bit fields
+ */
+#define IOMUXC_GPR5_PCIE_BTNRST			(1 << 19)
+#define IOMUXC_GPR5_PCIE_PERST			(1 << 18)
+
+/*
  * IOMUXC_GPR8 bit fields
  */
 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK		(0x3f << 0)

@@ -35,12 +41,15 @@
 /*
  * IOMUXC_GPR12 bit fields
  */
+#define IOMUXC_GPR12_RX_EQ_2			(0x2 << 0)
+#define IOMUXC_GPR12_RX_EQ_MASK			(0x7 << 0)
 #define IOMUXC_GPR12_LOS_LEVEL_9		(0x9 << 4)
 #define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
 #define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x4 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
+#define IOMUXC_GPR12_TEST_POWERDOWN		(1 << 30)
 
 /*
  * IOMUXC_GPR13 bit fields

drivers/pci/pcie_imx.c +36 -4

index a3982c4..fd7e4d4 100644
@@ -23,13 +23,20 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
+#ifdef CONFIG_MX6SX
+#define MX6_DBI_ADDR	0x08ffc000
+#define MX6_IO_ADDR	0x08000000
+#define MX6_MEM_ADDR	0x08100000
+#define MX6_ROOT_ADDR	0x08f00000
+#else
 #define MX6_DBI_ADDR	0x01ffc000
-#define MX6_DBI_SIZE	0x4000
 #define MX6_IO_ADDR	0x01000000
-#define MX6_IO_SIZE	0x100000
 #define MX6_MEM_ADDR	0x01100000
-#define MX6_MEM_SIZE	0xe00000
 #define MX6_ROOT_ADDR	0x01f00000
+#endif
+#define MX6_DBI_SIZE	0x4000
+#define MX6_IO_SIZE	0x100000
+#define MX6_MEM_SIZE	0xe00000
 #define MX6_ROOT_SIZE	0xfc000
 
 /* PCIe Port Logic registers (memory-mapped) */

@@ -57,6 +64,8 @@
 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
 
+#define PCIE_PHY_PUP_REQ		(1 << 7)
+
 /* iATU registers */
 #define PCIE_ATU_VIEWPORT		0x900
 #define PCIE_ATU_REGION_INBOUND		(0x1 << 31)

@@ -421,9 +430,19 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
+#if defined(CONFIG_MX6SX)
+	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+	/* SSP_EN is not used on MX6SX anymore */
+	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	/* Force PCIe PHY reset */
+	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+	/* Power up PCIe PHY */
+	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+#else
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
 	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
 	return 0;
 }

@@ -441,6 +460,12 @@ static int imx6_pcie_init_phy(void)
 			IOMUXC_GPR12_LOS_LEVEL_MASK,
 			IOMUXC_GPR12_LOS_LEVEL_9);
 
+#ifdef CONFIG_MX6SX
+	clrsetbits_le32(&iomuxc_regs->gpr[12],
+			IOMUXC_GPR12_RX_EQ_MASK,
+			IOMUXC_GPR12_RX_EQ_2);
+#endif
+
 	writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
 	       (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
 	       (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |

@@ -517,9 +542,16 @@ static int imx6_pcie_deassert_core_reset(void)
 	 */
 	mdelay(50);
 
+#if defined(CONFIG_MX6SX)
+	/* SSP_EN is not used on MX6SX anymore */
+	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	/* Clear PCIe PHY reset bit */
+	clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+#else
 	/* Enable PCIe */
 	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
 	imx6_pcie_toggle_reset();

Signature · 1 line

1.9.1

Marek Vasut

2014-08-25 19:50 UTC #2 lore raw

PATCH v3 2/3 pcie_imx: Add mx6solox support

Quoted 10 lines · Fabio Estevam

Let PCI on mx6solox also be supported.
Signed-off-by Fabio Estevam <[email protected]>
---
Changes since v2:
- Configure lvds1_clk_sel in run-time
Changes since v1:
- Put the definition of gpc inside CONFIG_MX6SX ifdef
- Use setbits_le32 to configure register CNTR
- Improve comments in the code

Quoted 6 lines

 arch/arm/cpu/armv7/mx6/clock.c        | 17 +++++++++++----
 arch/arm/include/asm/arch-mx6/iomux.h |  9 ++++++++
 drivers/pci/pcie_imx.c                | 40
+++++++++++++++++++++++++++++++---- 3 files changed, 58 insertions(+), 8 deletions(-)

Acked-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut

Stefano Babic

2014-09-09 15:26 UTC #3 lore raw

PATCH v3 2/3 pcie_imx: Add mx6solox support

In reply to Fabio Estevam

Quoted 4 lines · Fabio Estevam

Let PCI on mx6solox also be supported.
Signed-off-by Fabio Estevam <[email protected]>
---

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Fabio Estevam

author

2014-08-25 17:26 UTC #4 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

In reply to Fabio Estevam

Tested with an Intel Wireless PCI 7260HMW card:

U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz                                      
Reset cause: WDOG                                                               
Board: MX6SX SABRE SDB                                                          
I2C:   ready                                                                    
DRAM:  1 GiB                                                                    
MMC:   FSL_SDHC: 0

00:01.0 - 16c3:abcd - Bridge device
01:00.0 - 8086:08b1 - Network controller

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v2:
- None
Changes since v1:
- None

 include/configs/mx6sxsabresd.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

include/configs/mx6sxsabresd.h +10 -0

index 1eda65e..b92d944 100644
@@ -198,6 +198,16 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 1)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 0)
+#endif
+
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH

Signature · 1 line

1.9.1

Marek Vasut

2014-08-25 19:50 UTC #5 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

Quoted 10 lines · Fabio Estevam

Tested with an Intel Wireless PCI 7260HMW card:
U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0

Quoted 4 lines

00:01.0 - 16c3:abcd - Bridge device
01:00.0 - 8086:08b1 - Network controller
Signed-off-by Fabio Estevam <[email protected]>

Should this output be really part of the commit message?

Best regards,
Marek Vasut

Fabio Estevam

reviewer

2014-08-25 20:11 UTC #6 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

Quoted 14 lines · Marek Vasut

Quoted 13 lines · Fabio Estevam
Tested with an Intel Wireless PCI 7260HMW card:
U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
00:01.0 - 16c3:abcd - Bridge device
01:00.0 - 8086:08b1 - Network controller

Quoted 3 lines

Quoted 1 line
Signed-off-by Fabio Estevam <[email protected]>
Should this output be really part of the commit message?

Personally I don't see any problem with it, but if Stefano prefers I can remove it and send a v4.

Otavio Salvador

2014-08-25 20:24 UTC #7 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

Quoted 15 lines · Fabio Estevam

Quoted 14 lines · Marek Vasut
Quoted 13 lines · Fabio Estevam
Tested with an Intel Wireless PCI 7260HMW card:
U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
00:01.0 - 16c3:abcd - Bridge device
01:00.0 - 8086:08b1 - Network controller

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
Signed-off-by Fabio Estevam <[email protected]>
Should this output be really part of the commit message?
Personally I don't see any problem with it, but if Stefano prefers I can remove it and send a v4.

I like to have it included.

Signature · 3 lines

Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

Marek Vasut

2014-08-25 20:28 UTC #8 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

Quoted 18 lines · Otavio Salvador

Quoted 17 lines · Fabio Estevam
Quoted 16 lines · Marek Vasut
Quoted 15 lines · Fabio Estevam
Tested with an Intel Wireless PCI 7260HMW card:
U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
00:01.0 - 16c3:abcd - Bridge device
   01:00.0    - 8086:08b1 - Network controller

Quoted 8 lines

Quoted 6 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Fabio Estevam <[email protected]>
Should this output be really part of the commit message?
Personally I don't see any problem with it, but if Stefano prefers I can remove it and send a v4.
I like to have it included.

Please explain what exactly is the worth of having 50% of commit message contain standard U-Boot boot output, which is completely unrelated to what the commit implements. The rest of the commit message fails to explain what the commit does.

I would like to hear your reasoning for your claim.

Best regards,
Marek Vasut

Otavio Salvador

2014-08-25 20:31 UTC #9 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

Quoted 26 lines · Marek Vasut

Quoted 25 lines · Otavio Salvador
Quoted 23 lines · Fabio Estevam
Quoted 12 lines · Marek Vasut
Quoted 11 lines · Fabio Estevam
Tested with an Intel Wireless PCI 7260HMW card:
U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
Quoted 7 lines
Quoted 5 lines
00:01.0 - 16c3:abcd - Bridge device
   01:00.0    - 8086:08b1 - Network controller
Signed-off-by Fabio Estevam <[email protected]>
Should this output be really part of the commit message?
Personally I don't see any problem with it, but if Stefano prefers I can remove it and send a v4.

Quoted 8 lines

Quoted 1 line
I like to have it included.
Please explain what exactly is the worth of having 50% of commit message contain standard U-Boot boot output, which is completely unrelated to what the commit implements. The rest of the commit message fails to explain what the commit does.
I would like to hear your reasoning for your claim.

I don't have to explain. I like it there and I think it adds an information which I feel it is valid. You said you does not like it so please explain your reasoning ;-)

Signature · 3 lines

Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

Marek Vasut

2014-08-25 20:47 UTC #10 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

Quoted 29 lines · Otavio Salvador

Quoted 28 lines · Marek Vasut
Quoted 26 lines · Otavio Salvador
Quoted 15 lines · Fabio Estevam
Quoted 14 lines · Marek Vasut
Quoted 13 lines · Fabio Estevam
Tested with an Intel Wireless PCI 7260HMW card:
U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
00:01.0 - 16c3:abcd - Bridge device
Quoted 8 lines
Quoted 5 lines
Quoted 3 lines
   01:00.0    - 8086:08b1 - Network controller
Signed-off-by Fabio Estevam <[email protected]>
Should this output be really part of the commit message?
Personally I don't see any problem with it, but if Stefano prefers I can remove it and send a v4.
I like to have it included.

Quoted 8 lines

Quoted 6 lines
Please explain what exactly is the worth of having 50% of commit message contain standard U-Boot boot output, which is completely unrelated to what the commit implements. The rest of the commit message fails to explain what the commit does.
I would like to hear your reasoning for your claim.
I don't have to explain.

Sorry, but this is in no way how you proceed with a constructive discussion. I will cut the discussion here, since I am starting to see a recurring pattern and I am growing tired of this.

[...]

Best regards,
Marek Vasut

Fabio Estevam

reviewer

2014-08-29 20:19 UTC #11 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

In reply to Fabio Estevam

Hi Stefano,

Quoted 15 lines · Fabio Estevam

Quoted 14 lines · Marek Vasut
Quoted 13 lines · Fabio Estevam
Tested with an Intel Wireless PCI 7260HMW card:
U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
00:01.0 - 16c3:abcd - Bridge device
01:00.0 - 8086:08b1 - Network controller

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
Signed-off-by Fabio Estevam <[email protected]>
Should this output be really part of the commit message?
Personally I don't see any problem with it, but if Stefano prefers I can remove it and send a v4.

Please let me know if you want me to resend this series or if you are fine with it.

Thanks

Marek Vasut

2014-08-29 22:29 UTC #12 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

Quoted 22 lines · Fabio Estevam

Hi Stefano,
Quoted 19 lines · Fabio Estevam
Quoted 18 lines · Marek Vasut
Quoted 16 lines · Fabio Estevam
Tested with an Intel Wireless PCI 7260HMW card:
U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)
CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
00:01.0 - 16c3:abcd - Bridge device
   01:00.0    - 8086:08b1 - Network controller
Signed-off-by Fabio Estevam <[email protected]>

Quoted 7 lines

Quoted 4 lines
Quoted 1 line
Should this output be really part of the commit message?
Personally I don't see any problem with it, but if Stefano prefers I can remove it and send a v4.
Please let me know if you want me to resend this series or if you are fine with it.

A proper commit message describing the change would be very useful. Thank you!

Best regards,
Marek Vasut

Fabio Estevam

reviewer

2014-08-29 22:54 UTC #13 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

Quoted 1 line · Marek Vasut

A proper commit message describing the change would be very useful. Thank you!

Sorry, but I don't understand your suggestion.

The Subject says that I am adding PCI support to the mx6sxsabresd board.

Then I say that I tested it with a PCI card and put the log showing that the card was detected.

I really don't know how I can be clearer in the description of this simple patch.

Marek Vasut

2014-08-30 12:31 UTC #14 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

Quoted 6 lines · Fabio Estevam

Quoted 2 lines · Marek Vasut
A proper commit message describing the change would be very useful. Thank you!
Sorry, but I don't understand your suggestion.

Quoted 7 lines

The Subject says that I am adding PCI support to the mx6sxsabresd board.
Then I say that I tested it with a PCI card and put the log showing that the card was detected.
I really don't know how I can be clearer in the description of this simple patch.

Just one or two lines explaining that you're adding the sabre-sx PCIe support in the commit message would do, really.

Best regards,
Marek Vasut

Stefano Babic

2014-09-09 15:26 UTC #15 lore raw

PATCH v3 3/3 mx6sxsabresd: Add PCI support

In reply to Fabio Estevam

Quoted 10 lines · Fabio Estevam

Tested with an Intel Wireless PCI 7260HMW card:

U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz                                      
Reset cause: WDOG                                                               
Board: MX6SX SABRE SDB                                                          
I2C:   ready                                                                    
DRAM:  1 GiB                                                                    
MMC:   FSL_SDHC: 0

Quoted 5 lines

00:01.0 - 16c3:abcd - Bridge device
01:00.0 - 8086:08b1 - Network controller
Signed-off-by Fabio Estevam <[email protected]>
---

I have no problem with the commit message.

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2014-09-09 15:26 UTC #16 lore raw

PATCH v3 1/3 mx6: imx-regs: Provide a structure for GPC registers

In reply to Fabio Estevam

Quoted 5 lines · Fabio Estevam

Introduce a structure for accessing the General Power Controller block (GPC) registers.
Signed-off-by Fabio Estevam <[email protected]>
---

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================