net: fec_mxc: Adjust RX DMA alignment for mx6solox

PATCH New Fabio Estevam 5 participants 11 messages Aug 25, 2014 – Sep 9, 2014 Network drivers

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Fabio Estevam

author

2014-08-25 16:34 UTC #0 lore raw

PATCH v7 1/2 net: fec_mxc: Adjust RX DMA alignment for mx6solox

mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.

Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v6:
- Only use FEC_DMA_RX_MINALIGN for the RX buffers
Changes since v5:
- Add Stefan's Ack
Changes since v4:
- None

Signed-off-by Fabio Estevam <[email protected]>

---
 drivers/net/fec_mxc.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

drivers/net/fec_mxc.c +10 -2

index 4cefda4..d310016 100644
@@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define FEC_XFER_TIMEOUT	5000
 
+/*
+ * The standard 32-byte DMA alignment does not work on mx6solox, which requires
+ * 64-byte alignment in the DMA RX FEC buffer.
+ * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
+ * satisfies the alignment on other SoCs (32-bytes)
+ */
+#define FEC_DMA_RX_MINALIGN	64
+
 #ifndef CONFIG_MII
 #error "CONFIG_MII has to be defined!"
 #endif

@@ -881,9 +889,9 @@ static int fec_alloc_descs(struct fec_priv *fec)
 	/* Allocate RX buffers. */
 
 	/* Maximum RX buffer size. */
-	size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
+	size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
 	for (i = 0; i < FEC_RBD_NUM; i++) {
-		data = memalign(ARCH_DMA_MINALIGN, size);
+		data = memalign(FEC_DMA_RX_MINALIGN, size);
 		if (!data) {
 			printf("%s: error allocating rxbuf %d\n", __func__, i);
 			goto err_ring;

Signature · 1 line

1.9.1

Fabio Estevam

author

2014-08-25 16:34 UTC #1 lore raw

PATCH v7 2/2 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail.

As explained by Ye Li:

"The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version."

Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs.

No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v6:
- Fix checkpatch complaint about >80 colummn
Changes since v5:
- Put explanation why we need to poll READY bit after TDAR into the code

 drivers/net/fec_mxc.c | 30 +++++++++++++++++++++++++++---
 1 file changed, 27 insertions(+), 3 deletions(-)

drivers/net/fec_mxc.c +27 -3

index d310016..549d648 100644
@@ -719,13 +719,37 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 			break;
 	}
 
-	if (!timeout)
+	if (!timeout) {
 		ret = -EINVAL;
+		goto out;
+	}
 
-	invalidate_dcache_range(addr, addr + size);
-	if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
+	/*
+	 * The TDAR bit is cleared when the descriptors are all out from TX
+	 * but on mx6solox we noticed that the READY bit is still not cleared
+	 * right after TDAR.
+	 * These are two distinct signals, and in IC simulation, we found that
+	 * TDAR always gets cleared prior than the READY bit of last BD becomes
+	 * cleared.
+	 * In mx6solox, we use a later version of FEC IP. It looks like that
+	 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
+	 * version.
+	 *
+	 * Fix this by polling the READY bit of BD after the TDAR polling,
+	 * which covers the mx6solox case and does not harm the other SoCs.
+	 */
+	timeout = FEC_XFER_TIMEOUT;
+	while (--timeout) {
+		invalidate_dcache_range(addr, addr + size);
+		if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
+		    FEC_TBD_READY))
+			break;
+	}
+
+	if (!timeout)
 		ret = -EINVAL;
 
+out:
 	debug("fec_send: status 0x%x index %d ret %i\n",
 			readw(&fec->tbd_base[fec->tbd_index].status),
 			fec->tbd_index, ret);

Signature · 1 line

1.9.1

Marek Vasut

2014-08-25 19:51 UTC #2 lore raw

PATCH v7 2/2 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

Quoted 14 lines · Fabio Estevam

When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail.
As explained by Ye Li:
"The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared.
In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version."

Quoted 7 lines

Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs.
No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs.
Signed-off-by Fabio Estevam <[email protected]>

Acked-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut

Stefano Babic

2014-09-09 13:10 UTC #3 lore raw

PATCH v7 2/2 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

In reply to Fabio Estevam

Quoted 13 lines · Fabio Estevam

When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail.
As explained by Ye Li:
"The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version."

Quoted 8 lines

Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs.
No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs.
Signed-off-by Fabio Estevam <[email protected]>
---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Marek Vasut

2014-08-25 19:51 UTC #4 lore raw

PATCH v7 1/2 net: fec_mxc: Adjust RX DMA alignment for mx6solox

In reply to Fabio Estevam

Quoted 7 lines · Fabio Estevam

mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by Fabio Estevam <[email protected]>

Acked-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut

Fabio Estevam

2014-08-30 17:22 UTC #5 lore raw

PATCH v7 1/2 net: fec_mxc: Adjust RX DMA alignment for mx6solox

Tom, Joe or Stefano,

Quoted 10 lines · Marek Vasut

Quoted 7 lines · Fabio Estevam
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by Fabio Estevam <[email protected]>
Acked-by Marek Vasut <[email protected]>

Could this one be applied for 2014.10-rc?

Thanks

Tom Rini

2014-08-30 19:21 UTC #6 lore raw

PATCH v7 1/2 net: fec_mxc: Adjust RX DMA alignment for mx6solox

Quoted 7 lines · Fabio Estevam

Tom, Joe or Stefano,
Quoted 4 lines · Marek Vasut
Quoted 3 lines · Fabio Estevam
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.

Quoted 8 lines

Quoted 6 lines
Quoted 4 lines
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by Fabio Estevam <[email protected]>
Acked-by Marek Vasut <[email protected]>
Could this one be applied for 2014.10-rc?

I'd like this via the imx tree.

Signature · 8 lines

Tom
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Fabio Estevam

2014-09-08 23:52 UTC #7 lore raw

PATCH v7 1/2 net: fec_mxc: Adjust RX DMA alignment for mx6solox

Hi Tom,

Quoted 11 lines · Tom Rini

Quoted 10 lines · Fabio Estevam
Tom, Joe or Stefano,
Quoted 7 lines · Marek Vasut
Quoted 6 lines · Fabio Estevam
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.

Quoted 7 lines

Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Fabio Estevam <[email protected]>
Acked-by Marek Vasut <[email protected]>
Could this one be applied for 2014.10-rc?
I'd like this via the imx tree.

Unfortunately, I am not getting any response from Stefano for quite some time.

Can you apply this series as we are already in rc2 now?

Stefano Babic

2014-09-09 13:09 UTC #8 lore raw

PATCH v7 1/2 net: fec_mxc: Adjust RX DMA alignment for mx6solox

Hi Fabio,

Quoted 16 lines · Fabio Estevam

Hi Tom,
Quoted 13 lines · Tom Rini
Quoted 12 lines · Fabio Estevam
Tom, Joe or Stefano,
Quoted 9 lines · Marek Vasut
Quoted 7 lines · Fabio Estevam
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by Fabio Estevam <[email protected]>

Quoted 8 lines

Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Acked-by Marek Vasut <[email protected]>
Could this one be applied for 2014.10-rc?
I'd like this via the imx tree.
Unfortunately, I am not getting any response from Stefano for quite some time.

Sorry, I was not in office in last two weeks.

Quoted 1 line

Can you apply this series as we are already in rc2 now?

Applied to u-boot-imx, thanks !

Fabio, I will try to dig in all patches that queue in last two weeks. If you can, please take a look next week what is still missing and send me a remind - thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Fabio Estevam

2014-09-09 13:37 UTC #9 lore raw

PATCH v7 1/2 net: fec_mxc: Adjust RX DMA alignment for mx6solox

Hi Stefano,

Quoted 3 lines · Stefano Babic

Fabio, I will try to dig in all patches that queue in last two weeks. If you can, please take a look next week what is still missing and send me a remind - thanks !

Excellent, thanks!

Fabio Estevam

2014-09-03 22:21 UTC #10 lore raw

PATCH v7 1/2 net: fec_mxc: Adjust RX DMA alignment for mx6solox

In reply to Fabio Estevam

Hi Stefano,

Quoted 7 lines · Fabio Estevam

mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by Fabio Estevam <[email protected]>

Could we have this series applied for 2014.10-rc ?