Skip to contentSkip to conversation

of: Add NVIDIA Tegra Legacy Interrupt Controller binding

PATCH Superseded Thierry Reding 2 participants 7 messages Aug 26, 2014 – Aug 27, 2014

Subsystems (5)
Device tree bindings Arm (32-bit) Arm sub-architectures Tegra architecture support +1 more subsystems

v3 of 4 Superseded Latest is v4 →

lore
Share & tools
lore

Thierry Reding

author
#0 lore raw

PATCH v3 1/5 of: Add NVIDIA Tegra Legacy Interrupt Controller binding

From: Thierry Reding <[email protected]>

The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by the AVP coprocessor and can also serve as a backup for the ARM Cortex CPU's local interrupt controller (GIC).

The LIC is subdivided into multiple identical units, each handling 32 possible interrupt sources.

Signed-off-by Thierry Reding <[email protected]>

---
Changes in v3:
- bracket individual tuples in the "reg" property

 .../interrupt-controller/nvidia,tegra20-ictlr.txt     | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt new file +19 -0
new file mode 100644
index 000000000000..1639389b7360
@@ -0,0 +1,19 @@
+NVIDIA Tegra Legacy Interrupt Controller
+
+The legacy interrupt controller is divided into units that serve 32 interrupts
+each. Tegra20 implements four units, whereas Tegra30 and later implement five.
+
+Required properties:
+- compatible: "nvidia,tegra<chip>-ictlr"
+- reg: Physical base address and length of the controller's registers. There
+  should be one entry for each unit.
+
+Example:
+
+	interrupt-controller at 60004000 {
+		compatible = "nvidia,tegra20-ictlr";
+		reg = <0x60004000 0x40>, /* primary controller */
+		      <0x60004100 0x40>, /* secondary controller */
+		      <0x60004200 0x40>, /* tertiary controller */
+		      <0x60004300 0x40>; /* quaternary controller */
+	};
Signature · 1 line
2.0.4
author
#1 lore raw

PATCH v3 2/5 ARM: tegra: Add legacy interrupt controller nodes

From: Thierry Reding <[email protected]>

Add device tree nodes for the legacy interrupt controller so that the driver can get the register ranges from device tree rather than hard- coding them.

Signed-off-by Thierry Reding <[email protected]>

---
Changes in v3:
- bracket individual tuples in the "reg" property

Changes in v2:
- add chip-specific compatible string
- drop quinary controller on Tegra20

 arch/arm/boot/dts/tegra114.dtsi | 9 +++++++++
 arch/arm/boot/dts/tegra124.dtsi | 9 +++++++++
 arch/arm/boot/dts/tegra20.dtsi  | 8 ++++++++
 arch/arm/boot/dts/tegra30.dtsi  | 9 +++++++++
 4 files changed, 35 insertions(+)
arch/arm/boot/dts/tegra114.dtsi +9 -0
index a147fa2bfdd2..9bfab8bb765a 100644
@@ -141,6 +141,15 @@
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	interrupt-controller at 60004000 {
+		compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
+		reg = <0x60004000 0x40>, /* primary controller */
+		      <0x60004100 0x40>, /* secondary controller */
+		      <0x60004200 0x40>, /* tertiary controller */
+		      <0x60004300 0x40>, /* quaternary controller */
+		      <0x60004400 0x40>; /* quinary controller */
+	};
+
 	timer at 60005000 {
 		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;
arch/arm/boot/dts/tegra124.dtsi +9 -0
index e8432da81985..d4f284b30195 100644
@@ -190,6 +190,15 @@
 		status = "disabled";
 	};
 
+	interrupt-controller at 0,60004000 {
+		compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
+		reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
+		      <0x0 0x60004100 0x0 0x40>, /* secondary controller */
+		      <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
+		      <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
+		      <0x0 0x60004400 0x0 0x40>; /* quinary controller */
+	};
+
 	timer at 0,60005000 {
 		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 		reg = <0x0 0x60005000 0x0 0x400>;
arch/arm/boot/dts/tegra20.dtsi +8 -0
index c6a2d078bdf4..fe2f57d19438 100644
@@ -183,6 +183,14 @@
 		cache-level = <2>;
 	};
 
+	interrupt-controller at 60004000 {
+		compatible = "nvidia,tegra20-ictlr";
+		reg = <0x60004000 0x40>, /* primary controller */
+		      <0x60004100 0x40>, /* secondary controller */
+		      <0x60004200 0x40>, /* tertiary controller */
+		      <0x60004300 0x40>; /* quaternary controller */
+	};
+
 	timer at 60005000 {
 		compatible = "nvidia,tegra20-timer";
 		reg = <0x60005000 0x60>;
arch/arm/boot/dts/tegra30.dtsi +9 -0
index f4693c9c070e..e5da2d252220 100644
@@ -262,6 +262,15 @@
 		cache-level = <2>;
 	};
 
+	interrupt-controller at 60004000 {
+		compatible = "nvidia,tegra30-ictlr";
+		reg = <0x60004000 0x40>, /* primary controller */
+		      <0x60004100 0x40>, /* secondary controller */
+		      <0x60004200 0x40>, /* tertiary controller */
+		      <0x60004300 0x40>, /* quaternary controller */
+		      <0x60004400 0x40>; /* quinary controller */
+	};
+
 	timer at 60005000 {
 		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;
Signature · 1 line
2.0.4
author
#2 lore raw

PATCH v3 3/5 ARM: tegra: Initialize interrupt controller from DT

In reply to Thierry Reding

From: Thierry Reding <[email protected]>

Obtains the register ranges for the legacy interrupt controller from DT and provide hard-coded values as fallback.

Signed-off-by Thierry Reding <[email protected]>

---
Changes in v4:
- cleanup warning messages

Changes in v3:
- fixup subject prefix

Changes in v2:
- check for the exact number of controllers expected
- fallback to tegra_chip_id for non-DT
- warn on parsing errors

 arch/arm/mach-tegra/iomap.h |  18 -------
 arch/arm/mach-tegra/irq.c   | 122 ++++++++++++++++++++++++++++++++++++--------
 2 files changed, 101 insertions(+), 39 deletions(-)
arch/arm/mach-tegra/iomap.h +0 -18
index ee79808e93a3..52bbb5c8fe84 100644
@@ -28,24 +28,6 @@
 #define TEGRA_ARM_PERIF_BASE		0x50040000
 #define TEGRA_ARM_PERIF_SIZE		SZ_8K
 
-#define TEGRA_ARM_INT_DIST_BASE		0x50041000
-#define TEGRA_ARM_INT_DIST_SIZE		SZ_4K
-
-#define TEGRA_PRIMARY_ICTLR_BASE	0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE	SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE	0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE	SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE	0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE	SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE	0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZE	SZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE	0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE	SZ_64
-
 #define TEGRA_TMR1_BASE			0x60005000
 #define TEGRA_TMR1_SIZE			SZ_8
arch/arm/mach-tegra/irq.c +101 -21

165 lines not on this page · raw message

Signature · 1 line
2.0.4
author
#3 lore raw

PATCH v3 4/5 ARM: tegra: Remove unused GIC initialization

In reply to Thierry Reding

From: Thierry Reding <[email protected]>

Tegra has been booting from DT exclusively for quite some time, so this old code setting up the GIC for non-DT boot is unused and can therefore be removed.

Signed-off-by Thierry Reding <[email protected]>
---
 arch/arm/mach-tegra/irq.c | 9 ---------
 1 file changed, 9 deletions(-)
arch/arm/mach-tegra/irq.c +0 -9
index b2e2e6dbe52d..39a3358877e0 100644
@@ -362,14 +362,5 @@ void __init tegra_init_irq(void)
 	gic_arch_extn.irq_set_wake = tegra_set_wake;
 	gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
-	/*
-	 * Check if there is a devicetree present, since the GIC will be
-	 * initialized elsewhere under DT.
-	 */
-	if (!of_have_populated_dt()) {
-		void __iomem *cpubase = ioremap_nocache(0x50040000, 0x2000);
-		gic_init(0, 29, distbase, cpubase);
-	}
-
 	tegra114_gic_cpu_pm_registration();
 }
Signature · 1 line
2.0.4
author
#4 lore raw

PATCH v3 5/5 ARM: tegra: Remove unused defines

In reply to Thierry Reding

From: Thierry Reding <[email protected]>

Eventually the aim is to get rid of this file because it cannot be built on ARM64. Until it can be completely removed, eliminate unused entries to make it easier to see which are still used.

Reviewed-by Stephen Warren <[email protected]>
Signed-off-by Thierry Reding <[email protected]>

---
Changes in v3:
- fixup subject prefix

 arch/arm/mach-tegra/iomap.h | 30 ------------------------------
 1 file changed, 30 deletions(-)
arch/arm/mach-tegra/iomap.h +0 -30
index 52bbb5c8fe84..c2fd86a9b43f 100644
@@ -28,21 +28,9 @@
 #define TEGRA_ARM_PERIF_BASE		0x50040000
 #define TEGRA_ARM_PERIF_SIZE		SZ_8K
 
-#define TEGRA_TMR1_BASE			0x60005000
-#define TEGRA_TMR1_SIZE			SZ_8
-
-#define TEGRA_TMR2_BASE			0x60005008
-#define TEGRA_TMR2_SIZE			SZ_8
-
 #define TEGRA_TMRUS_BASE		0x60005010
 #define TEGRA_TMRUS_SIZE		SZ_64
 
-#define TEGRA_TMR3_BASE			0x60005050
-#define TEGRA_TMR3_SIZE			SZ_8
-
-#define TEGRA_TMR4_BASE			0x60005058
-#define TEGRA_TMR4_SIZE			SZ_8
-
 #define TEGRA_CLK_RESET_BASE		0x60006000
 #define TEGRA_CLK_RESET_SIZE		SZ_4K
 

@@ -58,21 +46,6 @@
 #define TEGRA_APB_MISC_BASE		0x70000000
 #define TEGRA_APB_MISC_SIZE		SZ_4K
 
-#define TEGRA_UARTA_BASE		0x70006000
-#define TEGRA_UARTA_SIZE		SZ_64
-
-#define TEGRA_UARTB_BASE		0x70006040
-#define TEGRA_UARTB_SIZE		SZ_64
-
-#define TEGRA_UARTC_BASE		0x70006200
-#define TEGRA_UARTC_SIZE		SZ_256
-
-#define TEGRA_UARTD_BASE		0x70006300
-#define TEGRA_UARTD_SIZE		SZ_256
-
-#define TEGRA_UARTE_BASE		0x70006400
-#define TEGRA_UARTE_SIZE		SZ_256
-
 #define TEGRA_PMC_BASE			0x7000E400
 #define TEGRA_PMC_SIZE			SZ_256
 

@@ -91,9 +64,6 @@
 #define TEGRA124_EMC_BASE		0x7001B000
 #define TEGRA124_EMC_SIZE		SZ_2K
 
-#define TEGRA_CSITE_BASE		0x70040000
-#define TEGRA_CSITE_SIZE		SZ_256K
-
 /* On TEGRA, many peripherals are very closely packed in
  * two 256MB io windows (that actually only use about 64KB
  * at the start of each).
Signature · 1 line
2.0.4
#5 lore raw

PATCH v3 1/5 of: Add NVIDIA Tegra Legacy Interrupt Controller binding

In reply to Thierry Reding
Quoted 8 lines · Thierry Reding

From: Thierry Reding <[email protected]>

The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by the AVP coprocessor and can also serve as a backup for the ARM Cortex CPU's local interrupt controller (GIC).

The LIC is subdivided into multiple identical units, each handling 32 possible interrupt sources.

If I apply this series without patch 2, which is necessary to test the support for compatibility with old DTs, then I get the following very early on in boot:

Other than that, I would apply this.

Quoted 33 lines
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: CPU: 0 PID: 0 at drivers/soc/tegra/fuse/tegra-apbmisc.c:42 tegra_get_chip_id+0x30/0x44()
[    0.000000] Tegra Chip ID not yet available
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc2-00016-g6a550998848e #32
[    0.000000] [<c00157a0>] (unwind_backtrace) from [<c0011344>] (show_stack+0x10/0x14)
[    0.000000] [<c0011344>] (show_stack) from [<c06045e8>] (dump_stack+0x84/0xd0)
[    0.000000] [<c06045e8>] (dump_stack) from [<c0024f44>] (warn_slowpath_common+0x64/0x88)
[    0.000000] [<c0024f44>] (warn_slowpath_common) from [<c0024ffc>] (warn_slowpath_fmt+0x30/0x40)
[    0.000000] [<c0024ffc>] (warn_slowpath_fmt) from [<c0267acc>] (tegra_get_chip_id+0x30/0x44)
[    0.000000] [<c0267acc>] (tegra_get_chip_id) from [<c08576a8>] (tegra_init_irq+0xb0/0x2d0)
[    0.000000] [<c08576a8>] (tegra_init_irq) from [<c0857d60>] (tegra_dt_init_irq+0x8/0x14)
[    0.000000] [<c0857d60>] (tegra_dt_init_irq) from [<c08525a8>] (init_IRQ+0x28/0x7c)
[    0.000000] [<c08525a8>] (init_IRQ) from [<c0850a48>] (start_kernel+0x21c/0x3a8)
[    0.000000] [<c0850a48>] (start_kernel) from [<80008074>] (0x80008074)
[    0.000000] ---[ end trace cb88537fdc8fa200 ]---
[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: CPU: 0 PID: 0 at arch/arm/mach-tegra/irq.c:343 tegra_init_irq+0x184/0x2d0()
[    0.000000] Found 5 interrupt controllers; expected 4.
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W      3.17.0-rc2-00016-g6a550998848e #32
[    0.000000] [<c00157a0>] (unwind_backtrace) from [<c0011344>] (show_stack+0x10/0x14)
[    0.000000] [<c0011344>] (show_stack) from [<c06045e8>] (dump_stack+0x84/0xd0)
[    0.000000] [<c06045e8>] (dump_stack) from [<c0024f44>] (warn_slowpath_common+0x64/0x88)
[    0.000000] [<c0024f44>] (warn_slowpath_common) from [<c0024ffc>] (warn_slowpath_fmt+0x30/0x40)
[    0.000000] [<c0024ffc>] (warn_slowpath_fmt) from [<c085777c>] (tegra_init_irq+0x184/0x2d0)
[    0.000000] [<c085777c>] (tegra_init_irq) from [<c0857d60>] (tegra_dt_init_irq+0x8/0x14)
[    0.000000] [<c0857d60>] (tegra_dt_init_irq) from [<c08525a8>] (init_IRQ+0x28/0x7c)
[    0.000000] [<c08525a8>] (init_IRQ) from [<c0850a48>] (start_kernel+0x21c/0x3a8)
[    0.000000] [<c0850a48>] (start_kernel) from [<80008074>] (0x80008074)
[    0.000000] ---[ end trace cb88537fdc8fa201 ]---
author
#6 lore raw

PATCH v3 1/5 of: Add NVIDIA Tegra Legacy Interrupt Controller binding

Quoted 7 lines · Stephen Warren
Quoted 6 lines · Thierry Reding

From: Thierry Reding <[email protected]>

The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by the AVP coprocessor and can also serve as a backup for the ARM Cortex CPU's local interrupt controller (GIC).

Quoted 8 lines
Quoted 2 lines

The LIC is subdivided into multiple identical units, each handling 32 possible interrupt sources.

If I apply this series without patch 2, which is necessary to test the support for compatibility with old DTs, then I get the following very early on in boot:

Other than that, I would apply this.

Ugh... this is because before patch 3 the code would always initialize all five controllers, even on Tegra20 where it doesn't exist. Patch 3 adds a check for that based on the chip ID, which due to other patches merged for v3.17 isn't available at this point. One solution would be for this to be moved into an initcall to make sure it's called after initialization of the fuse driver so that tegra_get_chip_id() can read the chip ID. But since you're not at all a fan of that I guess the best we can do is to match on the top-level machine compatible instead of using the chip ID.

Thierry
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140827/82920ae3/attachment.sig>