clk: sunxi: Improve MMC clocks support

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 17 ++++++++++++++---
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 19 insertions(+), 3 deletions(-)

drivers/clk/clk.c +2 -2

index d87661af0c72..7dbceca694f1 100644
@@ -1797,8 +1797,8 @@ out:
  * clk_get_phase - return the phase shift of a clock signal
  * @clk: clock signal source
  *
- * Returns the phase shift of a clock node in degrees, otherwise returns
- * -EERROR.
+ * Returns the phase shift of a clock node in degrees. Any negative
+ * values are errors.
  */
 int clk_get_phase(struct clk *clk)
 {

drivers/clk/clk.c +7 -0

+
+	if (!clk->ops->get_phase)
+		goto out_unlock;
+
+	ret = clk->ops->get_phase(clk->hw);
+
+out_unlock:
 	clk_prepare_unlock();
 
 out:

include/linux/clk-provider.h +5 -0

index 69b20d4c1e1a..abec961092a7 100644
@@ -130,6 +130,10 @@ struct dentry;
  *		set then clock accuracy will be initialized to parent accuracy
  *		or 0 (perfect clock) if clock has no parent.
  *
+ * @get_phase:	Queries the hardware to get the current phase of a clock.
+ *		Returned values are 0-359 degrees on success, negative
+ *		error codes on failure.
+ *
  * @set_phase:	Shift the phase this clock signal in degrees specified
  *		by the second argument. Valid values for degrees are
  *		0-359. Return 0 on success, otherwise -EERROR.

@@ -182,6 +186,7 @@ struct clk_ops {
 				    unsigned long parent_rate, u8 index);
 	unsigned long	(*recalc_accuracy)(struct clk_hw *hw,
 					   unsigned long parent_accuracy);
+	int		(*get_phase)(struct clk_hw *hw);
 	int		(*set_phase)(struct clk_hw *hw, int degrees);
 	void		(*init)(struct clk_hw *hw);
 	int		(*debug_init)(struct clk_hw *hw, struct dentry *dentry);

Hi,

Quoted 34 lines · Maxime Ripard

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 17 ++++++++++++++---
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 19 insertions(+), 3 deletions(-)

drivers/clk/clk.c +2 -2

index d87661af0c72..7dbceca694f1 100644
@@ -1797,8 +1797,8 @@ out:
  * clk_get_phase - return the phase shift of a clock signal
  * @clk: clock signal source
  *
- * Returns the phase shift of a clock node in degrees, otherwise returns
- * -EERROR.
+ * Returns the phase shift of a clock node in degrees. Any negative
+ * values are errors.
  */
 int clk_get_phase(struct clk *clk)
 {

drivers/clk/clk.c int clk_get_phase(struct clk *clk) · line 1815

Quoted 9 lines

drivers/clk/clk.c +5 -1

@@ -1808,7 +1808,18 @@ int clk_get_phase(struct clk *clk)
 		goto out;
 
 	clk_prepare_lock();
-	ret = clk->phase;
+
+	if (clk->phase) {
+		ret = clk->phase;
+		goto out_unlock;
+	}

0 is a valid phase, so this will cause the phase to be read from the hardware each time if the phase is 0.

Perhaps make clk->phase signed (if it is not already), init it to -1, and check for it not being -1 ?

Hi,

Quoted 50 lines · Hans de Goede

Hi,

Quoted 34 lines · Maxime Ripard

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 17 ++++++++++++++---
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 19 insertions(+), 3 deletions(-)

drivers/clk/clk.c +2 -2

index d87661af0c72..7dbceca694f1 100644
@@ -1797,8 +1797,8 @@ out:
  * clk_get_phase - return the phase shift of a clock signal
  * @clk: clock signal source
  *
- * Returns the phase shift of a clock node in degrees, otherwise returns
- * -EERROR.
+ * Returns the phase shift of a clock node in degrees. Any negative
+ * values are errors.
  */
 int clk_get_phase(struct clk *clk)
 {

drivers/clk/clk.c int clk_get_phase(struct clk *clk) · line 1815

Quoted 9 lines

drivers/clk/clk.c +5 -1

@@ -1808,7 +1808,18 @@ int clk_get_phase(struct clk *clk)
 		goto out;
 
 	clk_prepare_lock();
-	ret = clk->phase;
+
+	if (clk->phase) {
+		ret = clk->phase;
+		goto out_unlock;
+	}

0 is a valid phase, so this will cause the phase to be read from the hardware each time if the phase is 0.

Quoted 2 lines

Perhaps make clk->phase signed (if it is not already), init it to -1, and check for it not being -1 ?

Yeah, I'm not really proud of this code either, but yours would expose this -1 into debugfs, so I'm not sure it's really better :)

(with -1 being a valid phase too)

Hi,

Quoted 56 lines · Maxime Ripard

Hi,

Quoted 52 lines · Hans de Goede

Hi,

Quoted 34 lines · Maxime Ripard

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 17 ++++++++++++++---
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 19 insertions(+), 3 deletions(-)

drivers/clk/clk.c +2 -2

index d87661af0c72..7dbceca694f1 100644
@@ -1797,8 +1797,8 @@ out:
  * clk_get_phase - return the phase shift of a clock signal
  * @clk: clock signal source
  *
- * Returns the phase shift of a clock node in degrees, otherwise returns
- * -EERROR.
+ * Returns the phase shift of a clock node in degrees. Any negative
+ * values are errors.
  */
 int clk_get_phase(struct clk *clk)
 {

drivers/clk/clk.c int clk_get_phase(struct clk *clk) · line 1815

Quoted 9 lines

drivers/clk/clk.c +5 -1

@@ -1808,7 +1808,18 @@ int clk_get_phase(struct clk *clk)
 		goto out;
 
 	clk_prepare_lock();
-	ret = clk->phase;
+
+	if (clk->phase) {
+		ret = clk->phase;
+		goto out_unlock;
+	}

0 is a valid phase, so this will cause the phase to be read from the hardware each time if the phase is 0.

Perhaps make clk->phase signed (if it is not already), init it to -1, and check for it not being -1 ?

Quoted 4 lines

Yeah, I'm not really proud of this code either, but yours would expose this -1 into debugfs, so I'm not sure it's really better :)

(with -1 being a valid phase too)

According to the comments in the patch adding the original phase functions valid values are 0 - 359. And you could use clk_get_phase from the debugfs code.

Yep, except that if I see a value -1 as a phase, I would assume that it's 359, but maybe it's just me :)

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 17 ++++++++++++++---
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 19 insertions(+), 3 deletions(-)

drivers/clk/clk.c +2 -2

index d87661af0c72..7dbceca694f1 100644
@@ -1797,8 +1797,8 @@ out:
  * clk_get_phase - return the phase shift of a clock signal
  * @clk: clock signal source
  *
- * Returns the phase shift of a clock node in degrees, otherwise returns
- * -EERROR.
+ * Returns the phase shift of a clock node in degrees. Any negative
+ * values are errors.
  */
 int clk_get_phase(struct clk *clk)
 {

drivers/clk/clk.c +10 -0

+               ret = clk->phase;
+               goto out_unlock;
+       }
+
+       if (!clk->ops->get_phase)
+               goto out_unlock;
+
+       ret = clk->ops->get_phase(clk->hw);
+
+out_unlock:
        clk_prepare_unlock();
 
 out:

include/linux/clk-provider.h +5 -0

index 69b20d4c1e1a..abec961092a7 100644
@@ -130,6 +130,10 @@ struct dentry;
  *             set then clock accuracy will be initialized to parent accuracy
  *             or 0 (perfect clock) if clock has no parent.
  *
+ * @get_phase: Queries the hardware to get the current phase of a clock.
+ *             Returned values are 0-359 degrees on success, negative
+ *             error codes on failure.
+ *
  * @set_phase: Shift the phase this clock signal in degrees specified
  *             by the second argument. Valid values for degrees are
  *             0-359. Return 0 on success, otherwise -EERROR.

@@ -182,6 +186,7 @@ struct clk_ops {
                                    unsigned long parent_rate, u8 index);
        unsigned long   (*recalc_accuracy)(struct clk_hw *hw,
                                           unsigned long parent_accuracy);
+       int             (*get_phase)(struct clk_hw *hw);
        int             (*set_phase)(struct clk_hw *hw, int degrees);
        void            (*init)(struct clk_hw *hw);
        int             (*debug_init)(struct clk_hw *hw, struct dentry *dentry);

Signature · 1 line

2.0.2

Quoting Maxime Ripard (2014-08-30 13:03:02)

Quoted 36 lines

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 17 ++++++++++++++---
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 19 insertions(+), 3 deletions(-)

drivers/clk/clk.c +2 -2

index d87661af0c72..7dbceca694f1 100644
@@ -1797,8 +1797,8 @@ out:
  * clk_get_phase - return the phase shift of a clock signal
  * @clk: clock signal source
  *
- * Returns the phase shift of a clock node in degrees, otherwise returns
- * -EERROR.
+ * Returns the phase shift of a clock node in degrees. Any negative
+ * values are errors.
  */
 int clk_get_phase(struct clk *clk)
 {

@@ -1808,7 +1808,18 @@ int clk_get_phase(struct clk *clk)
                goto out;
 

drivers/clk/clk.c int clk_get_phase(struct clk *clk) · line 1812

Quoted 4 lines

drivers/clk/clk.c +2 -1

        clk_prepare_lock();
-       ret = clk->phase;
+
+       if (clk->phase) {

So if a phase is zero, then we fall through and query the hardware? Seems like this case might be hit a lot for clocks that implement .get_phase but never have their phase shifted, and accesses to the registers may be much slower than to memory.

Do you expect the phase to be changed behind our backs? E.g. firmware changes it, or coming in and out of idle state, etc. If not then we can store the phase at clock registration time and use a cached value.

See how the CLK_GET_RATE_NOCACHE and CLK_GET_ACCURACY_NOCACHE flags are used for details on how we can handle the case where the phase might change behind our back.

Add the sample and output clocks for the MMC phase support.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun4i-a10.dtsi  | 104 +++++++++++++++++++++++++++++++++++---
 arch/arm/boot/dts/sun5i-a10s.dtsi |  79 ++++++++++++++++++++++++++---
 arch/arm/boot/dts/sun5i-a13.dtsi  |  80 +++++++++++++++++++++++++----
 arch/arm/boot/dts/sun6i-a31.dtsi  | 104 +++++++++++++++++++++++++++++++++++---
 arch/arm/boot/dts/sun7i-a20.dtsi  | 104 +++++++++++++++++++++++++++++++++++---
 5 files changed, 430 insertions(+), 41 deletions(-)

arch/arm/boot/dts/sun4i-a10.dtsi +0 -0

index 380f914b226d..3183436528e1 100644

arch/arm/boot/dts/sun4i-a10.dtsi +95 -8

+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: clk_mmc_sample at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
                mmc1_clk: clk at 01c2008c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -235,6 +251,22 @@
                        clock-output-names = "mmc1";
                };
 
+               mmc1_output_clk: clk_mmc_output at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: clk_mmc_sample at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
                mmc2_clk: clk at 01c20090 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -243,6 +275,22 @@
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: clk_mmc_output at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: clk_mmc_sample at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                mmc3_clk: clk at 01c20094 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -251,6 +299,22 @@
                        clock-output-names = "mmc3";
                };
 
+               mmc3_output_clk: clk_mmc_output at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_output";
+               };
+
+               mmc3_sample_clk: clk_mmc_sample at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_sample";
+               };
+
                ts_clk: clk at 01c20098 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -392,8 +456,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <32>;
                        status = "disabled";
                };

@@ -401,8 +471,14 @@
                mmc1: mmc at 01c10000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb_gates 9>, <&mmc1_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 9>,
+                                <&mmc1_clk>,
+                                <&mmc1_sample_clk>,
+                                <&mmc1_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <33>;
                        status = "disabled";
                };

@@ -410,8 +486,14 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <34>;
                        status = "disabled";
                };

@@ -419,8 +501,14 @@
                mmc3: mmc at 01c12000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c12000 0x1000>;
-                       clocks = <&ahb_gates 11>, <&mmc3_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 11>,
+                                <&mmc3_clk>,
+                                <&mmc3_sample_clk>,
+                                <&mmc3_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <35>;
                        status = "disabled";
                };

arch/arm/boot/dts/sun5i-a10s.dtsi +72 -7

index 531272c0e526..4f5eb763e05a 100644
@@ -212,6 +212,22 @@
                        clock-output-names = "mmc0";
                };
 
+               mmc0_output_clk: clk_mmc_output at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: clk_mmc_sample at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
                mmc1_clk: clk at 01c2008c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -220,6 +236,22 @@
                        clock-output-names = "mmc1";
                };
 
+               mmc1_output_clk: clk_mmc_output at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: clk_mmc_sample at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
                mmc2_clk: clk at 01c20090 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -228,6 +260,22 @@
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: clk_mmc_output at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: clk_mmc_sample at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                ts_clk: clk at 01c20098 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -353,8 +401,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <32>;
                        status = "disabled";
                };

@@ -362,8 +416,14 @@
                mmc1: mmc at 01c10000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb_gates 9>, <&mmc1_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 9>,
+                                <&mmc1_clk>,
+                                <&mmc1_sample_clk>,
+                                <&mmc1_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <33>;
                        status = "disabled";
                };

@@ -371,12 +431,17 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <34>;
                        status = "disabled";
                };
-
                usbphy: phy at 01c13400 {
                        #phy-cells = <1>;
                        compatible = "allwinner,sun5i-a13-usb-phy";

arch/arm/boot/dts/sun5i-a13.dtsi +70 -10

index b131068f4f35..73f99ff6ac6f 100644
@@ -202,30 +202,78 @@
                        clock-output-names = "ms";
                };
 
-               mmc0_clk: clk at 01c20088 {
+               mmc0_clk: clk_mmc at 01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mmc-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
                };
 
-               mmc1_clk: clk at 01c2008c {
+               mmc0_output_clk: clk_mmc_output at 01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: clk_mmc_sample at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
+               mmc1_clk: clk_mmc at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
                };
 
-               mmc2_clk: clk at 01c20090 {
+               mmc1_output_clk: clk_mmc_output at 01c2008c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: clk_mmc_sample at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
+               mmc2_clk: clk_mmc at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: clk_mmc_output at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: clk_mmc_sample at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                ts_clk: clk at 01c20098 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -335,8 +383,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <32>;
                        status = "disabled";
                };

@@ -344,8 +398,14 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <34>;
                        status = "disabled";
                };

arch/arm/boot/dts/sun6i-a31.dtsi +96 -8

index 1c2ec913e650..574e6f19a0f6 100644
@@ -216,6 +216,22 @@
                        clock-output-names = "mmc0";
                };
 
+               mmc0_output_clk: clk_mmc_output at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: clk_mmc_sample at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
                mmc1_clk: clk at 01c2008c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -224,6 +240,22 @@
                        clock-output-names = "mmc1";
                };
 
+               mmc1_output_clk: clk_mmc_output at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: clk_mmc_sample at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
                mmc2_clk: clk at 01c20090 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -232,6 +264,22 @@
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: clk_mmc_output at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: clk_mmc_sample at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                mmc3_clk: clk at 01c20094 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -240,6 +288,22 @@
                        clock-output-names = "mmc3";
                };
 
+               mmc3_output_clk: clk_mmc_output at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_output";
+               };
+
+               mmc3_sample_clk: clk_mmc_sample at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_sample";
+               };
+
                spi0_clk: clk at 01c200a0 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -330,8 +394,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb1_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 8>;
                        reset-names = "ahb";
                        interrupts = <0 60 4>;

@@ -341,8 +411,14 @@
                mmc1: mmc at 01c10000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb1_gates 9>, <&mmc1_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 9>,
+                                <&mmc1_clk>,
+                                <&mmc1_sample_clk>,
+                                <&mmc1_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 9>;
                        reset-names = "ahb";
                        interrupts = <0 61 4>;

@@ -352,8 +428,14 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb1_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 10>;
                        reset-names = "ahb";
                        interrupts = <0 62 4>;

@@ -363,8 +445,14 @@
                mmc3: mmc at 01c12000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c12000 0x1000>;
-                       clocks = <&ahb1_gates 11>, <&mmc3_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 11>,
+                                <&mmc3_clk>,
+                                <&mmc3_sample_clk>,
+                                <&mmc3_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 11>;
                        reset-names = "ahb";
                        interrupts = <0 63 4>;

arch/arm/boot/dts/sun7i-a20.dtsi +89 -8

index ec5603da595e..fc0a90d54d63 100644
@@ -239,6 +239,22 @@
                        clock-output-names = "mmc0";
                };
 
+               mmc0_output_clk: clk_mmc_output at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: clk_mmc_sample at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
                mmc1_clk: clk at 01c2008c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -247,6 +263,22 @@
                        clock-output-names = "mmc1";
                };
 
+               mmc1_output_clk: clk_mmc_output at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: clk_mmc_sample at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
                mmc2_clk: clk at 01c20090 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -255,6 +287,22 @@
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: clk_mmc_output at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: clk_mmc_sample at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                mmc3_clk: clk at 01c20094 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -263,6 +311,22 @@
                        clock-output-names = "mmc3";
                };
 
+               mmc3_output_clk: clk_mmc_output at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_output";
+               };
+
+               mmc3_sample_clk: clk_mmc_sample at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_sample";
+               };
+
                ts_clk: clk at 01c20098 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -476,8 +540,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <0 32 4>;
                        status = "disabled";
                };

@@ -485,8 +555,14 @@
                mmc1: mmc at 01c10000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb_gates 9>, <&mmc1_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 9>,
+                                <&mmc1_clk>,
+                                <&mmc1_sample_clk>,
+                                <&mmc1_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <0 33 4>;
                        status = "disabled";
                };

@@ -494,8 +570,14 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <0 34 4>;
                        status = "disabled";
                };

@@ -503,8 +585,14 @@
                mmc3: mmc at 01c12000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c12000 0x1000>;
-                       clocks = <&ahb_gates 11>, <&mmc3_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 11>,

The MMC clock we thought we had until now are actually not one but three different clocks.

The main one is unchanged, and will have three outputs:
- The clock fed into the MMC
- a sample and output clocks, to deal with when should we output/sample data to/from the MMC bus

The phase control we had are actually controlling the two latter clocks, but the main MMC one is unchanged.

We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase shift, and the other values being the number of periods from the MMC parent clock to outphase the clock of.

Signed-off-by Maxime Ripard <[email protected]>

---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/clk-mod0.c                      | 189 ++++++++++++++++++++++
 2 files changed, 191 insertions(+)

Documentation/devicetree/bindings/clock/sunxi.txt +2 -0

index b938a990602a..eb690ed92a53 100644
@@ -47,6 +47,8 @@ Required properties:
        "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
        "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
        "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
+       "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
+       "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
        "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
        "allwinner,sun7i-a20-out-clk" - for the external output clocks
        "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31

drivers/clk/sunxi/clk-mod0.c +189 -0

index 8a7f7036aea3..4a563850ee6e 100644
@@ -16,6 +16,7 @@
 
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
+#include <linux/of_address.h>
 
 #include "clk-factors.h"
 

@@ -92,3 +93,191 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node)
        clk_prepare_enable(mbus);
 }
 CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
+
+struct mmc_phase_data {
+       u8      offset;
+};
+
+struct mmc_phase {
+       struct clk_hw           hw;
+       void __iomem            *reg;
+       struct mmc_phase_data   *data;
+       spinlock_t              *lock;
+};
+
+#define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)
+
+static int mmc_get_phase(struct clk_hw *hw)
+{
+       struct clk *mmc, *mmc_parent, *clk = hw->clk;
+       struct mmc_phase *phase = to_mmc_phase(hw);
+       unsigned int mmc_rate, mmc_parent_rate;
+       u16 step, mmc_div;
+       u32 value;
+       u8 delay;
+
+       value = readl(phase->reg);
+       delay = (value >> phase->data->offset) & 0x3;
+
+       if (!delay)
+               return 180;
+
+       /* Get the main MMC clock */
+       mmc = clk_get_parent(clk);
+       if (!mmc)
+               return -EINVAL;
+
+       /* And its rate */
+       mmc_rate = clk_get_rate(mmc);
+       if (!mmc_rate)
+               return -EINVAL;
+
+       /* Now, get the MMC parent (most likely some PLL) */
+       mmc_parent = clk_get_parent(mmc);
+       if (!mmc_parent)
+               return -EINVAL;
+
+       /* And its rate */
+       mmc_parent_rate = clk_get_rate(mmc_parent);
+       if (!mmc_parent_rate)
+               return -EINVAL;
+
+       /* Get MMC clock divider */
+       mmc_div = mmc_parent_rate / mmc_rate;
+
+       step = DIV_ROUND_CLOSEST(360, mmc_div);
+       return delay * step;
+}
+
+static int mmc_set_phase(struct clk_hw *hw, int degrees)
+{
+       struct clk *mmc, *mmc_parent, *clk = hw->clk;
+       struct mmc_phase *phase = to_mmc_phase(hw);
+       unsigned int mmc_rate, mmc_parent_rate;
+       unsigned long flags;
+       u32 value;
+       u8 delay;
+
+       /* Get the main MMC clock */
+       mmc = clk_get_parent(clk);
+       if (!mmc)
+               return -EINVAL;
+
+       /* And its rate */
+       mmc_rate = clk_get_rate(mmc);
+       if (!mmc_rate)
+               return -EINVAL;
+
+       /* Now, get the MMC parent (most likely some PLL) */
+       mmc_parent = clk_get_parent(mmc);
+       if (!mmc_parent)
+               return -EINVAL;
+
+       /* And its rate */
+       mmc_parent_rate = clk_get_rate(mmc_parent);
+       if (!mmc_parent_rate)
+               return -EINVAL;
+
+       if (degrees != 180) {
+               u16 step, mmc_div;
+
+               /* Get MMC clock divider */
+               mmc_div = mmc_parent_rate / mmc_rate;
+
+               /*
+                * We can only outphase the clocks by multiple of the
+                * PLL's period.
+                *
+                * Since the MMC clock in only a divider, and the
+                * formula to get the outphasing in degrees is deg =
+                * 360 * delta / period
+                *
+                * If we simplify this formula, we can see that the
+                * only thing that we're concerned about is the number
+                * of period we want to outphase our clock from, and
+                * the divider set by the MMC clock.
+                */
+               step = DIV_ROUND_CLOSEST(360, mmc_div);
+               delay = DIV_ROUND_CLOSEST(degrees, step);
+       } else {
+               delay = 0;
+       }
+
+       spin_lock_irqsave(phase->lock, flags);
+       value = readl(phase->reg);
+       value &= ~GENMASK(phase->data->offset + 3, phase->data->offset);
+       value |= delay << phase->data->offset;
+       writel(value, phase->reg);
+       spin_unlock_irqrestore(phase->lock, flags);
+
+       return 0;
+}
+
+static const struct clk_ops mmc_clk_ops = {
+       .get_phase      = mmc_get_phase,
+       .set_phase      = mmc_set_phase,
+};
+
+static void __init sun4i_a10_mmc_phase_setup(struct device_node *node,
+                                            struct mmc_phase_data *data)
+{
+       const char *parent_names[1] = { of_clk_get_parent_name(node, 0) };
+       struct clk_init_data init = {
+               .num_parents    = 1,
+               .parent_names   = parent_names,
+               .ops            = &mmc_clk_ops,
+       };
+
+       struct mmc_phase *phase;
+       struct clk *clk;
+
+       phase = kmalloc(sizeof(*phase), GFP_KERNEL);
+       if (!phase)
+               return;
+
+       phase->hw.init = &init;
+
+       phase->reg = of_iomap(node, 0);
+       if (!phase->reg)
+               goto err_free;
+
+       phase->data = data;
+       phase->lock = &sun4i_a10_mod0_lock;
+
+       if (of_property_read_string(node, "clock-output-names", &init.name))
+               init.name = node->name;
+
+       clk = clk_register(NULL, &phase->hw);
+       if (IS_ERR(clk))
+               goto err_unmap;
+
+       of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+       return;
+
+err_unmap:
+       iounmap(phase->reg);
+err_free:
+       kfree(phase);
+}
+
+
+static struct mmc_phase_data mmc_output_clk = {
+       .offset = 8,
+};
+
+static struct mmc_phase_data mmc_sample_clk = {
+       .offset = 20,
+};
+
+static void __init sun4i_a10_mmc_output_setup(struct device_node *node)
+{
+       sun4i_a10_mmc_phase_setup(node, &mmc_output_clk);
+}
+CLK_OF_DECLARE(sun4i_a10_mmc_output, "allwinner,sun4i-a10-mmc-output-clk", sun4i_a10_mmc_output_setup);
+
+static void __init sun4i_a10_mmc_sample_setup(struct device_node *node)
+{
+       sun4i_a10_mmc_phase_setup(node, &mmc_sample_clk);
+}
+CLK_OF_DECLARE(sun4i_a10_mmc_sample, "allwinner,sun4i-a10-mmc-sample-clk", sun4i_a10_mmc_sample_setup);

Signature · 1 line

2.0.2

Quoting Maxime Ripard (2014-08-30 13:03:09)

Quoted 11 lines

The MMC clock we thought we had until now are actually not one but three different clocks.

The main one is unchanged, and will have three outputs:
- The clock fed into the MMC
- a sample and output clocks, to deal with when should we output/sample data to/from the MMC bus

The phase control we had are actually controlling the two latter clocks, but the main MMC one is unchanged.

Quoted 5 lines

We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase shift, and the other values being the number of periods from the MMC parent clock to outphase the clock of.

Signed-off-by Maxime Ripard <[email protected]>

Looks good. Thanks a lot for revisiting this after talking to your hardware team!