clk: qcom: Fix sdc 144kHz frequency entry
Subsystems (3)
PATCH 1/1 clk: qcom: Fix sdc 144kHz frequency entry
The pre-divider for the sdc clocks only has 2 bits in it, so we can't possibly divide by anything larger than 4 here. Furthermore, we program the value of ~(n - m) and the n value is larger than 8 bits (max of 256). Replace this entry with 200kHz which is close enough to 144kHz to be usable.
--- drivers/clk/qcom/gcc-ipq806x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/qcom/gcc-ipq806x.c +1 -1
@@ -1095,7 +1095,7 @@ static struct clk_branch prng_clk = { };static const struct freq_tbl clk_tbl_sdc[] = { - {144000 ,P_PXO ,5 ,18 ,625 }, + {200000 ,P_PXO ,2 ,2 ,125 }, {400000 ,P_PLL8 ,4 ,1 ,240 }, {16000000 ,P_PLL8 ,4 ,1 ,6 }, {17070000 ,P_PLL8 ,1 ,2 ,45 },
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PATCH 1/1 clk: qcom: Fix sdc 144kHz frequency entry
Quoting Stephen Boyd (2014-08-29 12:49:26)
Quoted 10 lines
The pre-divider for the sdc clocks only has 2 bits in it, so we can't possibly divide by anything larger than 4 here. Furthermore, we program the value of ~(n - m) and the n value is larger than 8 bits (max of 256). Replace this entry with 200kHz which is close enough to 144kHz to be usable.
Cc Kumar Gala <[email protected]>Cc Andy Gross <[email protected]>Fixes 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"Signed-off-by Stephen Boyd <[email protected]>
Do you need this pulled into a 3.17-rc?
Regards,
Mike
Quoted 21 lines
--- drivers/clk/qcom/gcc-ipq806x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/qcom/gcc-ipq806x.c +1
-1@@ -1095,7 +1095,7 @@ static struct clk_branch prng_clk = { };static const struct freq_tbl clk_tbl_sdc[] = { - {144000 ,P_PXO ,5 ,18 ,625 }, + {200000 ,P_PXO ,2 ,2 ,125 }, {400000 ,P_PLL8 ,4 ,1 ,240 }, {16000000 ,P_PLL8 ,4 ,1 ,6 }, {17070000 ,P_PLL8 ,1 ,2 ,45 },Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
Quoted 7 lines · Mike Turquette
Quoting Stephen Boyd (2014-08-29 12:49:26)
Quoted 6 lines
The pre-divider for the sdc clocks only has 2 bits in it, so we can't possibly divide by anything larger than 4 here. Furthermore, we program the value of ~(n - m) and the n value is larger than 8 bits (max of 256). Replace this entry with 200kHz which is close enough to 144kHz to be usable.
Quoted 6 lines
Quoted 4 lines
Cc Kumar Gala <[email protected]>Cc Andy Gross <[email protected]>Fixes 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"Signed-off-by Stephen Boyd <[email protected]>Do you need this pulled into a 3.17-rc?
Yes that would be helpful since this fixes a driver introduced into 3.17.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Mike Turquette
AppliedPATCH 1/1 clk: qcom: Fix sdc 144kHz frequency entry
Quoting Stephen Boyd (2014-09-02 15:01:15)
Quoted 8 lines · Mike Turquette
Quoted 7 lines
Quoting Stephen Boyd (2014-08-29 12:49:26)
Quoted 6 lines
The pre-divider for the sdc clocks only has 2 bits in it, so we can't possibly divide by anything larger than 4 here. Furthermore, we program the value of ~(n - m) and the n value is larger than 8 bits (max of 256). Replace this entry with 200kHz which is close enough to 144kHz to be usable.
Quoted 8 lines
Quoted 6 lines
Quoted 4 lines
Cc Kumar Gala <[email protected]>Cc Andy Gross <[email protected]>Fixes 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"Signed-off-by Stephen Boyd <[email protected]>Do you need this pulled into a 3.17-rc?
Yes that would be helpful since this fixes a driver introduced into 3.17.
Applied to clk-fixes.
Thanks,
Mike
Quoted 5 lines
Signature · 3 lines
-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation