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PCI: designware: Fix configuration base address

PATCH New Minghuan Lian 5 participants 18 messages Sep 23, 2014 – Sep 24, 2014

Subsystems (3)
Device tree bindings PCI PCI native host bridge and endpoint drivers
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Minghuan Lian

author
#0 lore raw

PATCH 1/1 PCI: designware: Fix configuration base address

The code has calculated cfg0_base and cfg1_base when parsing 'reg' or 'ranges' property of PCI DTS node. so remove duplicate calculation. And when using 'reg', resource cfg is not used, the removed code will get incorrect configuration base.

Signed-off-by Minghuan Lian <[email protected]>
---
 drivers/pci/host/pcie-designware.c | 2 --
 1 file changed, 2 deletions(-)
drivers/pci/host/pcie-designware.c +0 -2
index c28ca05..0f3cb2a 100644
@@ -515,7 +515,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	pp->mem_base = pp->mem.start;
 
 	if (!pp->va_cfg0_base) {
-		pp->cfg0_base = pp->cfg.start;
 		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
 						pp->cfg0_size);
 		if (!pp->va_cfg0_base) {

@@ -525,7 +524,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	}
 
 	if (!pp->va_cfg1_base) {
-		pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
 		pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
 						pp->cfg1_size);
 		if (!pp->va_cfg1_base) {
Signature · 1 line
1.9.1
author
#1 lore raw

PATCH 1/1 PCI: designware: Fix IO resource end address calculation

End address should be equal to start_addr + size - 1. The patch fixes PCI IO resource end address calculation.

Signed-off-by Minghuan Lian <[email protected]>
---
 drivers/pci/host/pcie-designware.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/host/pcie-designware.c +1 -1
index 0f3cb2a..c19184f7 100644
@@ -459,7 +459,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 			pp->io.end = min_t(resource_size_t,
 					   IO_SPACE_LIMIT,
 					   range.pci_addr + range.size
-					   + global_io_offset);
+					   + global_io_offset - 1);
 			pp->io_size = resource_size(&pp->io);
 			pp->io_bus_addr = range.pci_addr;
 			pp->io_base = range.cpu_addr;
Signature · 1 line
1.9.1
maintainer
#2 lore raw

PATCH 1/1 PCI: designware: Fix IO resource end address calculation

[+cc Mohit, Jingoo]

Quoted 24 lines · Minghuan Lian

End address should be equal to start_addr + size - 1. The patch fixes PCI IO resource end address calculation.

Signed-off-by Minghuan Lian <[email protected]>
---
 drivers/pci/host/pcie-designware.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/host/pcie-designware.c +1 -1
index 0f3cb2a..c19184f7 100644
@@ -459,7 +459,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 			pp->io.end = min_t(resource_size_t,
 					   IO_SPACE_LIMIT,
 					   range.pci_addr + range.size
-					   + global_io_offset);
+					   + global_io_offset - 1);
 			pp->io_size = resource_size(&pp->io);
 			pp->io_bus_addr = range.pci_addr;
 			pp->io_base = range.cpu_addr;
Signature · 1 line
1.9.1
#3 lore raw

PATCH 1/1 PCI: designware: Fix IO resource end address calculation

Quoted 25 lines

-----Original Message-----
From: Bjorn Helgaas [mailto:bhelgaas at google.com]
Sent: Wednesday, September 24, 2014 4:24 AM
To: Minghuan Lian
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Zang Roy-R61911; Hu Mingkai-B21284; Scott Wood; Yoder Stuart-B08248; Arnd Bergmann; Mohit KUMAR DCG; Jingoo Han
Subject: Re: [PATCH] PCI: designware: Fix IO resource end address calculation

[+cc Mohit, Jingoo]

drivers/pci/host/pcie-

Quoted 9 lines · Minghuan Lian

End address should be equal to start_addr + size - 1. The patch fixes PCI IO resource end address calculation.

Signed-off-by Minghuan Lian <[email protected]>
---
 drivers/pci/host/pcie-designware.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/host/pcie- renamed from drivers/pci/host/pcie-designware.c +0 -0

designware.c

Quoted 15 lines
Quoted 13 lines

index 0f3cb2a..c19184f7 100644

drivers/pci/host/pcie-designware.c +1 -2
@@ -459,7 +459,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 			pp->io.end = min_t(resource_size_t,
 					   IO_SPACE_LIMIT,
 					   range.pci_addr + range.size
-					   + global_io_offset);
+					   + global_io_offset - 1);
 			pp->io_size = resource_size(&pp->io);
 			pp->io_bus_addr = range.pci_addr;
 			pp->io_base = range.cpu_addr;
--
Quoted 2 lines

1.9.1

- Acked-by: Mohit KUMAR <[email protected]>

Thanks
Mohit

maintainer Applied
#4 lore raw

PATCH 1/1 PCI: designware: Fix IO resource end address calculation

In reply to Minghuan Lian
Quoted 4 lines · Minghuan Lian

End address should be equal to start_addr + size - 1. The patch fixes PCI IO resource end address calculation.

Signed-off-by Minghuan Lian <[email protected]>

Applied to pci/host-designware with Mohit's ack for v3.18, thanks!

Quoted 20 lines
---
 drivers/pci/host/pcie-designware.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/host/pcie-designware.c +1 -1
index 0f3cb2a..c19184f7 100644
@@ -459,7 +459,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 			pp->io.end = min_t(resource_size_t,
 					   IO_SPACE_LIMIT,
 					   range.pci_addr + range.size
-					   + global_io_offset);
+					   + global_io_offset - 1);
 			pp->io_size = resource_size(&pp->io);
 			pp->io_bus_addr = range.pci_addr;
 			pp->io_base = range.cpu_addr;
Signature · 1 line
1.9.1
author
#5 lore raw

PATCH v3 1/3 PCI: designware: Rename get_msi_data to get_msi_addr

In reply to Minghuan Lian

The function get_msi_data is used to return MSI message address. In order to accurately express function purpose the patch rename it to get_msi_addr.

Signed-off-by Minghuan Lian <[email protected]>

---
Change log:
v3: no change
v2: no change just derived from v1

 drivers/pci/host/pcie-designware.c | 4 ++--
 drivers/pci/host/pcie-designware.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
drivers/pci/host/pcie-designware.c +2 -2
index 5d720c2..1c09f814 100644
@@ -361,8 +361,8 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
 	 */
 	desc->msi_attrib.multiple = msgvec;
 
-	if (pp->ops->get_msi_data)
-		msg.address_lo = pp->ops->get_msi_data(pp);
+	if (pp->ops->get_msi_addr)
+		msg.address_lo = pp->ops->get_msi_addr(pp);
 	else
 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
 	msg.address_hi = 0x0;
drivers/pci/host/pcie-designware.h +1 -1
index 48f8670..904e40a 100644
@@ -70,7 +70,7 @@ struct pcie_host_ops {
 	void (*host_init)(struct pcie_port *pp);
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
-	u32 (*get_msi_data)(struct pcie_port *pp);
+	u32 (*get_msi_addr)(struct pcie_port *pp);
 	void (*scan_bus)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
 };
Signature · 1 line
1.9.1
maintainer
#6 lore raw

PATCH v3 1/3 PCI: designware: Rename get_msi_data to get_msi_addr

[+cc Mohit, Jingoo]

Quoted 5 lines · Minghuan Lian

The function get_msi_data is used to return MSI message address. In order to accurately express function purpose the patch rename it to get_msi_addr.

Signed-off-by Minghuan Lian <[email protected]>

I think this looks like a good idea, but it needs an ack from Mohit and/or Jingoo (cc'd).

You previously asked whether .get_msi_addr() should also be changed to return u64 instead of u32. I think it should, and you can do that in a separate patch that also changes the use in dw_msi_setup_irq() to split the 64-bit result into msg.address_lo and msg.address_hi.

I don't see any implementations of .get_msi_data() or .get_msi_addr(), so this seems pretty straightforward.

Bjorn

Quoted 40 lines

---
Change log:
v3: no change
v2: no change just derived from v1

 drivers/pci/host/pcie-designware.c | 4 ++--
 drivers/pci/host/pcie-designware.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
drivers/pci/host/pcie-designware.c +2 -2
index 5d720c2..1c09f814 100644
@@ -361,8 +361,8 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
 	 */
 	desc->msi_attrib.multiple = msgvec;
 
-	if (pp->ops->get_msi_data)
-		msg.address_lo = pp->ops->get_msi_data(pp);
+	if (pp->ops->get_msi_addr)
+		msg.address_lo = pp->ops->get_msi_addr(pp);
 	else
 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
 	msg.address_hi = 0x0;
drivers/pci/host/pcie-designware.h +1 -1
index 48f8670..904e40a 100644
@@ -70,7 +70,7 @@ struct pcie_host_ops {
 	void (*host_init)(struct pcie_port *pp);
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
-	u32 (*get_msi_data)(struct pcie_port *pp);
+	u32 (*get_msi_addr)(struct pcie_port *pp);
 	void (*scan_bus)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
 };
Signature · 1 line
1.9.1
#7 lore raw

PATCH v3 1/3 PCI: designware: Rename get_msi_data to get_msi_addr

Hello Minghuan,

Quoted 13 lines

-----Original Message-----
From: Bjorn Helgaas [mailto:bhelgaas at google.com]
Sent: Wednesday, September 24, 2014 4:16 AM
To: Minghuan Lian
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Zang Roy-R61911; Hu Mingkai-B21284; Scott Wood; Yoder Stuart-B08248; Arnd Bergmann; Mohit KUMAR DCG; Jingoo Han
Subject: Re: [PATCH v3 1/3] PCI: designware: Rename get_msi_data to get_msi_addr

[+cc Mohit, Jingoo]

On Tue, Sep 23, 2014 at 10:28:58PM +0800, Minghuan Lian wrote:

Quoted 9 lines
Quoted 5 lines

The function get_msi_data is used to return MSI message address. In order to accurately express function purpose the patch rename it to get_msi_addr.

Signed-off-by Minghuan Lian <[email protected]>

I think this looks like a good idea, but it needs an ack from Mohit and/or Jingoo (cc'd).

- Acked-by: Mohit KUMAR <[email protected]>

Thanks
Mohit

Quoted 53 lines

You previously asked whether .get_msi_addr() should also be changed to return u64 instead of u32. I think it should, and you can do that in a separate patch that also changes the use in dw_msi_setup_irq() to split the 64-bit result into msg.address_lo and msg.address_hi.

I don't see any implementations of .get_msi_data() or .get_msi_addr(), so this seems pretty straightforward.

Bjorn

drivers/pci/host/pcie-designware.c static int dw_msi_setup_irq(struct msi_chip *chip,

Quoted 15 lines

---
Change log:
v3: no change
v2: no change just derived from v1

 drivers/pci/host/pcie-designware.c | 4 ++--
drivers/pci/host/pcie-designware.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
drivers/pci/host/pcie-designware.c +0 -0
index 5d720c2..1c09f814 100644
@@ -361,8 +361,8 @@ static int dw_msi_setup_irq(struct msi_chip *chip,

struct pci_dev *pdev,

Quoted 27 lines
drivers/pci/host/pcie-designware.c +2 -2
 	 */
 	desc->msi_attrib.multiple = msgvec;
 
-	if (pp->ops->get_msi_data)
-		msg.address_lo = pp->ops->get_msi_data(pp);
+	if (pp->ops->get_msi_addr)
+		msg.address_lo = pp->ops->get_msi_addr(pp);
 	else
 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
 	msg.address_hi = 0x0;
drivers/pci/host/pcie-designware.h +1 -2
index 48f8670..904e40a 100644
@@ -70,7 +70,7 @@ struct pcie_host_ops {
 	void (*host_init)(struct pcie_port *pp);
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
-	u32 (*get_msi_data)(struct pcie_port *pp);
+	u32 (*get_msi_addr)(struct pcie_port *pp);
 	void (*scan_bus)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
 };
--

1.9.1

maintainer Applied
#8 lore raw

PATCH v3 1/3 PCI: designware: Rename get_msi_data to get_msi_addr

In reply to Minghuan Lian
Quoted 5 lines · Minghuan Lian

The function get_msi_data is used to return MSI message address. In order to accurately express function purpose the patch rename it to get_msi_addr.

Signed-off-by Minghuan Lian <[email protected]>

Applied patches 1 and 2 to pci/host-designware with Mohit's ack for v3.18, thanks!

Quoted 40 lines

---
Change log:
v3: no change
v2: no change just derived from v1

 drivers/pci/host/pcie-designware.c | 4 ++--
 drivers/pci/host/pcie-designware.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)
drivers/pci/host/pcie-designware.c +2 -2
index 5d720c2..1c09f814 100644
@@ -361,8 +361,8 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
 	 */
 	desc->msi_attrib.multiple = msgvec;
 
-	if (pp->ops->get_msi_data)
-		msg.address_lo = pp->ops->get_msi_data(pp);
+	if (pp->ops->get_msi_addr)
+		msg.address_lo = pp->ops->get_msi_addr(pp);
 	else
 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
 	msg.address_hi = 0x0;
drivers/pci/host/pcie-designware.h +1 -1
index 48f8670..904e40a 100644
@@ -70,7 +70,7 @@ struct pcie_host_ops {
 	void (*host_init)(struct pcie_port *pp);
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
-	u32 (*get_msi_data)(struct pcie_port *pp);
+	u32 (*get_msi_addr)(struct pcie_port *pp);
 	void (*scan_bus)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
 };
Signature · 1 line
1.9.1
author
#9 lore raw

PATCH v3 2/3 PCI: designware: Add get_msi_data() to pcie_host_ops

In reply to Minghuan Lian

The patch adds get_msi_data() for some platforms to return their special MSI message data.

Signed-off-by Minghuan Lian <[email protected]>

---
Change log:
v3: no change
v2: no change just derived from v1

 drivers/pci/host/pcie-designware.c | 7 ++++++-
 drivers/pci/host/pcie-designware.h | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)
drivers/pci/host/pcie-designware.c +6 -1
index 1c09f814..c28ca05 100644
@@ -366,7 +366,12 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
 	else
 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
 	msg.address_hi = 0x0;
-	msg.data = pos;
+
+	if (pp->ops->get_msi_data)
+		msg.data = pp->ops->get_msi_data(pp, pos);
+	else
+		msg.data = pos;
+
 	write_msi_msg(irq, &msg);
 
 	return 0;
drivers/pci/host/pcie-designware.h +1 -0
index 904e40a..c625675 100644
@@ -71,6 +71,7 @@ struct pcie_host_ops {
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
 	u32 (*get_msi_addr)(struct pcie_port *pp);
+	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
 	void (*scan_bus)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
 };
Signature · 1 line
1.9.1
maintainer
#10 lore raw

PATCH v3 2/3 PCI: designware: Add get_msi_data() to pcie_host_ops

[+cc Mohit, Jingoo]

Quoted 46 lines · Minghuan Lian

The patch adds get_msi_data() for some platforms to return their special MSI message data.

Signed-off-by Minghuan Lian <[email protected]>

---
Change log:
v3: no change
v2: no change just derived from v1

 drivers/pci/host/pcie-designware.c | 7 ++++++-
 drivers/pci/host/pcie-designware.h | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)
drivers/pci/host/pcie-designware.c +6 -1
index 1c09f814..c28ca05 100644
@@ -366,7 +366,12 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
 	else
 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
 	msg.address_hi = 0x0;
-	msg.data = pos;
+
+	if (pp->ops->get_msi_data)
+		msg.data = pp->ops->get_msi_data(pp, pos);
+	else
+		msg.data = pos;
+
 	write_msi_msg(irq, &msg);
 
 	return 0;
drivers/pci/host/pcie-designware.h +1 -0
index 904e40a..c625675 100644
@@ -71,6 +71,7 @@ struct pcie_host_ops {
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
 	u32 (*get_msi_addr)(struct pcie_port *pp);
+	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
 	void (*scan_bus)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
 };
Signature · 1 line
1.9.1
#11 lore raw

PATCH v3 2/3 PCI: designware: Add get_msi_data() to pcie_host_ops

Quoted 54 lines

-----Original Message-----
From: Bjorn Helgaas [mailto:bhelgaas at google.com]
Sent: Wednesday, September 24, 2014 4:44 AM
To: Minghuan Lian
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Zang Roy-R61911; Hu Mingkai-B21284; Scott Wood; Yoder Stuart-B08248; Arnd Bergmann; Mohit KUMAR DCG; Jingoo Han
Subject: Re: [PATCH v3 2/3] PCI: designware: Add get_msi_data() to pcie_host_ops

[+cc Mohit, Jingoo]

drivers/pci/host/pcie-designware.c static int dw_msi_setup_irq(struct msi_chip *chip,

Quoted 19 lines · Minghuan Lian

The patch adds get_msi_data() for some platforms to return their special MSI message data.

Signed-off-by Minghuan Lian <[email protected]>

---
Change log:
v3: no change
v2: no change just derived from v1

 drivers/pci/host/pcie-designware.c | 7 ++++++-
drivers/pci/host/pcie-designware.h | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)
drivers/pci/host/pcie-designware.c +0 -0
index 1c09f814..c28ca05 100644
@@ -366,7 +366,12 @@ static int dw_msi_setup_irq(struct msi_chip *chip,

struct pci_dev *pdev,

Quoted 21 lines
drivers/pci/host/pcie-designware.c +6 -1
 	else
 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
 	msg.address_hi = 0x0;
-	msg.data = pos;
+
+	if (pp->ops->get_msi_data)
+		msg.data = pp->ops->get_msi_data(pp, pos);
+	else
+		msg.data = pos;
+
 	write_msi_msg(irq, &msg);
 
 	return 0;
drivers/pci/host/pcie-designware.h +0 -0
index 904e40a..c625675 100644
@@ -71,6 +71,7 @@ struct pcie_host_ops {
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
Quoted 8 lines
Quoted 8 lines
drivers/pci/host/pcie-designware.h +1 -1
 	u32 (*get_msi_addr)(struct pcie_port *pp);
+	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
 	void (*scan_bus)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
 };
--

1.9.1

- Acked-by: Mohit KUMAR <[email protected]>

Thanks
Mohit

author
#12 lore raw

PATCH v3 3/3 PCI: Layerscape: Add Layerscape PCIe driver

In reply to Minghuan Lian

Add support for Freescale Layerscape PCIe controller. This driver re-uses the designware core code.

Signed-off-by Minghuan Lian <[email protected]>

---
Change log:
v3:
1. Add prefechable mem region and adjust mem region
2. Rename 'pcie-scfg' to 'fsl,pcie-scfg'
3. Change MSI interrupt handler
4. Use module_platform_driver_probe instead of subsys_initcall

v2:
1. Add pcie-scfg to link scfg device node and remove "fsl, ls-pcie" compatible
2. Use regmap API to access scfg.
3. remove ls1021 PCI device ID.
4. remove unused irq pme_irq and ls_pcie_list.
5. Do not set scfg bit reverse mode

 .../devicetree/bindings/pci/layerscape-pci.txt     |  46 ++++
 drivers/pci/host/Kconfig                           |   7 +
 drivers/pci/host/Makefile                          |   1 +
 drivers/pci/host/pci-layerscape.c                  | 274 +++++++++++++++++++++
 4 files changed, 328 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt
 create mode 100644 drivers/pci/host/pci-layerscape.c
Documentation/devicetree/bindings/pci/layerscape-pci.txt new file +46 -0
new file mode 100644
index 0000000..d7b0026
@@ -0,0 +1,46 @@
+Freescale Layerscape PCIe controller
+
+This PCIe host controller is based on the Synopsis Designware PCIe IP
+and thus inherits all the common properties defined in designware-pcie.txt.
+
+Required properties:
+- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
+- reg: base addresses and lengths of the PCIe controller
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+  entry for each entry in the interrupt-names property.
+- interrupt-names: Must include the following entries:
+  "intr": The interrupt that is asserted for controller interrupts
+  "msi": The interrupt that is asserted when an MSI is received
+  "pme": The interrupt that is asserted when PME state changes
+- fsl,pcie-scfg: Must include two entries.
+  The first entry must be a link to the SCFG device node
+  The second entry must be '0' or '1' based on physical PCIe controller index.
+  used to get SCFG PEXN registers
+
+Example:
+
+	pcie at 3400000 {
+		compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
+		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+		reg-names = "regs", "config";
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */
+			     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+		interrupt-names = "intr", "msi", "pme";
+		fsl,pcie-scfg = <&scfg 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000   /* prefetchable memory */
+			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
+				<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+	};
drivers/pci/host/Kconfig +7 -0
index 34134d6..7c49456 100644
@@ -82,4 +82,11 @@ config PCIE_XILINX
 	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
 	  Host Bridge driver.
 
+config PCI_LAYERSCAPE
+	bool "Freescale Layerscape PCIe controller"
+	select PCIE_DW
+	select MFD_SYSCON
+	help
+	  Say Y here if you want PCIe controller support on Layerscape SoCs.
+
 endmenu
drivers/pci/host/Makefile +1 -0
index 182929c..fd10554 100644
@@ -10,3 +10,4 @@ obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
 obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
+obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
drivers/pci/host/pci-layerscape.c new file +274 -0

274 lines not on this page · raw message

Signature · 1 line
1.9.1
#13 lore raw

PATCH v3 3/3 PCI: Layerscape: Add Layerscape PCIe driver

Quoted 6 lines · Minghuan Lian
drivers/pci/host/Kconfig +0 -0
index 34134d6..7c49456 100644
@@ -82,4 +82,11 @@ config PCIE_XILINX
 	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe

drivers/pci/host/Kconfig config PCIE_XILINX · line 92

Quoted 10 lines
drivers/pci/host/Kconfig +7 -0
 	  Host Bridge driver.
 
+config PCI_LAYERSCAPE
+	bool "Freescale Layerscape PCIe controller"
+	select PCIE_DW
+	select MFD_SYSCON
+	help
+	  Say Y here if you want PCIe controller support on Layerscape SoCs.
+
 endmenu

Are you sure there are no dependencies for this to build? At the least you need OF.

I think you should also be selecting REGMAP.

-Scott

#14 lore raw

PATCH v3 3/3 PCI: Layerscape: Add Layerscape PCIe driver

Hi Scott,

Please see my comments inline.

Quoted 20 lines · Scott Wood
Quoted 6 lines · Minghuan Lian
drivers/pci/host/Kconfig +0 -0
index 34134d6..7c49456 100644
@@ -82,4 +82,11 @@ config PCIE_XILINX
  	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe

drivers/pci/host/Kconfig config PCIE_XILINX · line 92

Quoted 10 lines
drivers/pci/host/Kconfig +7 -0
  	  Host Bridge driver.
 
+config PCI_LAYERSCAPE
+	bool "Freescale Layerscape PCIe controller"
+	select PCIE_DW
+	select MFD_SYSCON
+	help
+	  Say Y here if you want PCIe controller support on Layerscape SoCs.
+
  endmenu

Are you sure there are no dependencies for this to build? At the least you need OF.

Quoted 1 line

I think you should also be selecting REGMAP.

[Minghuan] Yes, it does need OF. I will add 'depends on OF' next version. Because MFS_SYSCON will select REGMAP, so I think it is enough to select MFS_SYSCON.

Quoted 3 lines

-Scott

maintainer
#15 lore raw

PATCH 1/1 PCI: designware: Fix configuration base address

In reply to Minghuan Lian

[+cc Mohit, Jingoo]

Quoted 33 lines · Minghuan Lian

The code has calculated cfg0_base and cfg1_base when parsing 'reg' or 'ranges' property of PCI DTS node. so remove duplicate calculation. And when using 'reg', resource cfg is not used, the removed code will get incorrect configuration base.

Signed-off-by Minghuan Lian <[email protected]>
---
 drivers/pci/host/pcie-designware.c | 2 --
 1 file changed, 2 deletions(-)
drivers/pci/host/pcie-designware.c +0 -2
index c28ca05..0f3cb2a 100644
@@ -515,7 +515,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	pp->mem_base = pp->mem.start;
 
 	if (!pp->va_cfg0_base) {
-		pp->cfg0_base = pp->cfg.start;
 		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
 						pp->cfg0_size);
 		if (!pp->va_cfg0_base) {

@@ -525,7 +524,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	}
 
 	if (!pp->va_cfg1_base) {
-		pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
 		pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
 						pp->cfg1_size);
 		if (!pp->va_cfg1_base) {
Signature · 1 line
1.9.1
#16 lore raw

PATCH 1/1 PCI: designware: Fix configuration base address

Hello Minghuan,

Quoted 39 lines

-----Original Message-----
From: Bjorn Helgaas [mailto:bhelgaas at google.com]
Sent: Wednesday, September 24, 2014 4:23 AM
To: Minghuan Lian
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Zang Roy-R61911; Hu Mingkai-B21284; Scott Wood; Yoder Stuart-B08248; Arnd Bergmann; Mohit KUMAR DCG; Jingoo Han
Subject: Re: [PATCH] PCI: designware: Fix configuration base address

[+cc Mohit, Jingoo]

Quoted 27 lines · Minghuan Lian

The code has calculated cfg0_base and cfg1_base when parsing 'reg' or 'ranges' property of PCI DTS node. so remove duplicate calculation. And when using 'reg', resource cfg is not used, the removed code will get incorrect configuration base.

Signed-off-by Minghuan Lian <[email protected]>
---
 drivers/pci/host/pcie-designware.c | 2 --
 1 file changed, 2 deletions(-)
drivers/pci/host/pcie-designware.c +0 -1
index c28ca05..0f3cb2a 100644
@@ -515,7 +515,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	pp->mem_base = pp->mem.start;
 
 	if (!pp->va_cfg0_base) {
-		pp->cfg0_base = pp->cfg.start;
 		pp->va_cfg0_base = devm_ioremap(pp->dev, pp-
 cfg0_base,
 						pp->cfg0_size);
drivers/pci/host/pcie-designware.c +0 -0
 		if (!pp->va_cfg0_base) {

@@ -525,7 +524,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	}
Quoted 9 lines
Quoted 9 lines
drivers/pci/host/pcie-designware.c +0 -1
 	if (!pp->va_cfg1_base) {
-		pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
 		pp->va_cfg1_base = devm_ioremap(pp->dev, pp-
 cfg1_base,
 						pp->cfg1_size);

if (!pp->va_cfg1_base) {
--
1.9.1

- Acked-by: Mohit KUMAR <[email protected]>

Thanks
Mohit

maintainer Applied
#17 lore raw

PATCH 1/1 PCI: designware: Fix configuration base address

In reply to Minghuan Lian
Quoted 6 lines · Minghuan Lian

The code has calculated cfg0_base and cfg1_base when parsing 'reg' or 'ranges' property of PCI DTS node. so remove duplicate calculation. And when using 'reg', resource cfg is not used, the removed code will get incorrect configuration base.

Signed-off-by Minghuan Lian <[email protected]>

Applied to pci/host-designware with Mohit's ack for v3.18, thanks!

Quoted 27 lines
---
 drivers/pci/host/pcie-designware.c | 2 --
 1 file changed, 2 deletions(-)
drivers/pci/host/pcie-designware.c +0 -2
index c28ca05..0f3cb2a 100644
@@ -515,7 +515,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	pp->mem_base = pp->mem.start;
 
 	if (!pp->va_cfg0_base) {
-		pp->cfg0_base = pp->cfg.start;
 		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
 						pp->cfg0_size);
 		if (!pp->va_cfg0_base) {

@@ -525,7 +524,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	}
 
 	if (!pp->va_cfg1_base) {
-		pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
 		pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
 						pp->cfg1_size);
 		if (!pp->va_cfg1_base) {
Signature · 1 line
1.9.1