arm: socfpga: Usability fixes
Subsystems (5)
cover arm: socfpga: Usability fixes
This entire series is the second stab at making SoCFPGA usable with mainline U-Boot again. There are much fewer bits missing than in the last series, more cleanup happened and bugs were fixed. This allows me to use mainline U-Boot on my SoCFPGA systems.
The big missing part is the SPL generation, which still needs a lot of additional work. We also miss the Cadence QSPI controller driver.
This set contains patches for a few subsystems, which are utilized by the SoCFPGA, but the most part is the SoCFPGA chip support. This series now contains cleanup for the mayhem in drivers/fpga/altera.c code, which was terrible, but is now much better.
Charles Manning (1):
tools: socfpga: Add socfpga preloader signing to mkimage
Chin Liang See (2):
arm: socfpga: Enable DWMMC for SOCFPGA
arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot
Marek Vasut (32):
net: dwc: Fix cache alignment issues
net: dwc: Make the cache handling less cryptic
mmc: dw_mmc: Fix cache alignment issue
arm: socfpga: Clean up base address file
arm: socfpga: sysmgr: Clean up system manager
arm: socfpga: clock: Implant order into bit definitions
arm: socfpga: clock: Drop nonsense inlining from clock manager code
arm: socfpga: clock: Add missing stubs into board file
arm: socfpga: clock: Trim down code duplication
arm: socfpga: clock: Clean up bit definitions
arm: socfpga: clock: Sync with reference code
arm: socfpga: timer: Pull the timer reload value from config file
arm: socfpga: reset: Add EMAC reset functions
arm: socfpga: board: Align checkboard() output
fpga: altera: Clean up the printing and debug
fpga: altera: Clean up altera_validate function
fpga: altera: More indentation trimdown
fpga: altera: Move altera_validate to the top
fpga: altera: Make altera_validate return normal values
fpga: altera: Clean up enums in altera.h
fpga: altera: Turn the switches into table lookup
arm: socfpga: reset: Add function to reset FPGA bridges
arm: socfpga: sysmgr: Add FPGA bits into system manager
arm: cache: Add support for write-allocate D-Cache
arm: socfpga: cache: Define cacheline size
arm: socfpga: cache: Enable D-Cache
arm: socfpga: cache: Enable PL310 L2 cache
arm: socfpga: scu: Add SCU register file
arm: socfpga: nic301: Add NIC-301 GPV register file
arm: socfpga: pl310: Map SDRAM to 0x0
arm: socfpga: Move cache_enable to CPU code
arm: socfpga: Use CMD_FS_GENERIC
Pavel Machek (16):
net: Remove unused CONFIG_DW_SEARCH_PHY from configs
net: phy: Cleanup drivers/net/phy/micrel.c
mmc: dw_mmc: cleanups
arm: socfpga: Complete the list of base addresses
arm: socfpga: Add watchdog disable for socfpga
arm: socfpga: clock: Add code to read clock configuration
arm: socfpga: mmc: Pick the clock from clock manager
arm: socfpga: misc: Add proper ethernet initialization
arm: socfpga: misc: Add SD controller init
arm: socfpga: misc: Align print_cpuinfo() output
arm: socfpga: board: Correctly set ATAG position
arm: socfpga: fpga: Add SoCFPGA FPGA programming interface
arm: socfpga: nic301: Add NIC-301 configuration code
arm: socfpga: Add command to control HPS-FPGA bridges
arm: socfpga: Clean up SoCFPGA configuration
arm: socfpga: Split SoCFPGA configuration
arch/arm/cpu/armv7/socfpga/Makefile | 3 +- arch/arm/cpu/armv7/socfpga/clock_manager.c | 340 ++++++++++++++++----- arch/arm/cpu/armv7/socfpga/fpga_manager.c | 78 +++++ arch/arm/cpu/armv7/socfpga/misc.c | 235 +++++++++++++- arch/arm/cpu/armv7/socfpga/reset_manager.c | 67 ++++ arch/arm/cpu/armv7/socfpga/spl.c | 174 ++++++----- arch/arm/cpu/armv7/socfpga/system_manager.c | 57 +++- arch/arm/cpu/armv7/socfpga/timer.c | 2 + arch/arm/include/asm/arch-socfpga/clock_manager.h | 306 ++++++++++++------- arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 +++++ arch/arm/include/asm/arch-socfpga/nic301.h | 195 ++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 9 + arch/arm/include/asm/arch-socfpga/scu.h | 23 ++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 62 +++- arch/arm/include/asm/arch-socfpga/system_manager.h | 111 +++++-- arch/arm/include/asm/system.h | 1 + arch/arm/lib/cache-cp15.c | 2 + board/altera/socfpga/pll_config.h | 3 + board/altera/socfpga/socfpga_cyclone5.c | 6 +- common/image.c | 1 + drivers/fpga/Makefile | 1 + drivers/fpga/altera.c | 308 ++++++++----------- drivers/fpga/socfpga.c | 301 ++++++++++++++++++ drivers/mmc/dw_mmc.c | 34 ++- drivers/mmc/socfpga_dw_mmc.c | 15 +- drivers/net/designware.c | 46 +-- drivers/net/phy/micrel.c | 7 +- include/altera.h | 82 +++-- include/configs/axs101.h | 1 - include/configs/socfpga_cyclone5.h | 318 ++++--------------- include/configs/socfpga_cyclone5_common.h | 196 ++++++++++++ include/dwmmc.h | 2 +- include/image.h | 1 + tools/Makefile | 1 + tools/imagetool.c | 2 + tools/imagetool.h | 1 + tools/socfpgaimage.c | 255 ++++++++++++++++ 37 files changed, 2503 insertions(+), 820 deletions(-) create mode 100644 arch/arm/cpu/armv7/socfpga/fpga_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/fpga_manager.h create mode 100644 arch/arm/include/asm/arch-socfpga/nic301.h create mode 100644 arch/arm/include/asm/arch-socfpga/scu.h create mode 100644 drivers/fpga/socfpga.c create mode 100644 include/configs/socfpga_cyclone5_common.h create mode 100644 tools/socfpgaimage.c
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Signature · 1 line
2.0.0
PATCH v2 1/51 net: Remove unused CONFIG_DW_SEARCH_PHY from configs
From: Pavel Machek <[email protected]>
Remove this symbol from configs, since it's unused.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Joe Hershberger <[email protected]>
--- include/configs/axs101.h | 1 - include/configs/socfpga_cyclone5.h | 1 - 2 files changed, 2 deletions(-)
V2: Drop this option globally from all configs
include/configs/axs101.h +0 -1
@@ -125,7 +125,6 @@*/ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_AUTONEG -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI /*
include/configs/socfpga_cyclone5.h +0 -1
@@ -225,7 +225,6 @@/* designware */ #define CONFIG_NET_MULTI #define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_DW_SEARCH_PHY #define CONFIG_MII #define CONFIG_PHY_GIGE #define CONFIG_DW_AUTONEG
Signature · 1 line
2.0.0
PATCH v2 1/51 net: Remove unused CONFIG_DW_SEARCH_PHY from configs
Quoted 37 lines · marex at denx.de
From: Pavel Machek <[email protected]>
Remove this symbol from configs, since it's unused.
Signed-off-by Pavel Machek <[email protected]>Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Cc Joe Hershberger <[email protected]>--- include/configs/axs101.h | 1 - include/configs/socfpga_cyclone5.h | 1 - 2 files changed, 2 deletions(-)V2: Drop this option globally from all configs
include/configs/axs101.h +0
-1@@ -125,7 +125,6 @@*/ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_AUTONEG -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI /* include/configs/socfpga_cyclone5.h +0
-0
include/configs/socfpga_cyclone5.h line 230
Quoted 7 lines
include/configs/socfpga_cyclone5.h +0
-1@@ -225,7 +225,6 @@/* designware */ #define CONFIG_NET_MULTI #define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_DW_SEARCH_PHY #define CONFIG_MII #define CONFIG_PHY_GIGE #define CONFIG_DW_AUTONEG
Acked-by Chin Liang See <[email protected]>
PATCH 2/51 net: phy: Cleanup drivers/net/phy/micrel.c
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Old saying says that more than three exclamation marks in a row are sign of mental disease. Cleanup micrel.c.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Joe Hershberger <[email protected]>
--- drivers/net/phy/micrel.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)
drivers/net/phy/micrel.c +3 -4
@@ -25,8 +25,7 @@ static struct phy_driver KSZ804_driver = {#ifndef CONFIG_PHY_MICREL_KSZ9021 /* * I can't believe Micrel used the exact same part number -* for the KSZ9021 -* Shame Micrel, Shame!!!!! +* for the KSZ9021. Shame Micrel, Shame! */ static struct phy_driver KS8721_driver = { .name = "Micrel KS8721BL",
@@ -40,7 +39,7 @@ static struct phy_driver KS8721_driver = {#endif -/** +/* * KSZ9021 - KSZ9031 common */
@@ -69,8 +68,8 @@ static int ksz90xx_startup(struct phy_device *phydev) phydev->speed =SPEED_10 ;return 0 ; } -#ifdef CONFIG_PHY_MICREL_KSZ9021 +#ifdef CONFIG_PHY_MICREL_KSZ9021 /* * KSZ9021 */
Signature · 1 line
2.0.0
PATCH 2/51 net: phy: Cleanup drivers/net/phy/micrel.c
Quoted 42 lines · marex at denx.de
From: Pavel Machek <[email protected]>
Old saying says that more than three exclamation marks in a row are sign of mental disease. Cleanup
micrel.c.Signed-off-by Pavel Machek <[email protected]>Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Cc Joe Hershberger <[email protected]>--- drivers/net/phy/micrel.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)drivers/net/phy/micrel.c +2
-3@@ -25,8 +25,7 @@ static struct phy_driver KSZ804_driver = {#ifndef CONFIG_PHY_MICREL_KSZ9021 /* * I can't believe Micrel used the exact same part number -* for the KSZ9021 -* Shame Micrel, Shame!!!!! +* for the KSZ9021. Shame Micrel, Shame! */ static struct phy_driver KS8721_driver = { .name = "Micrel KS8721BL",@@ -40,7 +39,7 @@ static struct phy_driver KS8721_driver = {#endif -/** +/* * KSZ9021 - KSZ9031 common */
drivers/net/phy/micrel.c static int ksz90xx_startup(struct phy_device *phydev) · line 75
Quoted 9 lines
drivers/net/phy/micrel.c +1
-1@@ -69,8 +68,8 @@ static int ksz90xx_startup(struct phy_device *phydev) phydev->speed =SPEED_10 ;return 0 ; } -#ifdef CONFIG_PHY_MICREL_KSZ9021 +#ifdef CONFIG_PHY_MICREL_KSZ9021 /* * KSZ9021 */
Acked-by Chin Liang See <[email protected]>
PATCH 3/51 net: dwc: Fix cache alignment issues
In reply to Marek VasutFix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Joe Hershberger <[email protected]>
--- drivers/net/designware.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/net/designware.c +4 -2
@@ -303,7 +303,8 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)/* Flush data to be sent */ flush_dcache_range ((unsigned long )desc_p->dmamac_addr, - (unsigned long )desc_p->dmamac_addr + length); + (unsigned long )desc_p->dmamac_addr + +roundup (length,ARCH_DMA_MINALIGN ));#if defined(CONFIG_DW_ALTDESCRIPTOR ) desc_p->txrx_status |=DESC_TXSTS_TXFIRST |DESC_TXSTS_TXLAST ;
@@ -372,7 +373,8 @@ static int dw_eth_recv(struct eth_device *dev)/* Flush only status field - others weren't changed */ flush_dcache_range ((unsigned long )&desc_p->txrx_status, (unsigned long )&desc_p->txrx_status + -sizeof (desc_p->txrx_status)); +roundup (sizeof (desc_p->txrx_status), +ARCH_DMA_MINALIGN ));/* Test the wrap-around condition. */ if (++desc_num >=CONFIG_RX_DESCR_NUM )
Signature · 1 line
2.0.0
PATCH 3/51 net: dwc: Fix cache alignment issues
Hi Marek,
Quoted 32 lines · marex at denx.de
Fix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Cc Joe Hershberger <[email protected]>--- drivers/net/designware.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)drivers/net/designware.c +2
-1@@ -303,7 +303,8 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)/* Flush data to be sent */ flush_dcache_range ((unsigned long )desc_p->dmamac_addr, - (unsigned long )desc_p->dmamac_addr + length); + (unsigned long )desc_p->dmamac_addr + +roundup (length,ARCH_DMA_MINALIGN ));#if defined(CONFIG_DW_ALTDESCRIPTOR ) desc_p->txrx_status |=DESC_TXSTS_TXFIRST |DESC_TXSTS_TXLAST ;
drivers/net/designware.c static int dw_eth_recv(struct eth_device *dev) · line 378
Quoted 7 lines
drivers/net/designware.c +2
-1@@ -372,7 +373,8 @@ static int dw_eth_recv(struct eth_device *dev)/* Flush only status field - others weren't changed */ flush_dcache_range ((unsigned long )&desc_p->txrx_status, (unsigned long )&desc_p->txrx_status + -sizeof (desc_p->txrx_status)); +roundup (sizeof (desc_p->txrx_status), +ARCH_DMA_MINALIGN ));
Current flush_dcache_range will clean & invalidate the whole cache line which contain the address specified by start and end. Hence I believe the alignment is not needed. Wonder the existing code got issue?
Thanks
Chin Liang
Quoted 2 lines
drivers/net/designware.c +0
-0/* Test the wrap-around condition. */ if (++desc_num >=CONFIG_RX_DESCR_NUM )
PATCH 3/51 net: dwc: Fix cache alignment issues
Quoted 46 lines · Chin Liang See
Hi Marek,
Quoted 43 lines · marex at denx.de
Fix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Cc Joe Hershberger <[email protected]>---
drivers/net/designware.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)drivers/net/designware.c +2
-1@@ -303,7 +303,8 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)/* Flush data to be sent */ flush_dcache_range ((unsigned long )desc_p->dmamac_addr, - (unsigned long )desc_p->dmamac_addr + length); + (unsigned long )desc_p->dmamac_addr + +roundup (length,ARCH_DMA_MINALIGN ));#if
defined(CONFIG_DW_ALTDESCRIPTOR)drivers/net/designware.c +0
-0desc_p->txrx_status |=DESC_TXSTS_TXFIRST |DESC_TXSTS_TXLAST ;@@ -372,7 +373,8 @@ static int dw_eth_recv(struct eth_device *dev)/* Flush only status field - others weren't changed */ flush_dcache_range((unsigned long)&desc_p->txrx_status, (unsigned long)&desc_p->txrx_status +
Quoted 7 lines
drivers/net/designware.c static int dw_eth_recv(struct eth_device *dev) · line 377
Quoted 3 lines
drivers/net/designware.c +2
-1- sizeof(desc_p->txrx_status)); +roundup (sizeof (desc_p->txrx_status), + ARCH_DMA_MINALIGN));Current
flush_dcache_rangewill clean & invalidate the whole cache line which contain the address specified by start and end. Hence I believe the alignment is not needed. Wonder the existing code got issue?
Don't be mistaken, please see drivers/net/designware.h :sizeof(desc_p->txrx_status) == sizeof(u32) == 4
Thus the flush is called like so:
flush_dcache_range(<address of start of DMA descriptor>,
<address of start of DMA descriptor> + 4);
On ARM, the cache ops have to be aligned to cacheline length, so the above code will indeed have issues. Thus the alignment.
The subsequent patch just converts this whole mess to flushing the entire descriptor , which is much more sane approach to take.
Best regards,
Marek Vasut
PATCH 4/51 net: dwc: Make the cache handling less cryptic
In reply to Marek VasutAdd a few new variables to make the cache handling less cryptic. Add a variable for DMA and DATA descriptor start and end, so the correctness of the code is easier to inspect.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Joe Hershberger <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- drivers/net/designware.c | 48 +++++++++++++++++++++++------------------------- 1 file changed, 23 insertions(+), 25 deletions(-)
drivers/net/designware.c +23 -25
@@ -279,19 +279,21 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)struct eth_dma_regs *dma_p = priv->dma_regs_p;u32 desc_num = priv->tx_currdescnum;struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; - +uint32_t desc_start = (uint32_t )desc_p; +uint32_t desc_end = desc_start + +roundup (sizeof (*desc_p),ARCH_DMA_MINALIGN ); +uint32_t data_start = (uint32_t )desc_p->dmamac_addr; +uint32_t data_end = data_start + +roundup (length,ARCH_DMA_MINALIGN );/* * Strictly we only need to invalidate the "txrx_status" field * for the following check, but on some platforms we cannot -* invalidate only 4 bytes, so roundup to -* ARCH_DMA_MINALIGN. This is safe because the individual -* descriptors in the array are each aligned to -* ARCH_DMA_MINALIGN. +* invalidate only 4 bytes, so we flush the entire descriptor, +* which is 16 bytes in total. This is safe because the +* individual descriptors in the array are each aligned to +* ARCH_DMA_MINALIGN and padded appropriately. */ -invalidate_dcache_range ( - (unsigned long )desc_p, - (unsigned long )desc_p + -roundup (sizeof (desc_p->txrx_status),ARCH_DMA_MINALIGN )); +invalidate_dcache_range (desc_start, desc_end);/* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status &DESC_TXSTS_OWNBYDMA ) {
@@ -299,12 +301,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)return -1 ; } -memcpy ((void *)desc_p->dmamac_addr, packet, length); +memcpy (desc_p->dmamac_addr, packet, length);/* Flush data to be sent */ -flush_dcache_range ((unsigned long )desc_p->dmamac_addr, - (unsigned long )desc_p->dmamac_addr + -roundup (length,ARCH_DMA_MINALIGN )); +flush_dcache_range (data_start, data_end);#if defined(CONFIG_DW_ALTDESCRIPTOR ) desc_p->txrx_status |=DESC_TXSTS_TXFIRST |DESC_TXSTS_TXLAST ;
@@ -322,8 +322,7 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)#endif /* Flush modified buffer descriptor */ -flush_dcache_range ((unsigned long )desc_p, - (unsigned long )desc_p +sizeof (struct dmamacdescr )); +flush_dcache_range (desc_start, desc_end);/* Test the wrap-around condition. */ if (++desc_num >=CONFIG_TX_DESCR_NUM )
@@ -343,11 +342,14 @@ static int dw_eth_recv(struct eth_device *dev)u32 status, desc_num = priv->rx_currdescnum;struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];int length =0 ; +uint32_t desc_start = (uint32_t )desc_p; +uint32_t desc_end = desc_start + +roundup (sizeof (*desc_p),ARCH_DMA_MINALIGN ); +uint32_t data_start = (uint32_t )desc_p->dmamac_addr; +uint32_t data_end;/* Invalidate entire buffer descriptor */ -invalidate_dcache_range ((unsigned long )desc_p, - (unsigned long )desc_p + -sizeof (struct dmamacdescr )); +invalidate_dcache_range (desc_start, desc_end); status = desc_p->txrx_status;
@@ -358,9 +360,8 @@ static int dw_eth_recv(struct eth_device *dev)DESC_RXSTS_FRMLENSHFT ;/* Invalidate received data */ -invalidate_dcache_range ((unsigned long )desc_p->dmamac_addr, - (unsigned long )desc_p->dmamac_addr + -roundup (length,ARCH_DMA_MINALIGN )); + data_end = data_start +roundup (length,ARCH_DMA_MINALIGN ); +invalidate_dcache_range (data_start, data_end);NetReceive (desc_p->dmamac_addr, length);
@@ -371,10 +372,7 @@ static int dw_eth_recv(struct eth_device *dev) desc_p->txrx_status |=DESC_RXSTS_OWNBYDMA ;/* Flush only status field - others weren't changed */ -flush_dcache_range ((unsigned long )&desc_p->txrx_status, - (unsigned long )&desc_p->txrx_status + -roundup (sizeof (desc_p->txrx_status), -ARCH_DMA_MINALIGN )); +flush_dcache_range (desc_start, desc_end);/* Test the wrap-around condition. */ if (++desc_num >=CONFIG_RX_DESCR_NUM )
Signature · 1 line
2.0.0
PATCH 4/51 net: dwc: Make the cache handling less cryptic
Quoted 109 lines · marex at denx.de
Add a few new variables to make the cache handling less cryptic. Add a variable for DMA and DATA descriptor start and end, so the correctness of the code is easier to inspect.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Cc Joe Hershberger <[email protected]>Acked-by Pavel Machek <[email protected]>--- drivers/net/designware.c | 48 +++++++++++++++++++++++------------------------- 1 file changed, 23 insertions(+), 25 deletions(-)drivers/net/designware.c +22
-21@@ -279,19 +279,21 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)struct eth_dma_regs *dma_p = priv->dma_regs_p;u32 desc_num = priv->tx_currdescnum;struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; - +uint32_t desc_start = (uint32_t )desc_p; +uint32_t desc_end = desc_start + +roundup (sizeof (*desc_p),ARCH_DMA_MINALIGN ); +uint32_t data_start = (uint32_t )desc_p->dmamac_addr; +uint32_t data_end = data_start + +roundup (length,ARCH_DMA_MINALIGN );/* * Strictly we only need to invalidate the "txrx_status" field * for the following check, but on some platforms we cannot -* invalidate only 4 bytes, so roundup to -* ARCH_DMA_MINALIGN. This is safe because the individual -* descriptors in the array are each aligned to -* ARCH_DMA_MINALIGN. +* invalidate only 4 bytes, so we flush the entire descriptor, +* which is 16 bytes in total. This is safe because the +* individual descriptors in the array are each aligned to +* ARCH_DMA_MINALIGN and padded appropriately. */ -invalidate_dcache_range ( - (unsigned long )desc_p, - (unsigned long )desc_p + -roundup (sizeof (desc_p->txrx_status),ARCH_DMA_MINALIGN )); +invalidate_dcache_range (desc_start, desc_end);/* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status &DESC_TXSTS_OWNBYDMA ) {@@ -299,12 +301,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)return -1 ; } -memcpy ((void *)desc_p->dmamac_addr, packet, length); +memcpy (desc_p->dmamac_addr, packet, length);/* Flush data to be sent */ -flush_dcache_range ((unsigned long )desc_p->dmamac_addr, - (unsigned long )desc_p->dmamac_addr + -roundup (length,ARCH_DMA_MINALIGN )); +flush_dcache_range (data_start, data_end);#if defined(CONFIG_DW_ALTDESCRIPTOR ) desc_p->txrx_status |=DESC_TXSTS_TXFIRST |DESC_TXSTS_TXLAST ;@@ -322,8 +322,7 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)#endif /* Flush modified buffer descriptor */ -flush_dcache_range ((unsigned long )desc_p, - (unsigned long )desc_p +sizeof (struct dmamacdescr )); +flush_dcache_range (desc_start, desc_end);/* Test the wrap-around condition. */ if (++desc_num >=CONFIG_TX_DESCR_NUM )@@ -343,11 +342,14 @@ static int dw_eth_recv(struct eth_device *dev)u32 status, desc_num = priv->rx_currdescnum;struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];int length =0 ; +uint32_t desc_start = (uint32_t )desc_p; +uint32_t desc_end = desc_start + +roundup (sizeof (*desc_p),ARCH_DMA_MINALIGN ); +uint32_t data_start = (uint32_t )desc_p->dmamac_addr; +uint32_t data_end;/* Invalidate entire buffer descriptor */ -invalidate_dcache_range ((unsigned long )desc_p, - (unsigned long )desc_p + -sizeof (struct dmamacdescr )); +invalidate_dcache_range (desc_start, desc_end); status = desc_p->txrx_status;@@ -358,9 +360,8 @@ static int dw_eth_recv(struct eth_device *dev)DESC_RXSTS_FRMLENSHFT ;/* Invalidate received data */ -invalidate_dcache_range ((unsigned long )desc_p->dmamac_addr, - (unsigned long )desc_p->dmamac_addr + -roundup (length,ARCH_DMA_MINALIGN )); + data_end = data_start +roundup (length,ARCH_DMA_MINALIGN ); +invalidate_dcache_range (data_start, data_end);NetReceive (desc_p->dmamac_addr, length);@@ -371,10 +372,7 @@ static int dw_eth_recv(struct eth_device *dev) desc_p->txrx_status |=DESC_RXSTS_OWNBYDMA ;
drivers/net/designware.c static int dw_eth_recv(struct eth_device *dev) · line 378
Quoted 10 lines
drivers/net/designware.c +1
-4/* Flush only status field - others weren't changed */ -flush_dcache_range ((unsigned long )&desc_p->txrx_status, - (unsigned long )&desc_p->txrx_status + -roundup (sizeof (desc_p->txrx_status), -ARCH_DMA_MINALIGN )); +flush_dcache_range (desc_start, desc_end);/* Test the wrap-around condition. */ if (++desc_num >=CONFIG_RX_DESCR_NUM )
Acked-by Chin Liang See <[email protected]>
PATCH 5/51 mmc: dw_mmc: cleanups
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
The dw_mmc driver was responding to errors with debug(). Change that to prinf()/puts() respectively so that any errors are immediately obvious. Also adjust english in comments.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Pantelis Antoniou <[email protected]>
--- drivers/mmc/dw_mmc.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-)
drivers/mmc/dw_mmc.c +22 -12
@@ -119,7 +119,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,while (dwmci_readl (host,DWMCI_STATUS ) &DWMCI_BUSY ) {if (get_timer (start) > timeout) { -printf ("Timeout on data busy\n" ); +printf ("%s: Timeout on data busy\n" , __func__);return TIMEOUT ; } }
@@ -177,14 +177,24 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } } -if (i == retry) +if (i == retry) { +printf ("%s: Timeout.\n" , __func__);return TIMEOUT ; + }if (mask &DWMCI_INTMSK_RTO ) { -debug ("Response Timeout..\n" ); +/* +* Timeout here is not necessarily fatal. (e)MMC cards +* will splat here when they receive CMD55 as they do +* not support this command and that is exactly the way +* to tell them apart from SD cards. Thus, this output +* below shall be debug(). eMMC cards also do not favor +* CMD8, please keep that in mind. +*/ +debug ("%s: Response Timeout.\n" , __func__);return TIMEOUT ; }else if (mask &DWMCI_INTMSK_RE ) { -debug ("Response Error..\n" ); +printf ("%s: Response Error.\n" , __func__);return -1 ; }
@@ -204,7 +214,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,do { mask =dwmci_readl (host,DWMCI_RINTSTS );if (mask & (DWMCI_DATA_ERR |DWMCI_DATA_TOUT )) { -debug ("DATA ERROR!\n" ); +printf ("%s: DATA ERROR!\n" , __func__);return -1 ; } }while (!(mask &DWMCI_INTMSK_DTO ));
@@ -232,16 +242,16 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)if ((freq == host->clock) || (freq ==0 ))return 0 ;/* -* If host->get_mmc_clk didn't define, +* If host->get_mmc_clk isn't defined, * then assume that host->bus_hz is source clock value. -* host->bus_hz should be set from user. +* host->bus_hz should be set by user. */ if (host->get_mmc_clk) sclk = host->get_mmc_clk (host);else if (host->bus_hz) sclk = host->bus_hz;else { -printf ("Didn't get source clock value..\n" ); +printf ("%s: Didn't get source clock value.\n" , __func__);return -EINVAL ; }
@@ -260,7 +270,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)do { status =dwmci_readl (host,DWMCI_CMD );if (timeout-- <0 ) { -printf ("TIMEOUT error!!\n" ); +printf ("%s: Timeout!\n" , __func__);return -ETIMEDOUT ; } }while (status &DWMCI_CMD_START );
@@ -275,7 +285,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)do { status =dwmci_readl (host,DWMCI_CMD );if (timeout-- <0 ) { -printf ("TIMEOUT error!!\n" ); +printf ("%s: Timeout!\n" , __func__);return -ETIMEDOUT ; } }while (status &DWMCI_CMD_START );
@@ -290,7 +300,7 @@ static void dwmci_set_ios(struct mmc *mmc)struct dwmci_host *host = (struct dwmci_host *)mmc->priv;u32 ctype, regs; -debug ("Buswidth = %d, clock: %d\n" ,mmc->bus_width, mmc->clock); +debug ("Buswidth = %d, clock: %d\n" , mmc->bus_width, mmc->clock);dwmci_setup_bus (host, mmc->clock);switch (mmc->bus_width) {
@@ -329,7 +339,7 @@ static int dwmci_init(struct mmc *mmc)dwmci_writel (host,DWMCI_PWREN ,1 );if (!dwmci_wait_reset (host,DWMCI_RESET_ALL )) { -debug ("%s[%d] Fail-reset!!\n" ,__func__,__LINE__); +printf ("%s[%d] Fail-reset!!\n" , __func__, __LINE__);return -1 ; }
Signature · 1 line
2.0.0
PATCH 5/51 mmc: dw_mmc: cleanups
Quoted 117 lines · marex at denx.de
From: Pavel Machek <[email protected]>
The
dw_mmcdriver was responding to errors withdebug(). Change that to prinf()/puts() respectively so that any errors are immediately obvious. Also adjust english in comments.Signed-off-by Pavel Machek <[email protected]>Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Cc Pantelis Antoniou <[email protected]>--- drivers/mmc/dw_mmc.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-)drivers/mmc/dw_mmc.c +21
-11@@ -119,7 +119,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,while (dwmci_readl (host,DWMCI_STATUS ) &DWMCI_BUSY ) {if (get_timer (start) > timeout) { -printf ("Timeout on data busy\n" ); +printf ("%s: Timeout on data busy\n" , __func__);return TIMEOUT ; } }@@ -177,14 +177,24 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } } -if (i == retry) +if (i == retry) { +printf ("%s: Timeout.\n" , __func__);return TIMEOUT ; + }if (mask &DWMCI_INTMSK_RTO ) { -debug ("Response Timeout..\n" ); +/* +* Timeout here is not necessarily fatal. (e)MMC cards +* will splat here when they receive CMD55 as they do +* not support this command and that is exactly the way +* to tell them apart from SD cards. Thus, this output +* below shall be debug(). eMMC cards also do not favor +* CMD8, please keep that in mind. +*/ +debug ("%s: Response Timeout.\n" , __func__);return TIMEOUT ; }else if (mask &DWMCI_INTMSK_RE ) { -debug ("Response Error..\n" ); +printf ("%s: Response Error.\n" , __func__);return -1 ; }@@ -204,7 +214,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,do { mask =dwmci_readl (host,DWMCI_RINTSTS );if (mask & (DWMCI_DATA_ERR |DWMCI_DATA_TOUT )) { -debug ("DATA ERROR!\n" ); +printf ("%s: DATA ERROR!\n" , __func__);return -1 ; } }while (!(mask &DWMCI_INTMSK_DTO ));@@ -232,16 +242,16 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)if ((freq == host->clock) || (freq ==0 ))return 0 ;/* -* If host->get_mmc_clk didn't define, +* If host->get_mmc_clk isn't defined, * then assume that host->bus_hz is source clock value. -* host->bus_hz should be set from user. +* host->bus_hz should be set by user. */ if (host->get_mmc_clk) sclk = host->get_mmc_clk (host);else if (host->bus_hz) sclk = host->bus_hz;else { -printf ("Didn't get source clock value..\n" ); +printf ("%s: Didn't get source clock value.\n" , __func__);return -EINVAL ; }@@ -260,7 +270,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)do { status =dwmci_readl (host,DWMCI_CMD );if (timeout-- <0 ) { -printf ("TIMEOUT error!!\n" ); +printf ("%s: Timeout!\n" , __func__);return -ETIMEDOUT ; } }while (status &DWMCI_CMD_START );@@ -275,7 +285,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)do { status =dwmci_readl (host,DWMCI_CMD );if (timeout-- <0 ) { -printf ("TIMEOUT error!!\n" ); +printf ("%s: Timeout!\n" , __func__);return -ETIMEDOUT ; } }while (status &DWMCI_CMD_START );@@ -290,7 +300,7 @@ static void dwmci_set_ios(struct mmc *mmc)struct dwmci_host *host = (struct dwmci_host *)mmc->priv;u32 ctype, regs; -debug ("Buswidth = %d, clock: %d\n" ,mmc->bus_width, mmc->clock); +debug ("Buswidth = %d, clock: %d\n" , mmc->bus_width, mmc->clock);dwmci_setup_bus (host, mmc->clock);switch (mmc->bus_width) {
drivers/mmc/dw_mmc.c static int dwmci_init(struct mmc *mmc) · line 345
Quoted 8 lines
drivers/mmc/dw_mmc.c +1
-1@@ -329,7 +339,7 @@ static int dwmci_init(struct mmc *mmc)dwmci_writel (host,DWMCI_PWREN ,1 );if (!dwmci_wait_reset (host,DWMCI_RESET_ALL )) { -debug ("%s[%d] Fail-reset!!\n" ,__func__,__LINE__); +printf ("%s[%d] Fail-reset!!\n" , __func__, __LINE__);return -1 ; }
Acked-by Chin Liang See <[email protected]>
PATCH 6/51 mmc: dw_mmc: Fix cache alignment issue
In reply to Marek VasutThe DMA descriptors used by the DW MMC block must be aligned to cacheline size, otherwise we are unable to properly flush/inval cache over them and we get data corruption.
The reason I chose this approach of expanding the structure is because the driver allocates the descriptors in bulk. This approach does waste space by inserting slop inbetween the descriptors, but it makes access to the descriptors easy as the compiler does know the real size of the structure. It also makes cache operations easy, since the size of the structure is cache aligned and the structure start address is as well.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Pantelis Antoniou <[email protected]>
--- include/dwmmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
include/dwmmc.h +1 -1
@@ -157,7 +157,7 @@ struct dwmci_idmac {u32 cnt;u32 addr;u32 next_addr; -}; +}__aligned(ARCH_DMA_MINALIGN) ;static inline void dwmci_writel (struct dwmci_host *host,int reg,u32 val) {
Signature · 1 line
2.0.0
PATCH 6/51 mmc: dw_mmc: Fix cache alignment issue
Hi Marek,
Quoted 28 lines · marex at denx.de
The DMA descriptors used by the DW MMC block must be aligned to cacheline size, otherwise we are unable to properly flush/inval cache over them and we get data corruption.
The reason I chose this approach of expanding the structure is because the driver allocates the descriptors in bulk. This approach does waste space by inserting slop inbetween the descriptors, but it makes access to the descriptors easy as the compiler does know the real size of the structure. It also makes cache operations easy, since the size of the structure is cache aligned and the structure start address is as well.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Cc Pantelis Antoniou <[email protected]>--- include/dwmmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)include/dwmmc.h +0
-0
include/dwmmc.h struct dwmci_idmac { · line 161
Quoted 6 lines
include/dwmmc.h +1
-1@@ -157,7 +157,7 @@ struct dwmci_idmac {u32 cnt;u32 addr;u32 next_addr; -}; +}__aligned(ARCH_DMA_MINALIGN) ;
Wonder the ALLOC_CACHE_ALIGN_BUFFER within function dwmci_send_cmd at drivers/mmc/dw_mmc.c already take care this?
Thanks
Chin Liang
Quoted 2 lines
include/dwmmc.h +0
-0static inline void dwmci_writel (struct dwmci_host *host,int reg,u32 val) {
PATCH 6/51 mmc: dw_mmc: Fix cache alignment issue
Quoted 37 lines · Chin Liang See
Hi Marek,
Quoted 34 lines · marex at denx.de
The DMA descriptors used by the DW MMC block must be aligned to cacheline size, otherwise we are unable to properly flush/inval cache over them and we get data corruption.
The reason I chose this approach of expanding the structure is because the driver allocates the descriptors in bulk. This approach does waste space by inserting slop inbetween the descriptors, but it makes access to the descriptors easy as the compiler does know the real size of the structure. It also makes cache operations easy, since the size of the structure is cache aligned and the structure start address is as well.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Cc Pantelis Antoniou <[email protected]>---
include/dwmmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)include/dwmmc.h +0
-0@@ -157,7 +157,7 @@ struct dwmci_idmac {u32 cnt;u32 addr;u32 next_addr;
Quoted 5 lines
include/dwmmc.h struct dwmci_idmac { · line 160
Quoted 2 lines
include/dwmmc.h +1
-1-}; +}__aligned(ARCH_DMA_MINALIGN) ;Wonder the
ALLOC_CACHE_ALIGN_BUFFERwithin functiondwmci_send_cmdatdrivers/mmc/dw_mmc.calready take care this?
This won't help, since you want to do cache ops only on one descriptor at a time. The ALLOC_CACHE_ALIGN_BUFFER will allocate an array of the descriptors with aligned start address and end address, but won't insert the necessary padding inbetween the elements so that each descriptor starts at the begining of a cacheline. So you can do:
flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
where $desc is a pointer to the n-th element in the array of descriptors.
I explained in the commit message why I didn't go for a scheme where the descriptors would be tightly packed one after the other -- it is possible to do it, but the already obscure cache handling mechanism would be even more complex that way and thus more bug-prone.
Best regards,
Marek Vasut
PATCH 7/51 tools: socfpga: Add socfpga preloader signing to mkimage
In reply to Marek VasutFrom: Charles Manning <[email protected]>
Like many platforms, the Altera socfpga platform requires that the preloader be "signed" in a certain way or the built-in boot ROM will not boot the code.
This change automatically creates an appropriately signed preloader from an SPL image.
The signed image includes a CRC which must, of course, be generated with a CRC generator that the SoCFPGA boot ROM agrees with otherwise the boot ROM will reject the image.
Unfortunately the CRC used in this boot ROM is not the same as the Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a CRC but is more correctly described as a checksum.
Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.
Signed-off-by Charles Manning <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- common/image.c | 1 + include/image.h | 1 + tools/Makefile | 1 + tools/imagetool.c | 2 + tools/imagetool.h | 1 + tools/socfpgaimage.c | 255 +++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 261 insertions(+) create mode 100644 tools/socfpgaimage.c
common/image.c +1 -0
@@ -138,6 +138,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, + { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",}, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",},
include/image.h +1 -0
@@ -232,6 +232,7 @@ struct lmb;#define IH_TYPE_MXSIMAGE 16/* Freescale MXSBoot Image */ #define IH_TYPE_GPIMAGE 17/* TI Keystone GPHeader Image */ #define IH_TYPE_ATMELIMAGE 18/* ATMEL ROM bootable Image */ +#define IH_TYPE_SOCFPGAIMAGE 19/* Altera SOCFPGA Preloader */ /* * Compression Types
tools/Makefile +1 -0
@@ -87,6 +87,7 @@ dumpimage-mkimage-objs := aisimage.o \ os_support.o \ pblimage.o \ pbl_crc32.o \ + socfpgaimage.o \ lib/sha1.o \ lib/sha256.o \ ublimage.o \
tools/imagetool.c +2 -0
@@ -47,6 +47,8 @@ void register_image_tool(imagetool_register_t image_register)init_ubl_image_type ();/* Init Davinci AIS support */ init_ais_image_type (); +/* Init Altera SOCFPGA support */ +init_socfpga_image_type ();/* Init TI Keystone boot image generation/list support */ init_gpimage_type (); }
tools/imagetool.h +1 -0
@@ -168,6 +168,7 @@ void init_mxs_image_type(void);void init_fit_image_type (void );void init_ubl_image_type (void );void init_omap_image_type (void ); +void init_socfpga_image_type (void );void init_gpimage_type (void );void pbl_load_uboot (int fd,struct image_tool_params *mparams);
tools/socfpgaimage.c new file +255 -0
255 lines not on this page · raw message
Signature · 1 line
2.0.0
PATCH 7/51 tools: socfpga: Add socfpga preloader signing to mkimage
Hi Charles,
Quoted 128 lines · marex at denx.de
From: Charles Manning <[email protected]>
Like many platforms, the Altera socfpga platform requires that the preloader be "signed" in a certain way or the built-in boot ROM will not boot the code.
This change automatically creates an appropriately signed preloader from an SPL image.
The signed image includes a CRC which must, of course, be generated with a CRC generator that the SoCFPGA boot ROM agrees with otherwise the boot ROM will reject the image.
Unfortunately the CRC used in this boot ROM is not the same as the Adler CRC in
lib/crc32.c. Indeed the Adler code is not technically a CRC but is more correctly described as a checksum.Thus, the appropriate CRC generator is added to
lib/ascrc32_alt.c.Signed-off-by Charles Manning <[email protected]>Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>--- common/image.c | 1 + include/image.h | 1 + tools/Makefile | 1 + tools/imagetool.c | 2 + tools/imagetool.h | 1 + tools/socfpgaimage.c | 255 +++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 261 insertions(+) create mode 100644 tools/socfpgaimage.ccommon/image.c +1
-0@@ -138,6 +138,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, + { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",}, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",},include/image.h +1
-0@@ -232,6 +232,7 @@ struct lmb;#define IH_TYPE_MXSIMAGE 16/* Freescale MXSBoot Image */ #define IH_TYPE_GPIMAGE 17/* TI Keystone GPHeader Image */ #define IH_TYPE_ATMELIMAGE 18/* ATMEL ROM bootable Image */ +#define IH_TYPE_SOCFPGAIMAGE 19/* Altera SOCFPGA Preloader */ /* * Compression Types tools/Makefile +1
-0@@ -87,6 +87,7 @@ dumpimage-mkimage-objs := aisimage.o \ os_support.o \ pblimage.o \ pbl_crc32.o \ + socfpgaimage.o \ lib/sha1.o \ lib/sha256.o \ ublimage.o \tools/imagetool.c +2
-0@@ -47,6 +47,8 @@ void register_image_tool(imagetool_register_t image_register)init_ubl_image_type ();/* Init Davinci AIS support */ init_ais_image_type (); +/* Init Altera SOCFPGA support */ +init_socfpga_image_type ();/* Init TI Keystone boot image generation/list support */ init_gpimage_type (); }tools/imagetool.h +1
-0@@ -168,6 +168,7 @@ void init_mxs_image_type(void);void init_fit_image_type (void );void init_ubl_image_type (void );void init_omap_image_type (void ); +void init_socfpga_image_type (void );void init_gpimage_type (void );void pbl_load_uboot (int fd,struct image_tool_params *mparams);tools/socfpgaimage.c new file +24
-0@@ -0,0 +1,255 @@ +/* +* Copyright (C) 2014 Charles Manning <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +* +* Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf +* Note this doc is not entirely accurate. Of particular interest to us is the +* "header" length field being in U32s and not bytes. +* +* "Header" is a structure of the following format. +* this is positioned at 0x40. +* +* Endian is LSB. +* +* Offset Length Usage +* ----------------------- +* 0x40 4 Validation word 0x31305341 +* 0x44 1 Version (whatever, zero is fine) +* 0x45 1 Flags (unused, zero is fine) +* 0x46 2 Length (in units of u32, including the end checksum). +* 0x48 2 Zero +* 0x4A 2 Checksum over the header. NB Not CRC32 +* +* At the end of the code we have a 32-bit CRC checksum over whole binary
tools/socfpgaimage.c line 34
Quoted 10 lines
tools/socfpgaimage.c new file +10
-0+* excluding the CRC. +* +* Note that the CRC used here is **not** the zlib/Adler crc32. It is the +* CRC-32 used in bzip2, ethernet and elsewhere. +* +* The image is padded out to 64k, because that is what is +* typically used to write the image to the boot medium. +*/ + +#include "pbl_crc32.h"
Seems I cannot find this file
tools/socfpgaimage.c line 39
Quoted 5 lines
tools/socfpgaimage.c new file +5
-0+#include "imagetool.h" +#include <image.h> + +#define HEADER_OFFSET 0x40 +#define HEADER_SIZE 0xC
Unused
Quoted 36 lines
tools/socfpgaimage.c new file +36
-0+#define VALIDATION_WORD 0x31305341 +#define PADDED_SIZE 0x10000 + +/* To allow for adding CRC, the max input size is a bit smaller. */ +#define MAX_INPUT_SIZE (PADDED_SIZE - sizeof(uint32_t)) + +static uint8_t buffer[PADDED_SIZE ]; + +static struct { +uint32_t validation; +uint8_t version; +uint8_t flags; +uint16_t length_u32; +uint16_t zero; +uint16_t checksum; +} header; + +/* +* The header checksum is just a very simple checksum over +* the header area. +* There is still a crc32 over the whole lot. +*/ +static uint16_t hdr_checksum (const uint8_t *buf,int len) +{ +uint16_t ret =0 ; +int i; + +for (i =0 ; i < len; i++) { + ret += (((uint16_t ) *buf) &0xff ); + buf++; + } +return ret; +} + + +static void build_header(uint8_t *buf,
tools/socfpgaimage.c line 85
Quoted 10 lines
tools/socfpgaimage.c new file +10
-0+uint8_t version, + uint8_t flags, + uint16_t length_bytes) +{ + header.validation = htole32(VALIDATION_WORD); + header.version = version; + header.flags = flags; + header.length_u32 =htole16 (length_bytes/4 ); + header.zero =0 ; + header.checksum =htole16 (hdr_checksum ((const uint8_t *)&header,10 ));
Seems 10 is a magic number here.
Suggest to use sizeof(header) - sizeof(header.checksum)
Quoted 6 lines
tools/socfpgaimage.c new file +6
-0+ +memcpy (buf, &header,sizeof (header)); +} + +/* +* Perform a rudimentary verification of header and return
tools/socfpgaimage.c line 101
Quoted 10 lines
tools/socfpgaimage.c new file +10
-0+* size of image. +*/ +static int verify_header (const uint8_t *buf) +{ +memcpy (&header, buf,sizeof (header)); + +if (le32toh (header.validation) !=VALIDATION_WORD ) +return -1 ; +if (le16toh (header.checksum) != +hdr_checksum ((const uint8_t *)&header,10 ))
Ditto
Quoted 11 lines
tools/socfpgaimage.c new file +11
-0+return -1 ; + +return le16toh (header.length_u32) *4 ; +} + +/* Sign the buffer and return the signed buffer size */ +static int sign_buffer (uint8_t *buf, +uint8_t version,uint8_t flags, +int len,int pad_64k) +{ +uint32_t calc_crc;
tools/socfpgaimage.c line 122
Quoted 10 lines
tools/socfpgaimage.c new file +10
-0+ +/* Align the length up */ + len = (len +3 ) & (~3 ); + +/* Build header, adding 4 bytes to length to hold the CRC32. */ +build_header (buf +HEADER_OFFSET , version, flags, len +4 ); + +/* Calculate and apply the CRC */ + calc_crc = ~pbl_crc32 (0 , (char *)buf, len); +
For this, we can reuse the lib/bzlib_private.h
/* Calculate and apply the CRC */
BZ_INITIALISE_CRC(calc_crc);
while (len--) {
BZ_UPDATE_CRC(calc_crc, *buf);
buf++;
}
calc_crc ^= ~0;Quoted 10 lines
tools/socfpgaimage.c new file +10
-0+ *((uint32_t *)(buf + len)) =htole32 (calc_crc); + +if (!pad_64k) +return len +4 ; + +return PADDED_SIZE ; +} + +/* Verify that the buffer looks sane */ +static int verify_buffer (const uint8_t *buf)
tools/socfpgaimage.c line 142
Quoted 10 lines
tools/socfpgaimage.c new file +10
-0+{ +int len;/* Including 32bit CRC */ +uint32_t calc_crc; +uint32_t buf_crc; + + len =verify_header (buf +HEADER_OFFSET ); +if (len <0 ) +return -1 ; +if (len <HEADER_OFFSET || len >PADDED_SIZE ) +return -1 ;
Suggest to have some printout to indicate failure type
tools/socfpgaimage.c line 151
Quoted 9 lines
tools/socfpgaimage.c new file +9
-0+ +/* +* Adjust length to the base of the CRC. +* Check the CRC. +*/ + len -=4 ; + + calc_crc = ~pbl_crc32 (0 , (const char *)buf, len); +
Ditto
tools/socfpgaimage.c line 156
Quoted 5 lines
tools/socfpgaimage.c new file +5
-0+ buf_crc =le32toh (*((uint32_t *)(buf + len))); + +if (buf_crc != calc_crc) +return -1 ; +
Suggest to have some printout to indicate failure type
Quoted 99 lines
tools/socfpgaimage.c new file +99
-0+return 0 ; +} + +/* mkimage glue functions */ +static int socfpgaimage_verify_header (unsigned char *ptr,int image_size, +struct image_tool_params *params) +{ +if (image_size !=PADDED_SIZE ) +return -1 ; + +return verify_buffer (ptr); +} + +static void socfpgaimage_print_header (const void *ptr) +{ +if (verify_buffer (ptr) ==0 ) +printf ("Looks like a sane SOCFPGA preloader\n" ); +else +printf ("Not a sane SOCFPGA preloader\n" ); +} + +static int socfpgaimage_check_params (struct image_tool_params *params) +{ +/* Not sure if we should be accepting fflags */ +return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} + +static int socfpgaimage_check_image_types (uint8_t type) +{ +if (type ==IH_TYPE_SOCFPGAIMAGE ) +return EXIT_SUCCESS ; +return EXIT_FAILURE ; +} + +/* +* To work in with the mkimage framework, we do some ugly stuff... +* +* First, socfpgaimage_vrec_header() is called. +* We prepend a fake header big enough to make the file PADDED_SIZE. +* This gives us enough space to do what we want later. +* +* Next, socfpgaimage_set_header() is called. +* We fix up the buffer by moving the image to the start of the buffer. +* We now have some room to do what we need (add CRC and padding). +*/ + +static int data_size; +#define FAKE_HEADER_SIZE (PADDED_SIZE - data_size) + +static int socfpgaimage_vrec_header (struct image_tool_params *params, +struct image_type_params *tparams) +{ +struct stat sbuf; + +if (params->datafile && +stat (params->datafile, &sbuf) ==0 && + sbuf.st_size <=MAX_INPUT_SIZE ) { + data_size = sbuf.st_size; + tparams->header_size =FAKE_HEADER_SIZE ; + } +return 0 ; +} + +static void socfpgaimage_set_header (void *ptr,struct stat *sbuf,int ifd, +struct image_tool_params *params) +{ +uint8_t *buf = (uint8_t *)ptr; + +/* +* This function is called after vrec_header() has been called. +* At this stage we have the FAKE_HEADER_SIZE dummy bytes followed by +* data_size image bytes. Total = PADDED_SIZE. +* We need to fix the buffer by moving the image bytes back to +* the beginning of the buffer, then actually do the signing stuff... +*/ +memmove (buf, buf +FAKE_HEADER_SIZE , data_size); +memset (buf + data_size,0 ,FAKE_HEADER_SIZE ); + +sign_buffer (buf,0 ,0 , data_size,0 ); +} + +static struct image_type_params socfpgaimage_params = { + .name ="Altera SOCFPGA preloader support" , + .vrec_header = socfpgaimage_vrec_header, + .header_size =0 ,/* This will be modified by vrec_header() */ + .hdr = (void *)buffer, + .check_image_type = socfpgaimage_check_image_types, + .verify_header = socfpgaimage_verify_header, + .print_header = socfpgaimage_print_header, + .set_header = socfpgaimage_set_header, + .check_params = socfpgaimage_check_params, +}; + +void init_socfpga_image_type (void ) +{ +register_image_type (&socfpgaimage_params); +}
PATCH 7/51 tools: socfpga: Add socfpga preloader signing to mkimage
On Wednesday, October 01, 2014 at 12:10:47 PM, Chin Liang See wrote:
[...]
Quoted 7 lines
tools/socfpgaimage.c line 34
Quoted 5 lines
+ * The image is padded out to 64k, because that is what is
+ * typically used to write the image to the boot medium.
+ */tools/socfpgaimage.c new file +2
-0+ +#include "pbl_crc32.h" Seems I cannot find this file
See tools/pbl_crc32.h
[...]
Quoted 6 lines
Quoted 6 lines
tools/socfpgaimage.c new file +6
-0+static void build_header (uint8_t *buf, +uint8_t version, +uint8_t flags, +uint16_t length_bytes) +{ + header.validation =htole32 (VALIDATION_WORD );
Quoted 8 lines
tools/socfpgaimage.c line 85
Quoted 5 lines
tools/socfpgaimage.c new file +5
-0+ header.version = version; + header.flags = flags; + header.length_u32 =htole16 (length_bytes/4 ); + header.zero =0 ; + header.checksum =htole16 (hdr_checksum ((const uint8_t *)&header,10 ));Seems 10 is a magic number here.
Suggest to use sizeof(header) - sizeof(header.checksum)
Even better, I can pass the whole *header into hdr_checksum and contain all that size computation in there. Your formula included.
[...]
Quoted 19 lines
Quoted 6 lines
tools/socfpgaimage.c new file +6
-0+/* Sign the buffer and return the signed buffer size */ +static int sign_buffer (uint8_t *buf, +uint8_t version,uint8_t flags, +int len,int pad_64k) +{ +uint32_t calc_crc;tools/socfpgaimage.c line 122
Quoted 10 lines
tools/socfpgaimage.c new file +10
-0+ +/* Align the length up */ + len = (len +3 ) & (~3 ); + +/* Build header, adding 4 bytes to length to hold the CRC32. */ +build_header (buf +HEADER_OFFSET , version, flags, len +4 ); + +/* Calculate and apply the CRC */ + calc_crc = ~pbl_crc32 (0 , (char *)buf, len); +For this, we can reuse the
lib/bzlib_private.h
Quoted 7 lines
/* Calculate and apply the CRC */
BZ_INITIALISE_CRC(calc_crc);
while (len--) {
BZ_UPDATE_CRC(calc_crc, *buf);
buf++;
}
calc_crc ^= ~0;Do you mean I should replace the one function call with this whole block ?
[...]
The rest was addressed.
PATCH 8/51 arm: socfpga: Complete the list of base addresses
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Add base addresses for all subsystems as documented in the Cyclone V HPS documentation.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+)
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +40 -0
@@ -7,16 +7,56 @@#ifndef _SOCFPGA_BASE_ADDRS_H_#define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000#define SOCFPGA_UART0_ADDRESS 0xffc02000#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000#define SOCFPGA_EMAC0_ADDRESS 0xff700000#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000#endif /* _SOCFPGA_BASE_ADDRS_H_ */
Signature · 1 line
2.0.0
PATCH 8/51 arm: socfpga: Complete the list of base addresses
Quoted 68 lines · marex at denx.de
From: Pavel Machek <[email protected]>
Add base addresses for all subsystems as documented in the Cyclone V HPS documentation.
Signed-off-by Pavel Machek <[email protected]>Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>--- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+)arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +32
-0@@ -7,16 +7,56 @@#ifndef _SOCFPGA_BASE_ADDRS_H_#define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000#define SOCFPGA_UART0_ADDRESS 0xffc02000#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000#define SOCFPGA_EMAC0_ADDRESS 0xff700000#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h line 62
Quoted 10 lines
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +8
-0+#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000#endif /* _SOCFPGA_BASE_ADDRS_H_ */
Probably want to sort it out?
Acked-by Chin Liang See <[email protected]>
PATCH 8/51 arm: socfpga: Complete the list of base addresses
Quoted 15 lines · Chin Liang See
Quoted 14 lines · marex at denx.de
From: Pavel Machek <[email protected]>
Add base addresses for all subsystems as documented in the Cyclone V HPS documentation.
Signed-off-by Pavel Machek <[email protected]>Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>---
[...]
Quoted 2 lines
Probably want to sort it out?
Done in the next patch ;-)
Best regards,
Marek Vasut
PATCH 9/51 arm: socfpga: Clean up base address file
In reply to Marek VasutSort the list of functional block addresses and fix indentation. No functional change.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 102 ++++++++++----------- 1 file changed, 51 insertions(+), 51 deletions(-)
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +51 -51
@@ -7,56 +7,56 @@#ifndef _SOCFPGA_BASE_ADDRS_H_#define _SOCFPGA_BASE_ADDRS_H_ -#define SOCFPGA_SDMMC_ADDRESS 0xff704000 -#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 -#define SOCFPGA_L3REGS_ADDRESS 0xff800000 -#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc03000 -#define SOCFPGA_SDR_ADDRESS 0xffc20000 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 -#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 -#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 -#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 -#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 -#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 -#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 -#define SOCFPGA_EMAC0_ADDRESS 0xff700000 -#define SOCFPGA_EMAC1_ADDRESS 0xff702000 -#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 -#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 -#define SOCFPGA_STM_ADDRESS 0xfc000000 -#define SOCFPGA_DAP_ADDRESS 0xff000000 -#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 -#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 -#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 -#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 -#define SOCFPGA_QSPI_ADDRESS 0xff705000 -#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 -#define SOCFPGA_GPIO0_ADDRESS 0xff708000 -#define SOCFPGA_GPIO1_ADDRESS 0xff709000 -#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 -#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 -#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 -#define SOCFPGA_USB0_ADDRESS 0xffb00000 -#define SOCFPGA_USB1_ADDRESS 0xffb40000 -#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 -#define SOCFPGA_CAN0_ADDRESS 0xffc00000 -#define SOCFPGA_CAN1_ADDRESS 0xffc01000 -#define SOCFPGA_I2C0_ADDRESS 0xffc04000 -#define SOCFPGA_I2C1_ADDRESS 0xffc05000 -#define SOCFPGA_I2C2_ADDRESS 0xffc06000 -#define SOCFPGA_I2C3_ADDRESS 0xffc07000 -#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 -#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 -#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 -#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 -#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 -#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 -#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 -#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 -#define SOCFPGA_ROM_ADDRESS 0xfffd0000 -#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_EMAC0_ADDRESS 0xff700000 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000#endif /* _SOCFPGA_BASE_ADDRS_H_ */
Signature · 1 line
2.0.0
PATCH 9/51 arm: socfpga: Clean up base address file
Quoted 117 lines · marex at denx.de
Sort the list of functional block addresses and fix indentation. No functional change.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Acked-by Pavel Machek <[email protected]>--- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 102 ++++++++++----------- 1 file changed, 51 insertions(+), 51 deletions(-)arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +43
-51@@ -7,56 +7,56 @@#ifndef _SOCFPGA_BASE_ADDRS_H_#define _SOCFPGA_BASE_ADDRS_H_ -#define SOCFPGA_SDMMC_ADDRESS 0xff704000 -#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 -#define SOCFPGA_L3REGS_ADDRESS 0xff800000 -#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc03000 -#define SOCFPGA_SDR_ADDRESS 0xffc20000 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 -#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 -#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 -#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 -#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 -#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 -#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 -#define SOCFPGA_EMAC0_ADDRESS 0xff700000 -#define SOCFPGA_EMAC1_ADDRESS 0xff702000 -#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 -#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 -#define SOCFPGA_STM_ADDRESS 0xfc000000 -#define SOCFPGA_DAP_ADDRESS 0xff000000 -#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 -#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 -#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 -#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 -#define SOCFPGA_QSPI_ADDRESS 0xff705000 -#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 -#define SOCFPGA_GPIO0_ADDRESS 0xff708000 -#define SOCFPGA_GPIO1_ADDRESS 0xff709000 -#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 -#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 -#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 -#define SOCFPGA_USB0_ADDRESS 0xffb00000 -#define SOCFPGA_USB1_ADDRESS 0xffb40000 -#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 -#define SOCFPGA_CAN0_ADDRESS 0xffc00000 -#define SOCFPGA_CAN1_ADDRESS 0xffc01000 -#define SOCFPGA_I2C0_ADDRESS 0xffc04000 -#define SOCFPGA_I2C1_ADDRESS 0xffc05000 -#define SOCFPGA_I2C2_ADDRESS 0xffc06000 -#define SOCFPGA_I2C3_ADDRESS 0xffc07000 -#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 -#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 -#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 -#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 -#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 -#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 -#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 -#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 -#define SOCFPGA_ROM_ADDRESS 0xfffd0000 -#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_EMAC0_ADDRESS 0xff700000 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h line 62
Quoted 10 lines
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +8
-0+#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000#endif /* _SOCFPGA_BASE_ADDRS_H_ */
Acked-by Chin Liang See <[email protected]>
PATCH v2 10/51 arm: socfpga: Add watchdog disable for socfpga
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/misc.c | 10 ++++++++++ arch/arm/cpu/armv7/socfpga/reset_manager.c | 12 ++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 4 ++++ 3 files changed, 26 insertions(+)
V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
arch/arm/cpu/armv7/socfpga/misc.c +10 -0
@@ -8,6 +8,7 @@#include <asm/io.h> #include <miiphy.h> #include <netdev.h> +#include <asm/arch/reset_manager.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -38,6 +39,15 @@ int overwrite_console(void)int misc_init_r (void ) { +/* +* If the HW watchdog is NOT enabled, make sure it is not running, +* for example because it was enabled in the preloader. This might +* trigger a watchdog-triggered reboot of Linux kernel later. +*/ +#ifndef CONFIG_HW_WATCHDOG +socfpga_watchdog_reset (); +#endif +return 0 ; }
arch/arm/cpu/armv7/socfpga/reset_manager.c +12 -0
@@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR;static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS ; +/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */ +void socfpga_watchdog_reset (void ) +{ +/* assert reset for watchdog */ +setbits_le32 (&reset_manager_base->per_mod_reset, +1 <<RSTMGR_PERMODRST_L4WD0_LSB ); + +/* deassert watchdog from reset (watchdog in not running state) */ +clrbits_le32 (&reset_manager_base->per_mod_reset, +1 <<RSTMGR_PERMODRST_L4WD0_LSB ); +} +/* * Write the reset manager register to cause reset */
arch/arm/include/asm/arch-socfpga/reset_manager.h +4 -0
@@ -10,6 +10,8 @@void reset_cpu (ulong addr);void reset_deassert_peripherals_handoff (void ); +void socfpga_watchdog_reset (void ); +struct socfpga_reset_manager {u32 status;u32 ctrl;
@@ -27,4 +29,6 @@ struct socfpga_reset_manager {#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1#endif +#define RSTMGR_PERMODRST_L4WD0_LSB 6 +#endif /* _RESET_MANAGER_H_ */
Signature · 1 line
2.0.0
PATCH v2 10/51 arm: socfpga: Add watchdog disable for socfpga
Quoted 36 lines · marex at denx.de
From: Pavel Machek <[email protected]>
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by Pavel Machek <[email protected]>Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>--- arch/arm/cpu/armv7/socfpga/misc.c | 10 ++++++++++ arch/arm/cpu/armv7/socfpga/reset_manager.c | 12 ++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 4 ++++ 3 files changed, 26 insertions(+)V2: Move
RSTMGR_PERMODRST_L4WD0_LSBtoreset_manager.h
Reset watchdog only ifCONFIG_HW_WATCHDOGis undefined (the default)arch/arm/cpu/armv7/socfpga/misc.c +1
-0@@ -8,6 +8,7 @@#include <asm/io.h> #include <miiphy.h> #include <netdev.h> +#include <asm/arch/reset_manager.h> DECLARE_GLOBAL_DATA_PTR ;@@ -38,6 +39,15 @@ int overwrite_console(void)int misc_init_r (void )
arch/arm/cpu/armv7/socfpga/misc.c int overwrite_console(void) · line 50
Quoted 10 lines
arch/arm/cpu/armv7/socfpga/misc.c +9
-0{ +/* +* If the HW watchdog is NOT enabled, make sure it is not running, +* for example because it was enabled in the preloader. This might +* trigger a watchdog-triggered reboot of Linux kernel later. +*/ +#ifndef CONFIG_HW_WATCHDOG +socfpga_watchdog_reset (); +#endif +
misc_init_r happens at some time after U-Boot entry. Afraid the watchdog might trigger prior its disabled. Suggest to call socfpga_watchdog_reset earlier.
Thanks
Chin Liang
PATCH v2 10/51 arm: socfpga: Add watchdog disable for socfpga
On Wednesday, October 01, 2014 at 12:50:52 PM, Chin Liang See wrote:
[...]
Quoted 5 lines
Quoted 5 lines
arch/arm/cpu/armv7/socfpga/misc.c +5
-0+/* +* If the HW watchdog is NOT enabled, make sure it is not running, +* for example because it was enabled in the preloader. This might +* trigger a watchdog-triggered reboot of Linux kernel later. +*/
Quoted 8 lines
arch/arm/cpu/armv7/socfpga/misc.c int overwrite_console(void) · line 50
Quoted 4 lines
arch/arm/cpu/armv7/socfpga/misc.c +4
-0+#ifndef CONFIG_HW_WATCHDOG +socfpga_watchdog_reset (); +#endif +
misc_init_rhappens at some time after U-Boot entry. Afraid the watchdog might trigger prior its disabled. Suggest to callsocfpga_watchdog_resetearlier.
arch_cpu_init() might be a good idea, thanks.
Best regards,
Marek Vasut
PATCH 11/51 arm: socfpga: sysmgr: Clean up system manager
In reply to Marek VasutClean up the system manager register definition and add the missing register definitions in place.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/system_manager.c | 18 ++-- arch/arm/include/asm/arch-socfpga/system_manager.h | 102 +++++++++++++++------ 2 files changed, 86 insertions(+), 34 deletions(-)
arch/arm/cpu/armv7/socfpga/system_manager.c +10 -8
@@ -1,5 +1,5 @@/* -* Copyright (C) 2013 Altera Corporation <www.altera.com> +* Copyright (C) 2013 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */
@@ -7,21 +7,23 @@#include <common.h> #include <asm/io.h> #include <asm/arch/system_manager.h> +#include <asm/arch/fpga_manager.h> DECLARE_GLOBAL_DATA_PTR ; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +/* * Configure all the pin muxes */ void sysmgr_pinmux_init (void ) { -unsigned long offset =CONFIG_SYSMGR_PINMUXGRP_OFFSET ; - -const unsigned long *pval = sys_mgr_init_table; -unsigned long i; +uint32_t regs = (uint32_t )&sysmgr_regs->emacio[0 ]; +int i; -for (i =0 ; i <ARRAY_SIZE (sys_mgr_init_table); - i++, offset +=sizeof (unsigned long )) { -writel (*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset)); +for (i =0 ; i <ARRAY_SIZE (sys_mgr_init_table); i++) { +writel (sys_mgr_init_table[i], regs); + regs +=sizeof (regs); } }
arch/arm/include/asm/arch-socfpga/system_manager.h +76 -26
153 lines not on this page · raw message
Signature · 1 line
2.0.0
PATCH 12/51 arm: socfpga: clock: Implant order into bit definitions
In reply to Marek VasutThe bit definitions for clock manager are complete chaos. Implement some basic logical order into them.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/include/asm/arch-socfpga/clock_manager.h | 166 +++++++++++++--------- 1 file changed, 99 insertions(+), 67 deletions(-)
arch/arm/include/asm/arch-socfpga/clock_manager.h +99 -67
@@ -103,96 +103,128 @@ struct socfpga_clock_manager {u32 _pad_0xe0_0x200[72 ]; }; -#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 +#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 +#define CLKMGR_CTRL_SAFEMODE_SET (x) (((x) << 0) & 0x00000001) + +#define CLKMGR_BYPASS_MAINPLL_SET (x) (((x) << 0) & 0x00000001) +#define CLKMGR_BYPASS_PERPLLSRC_SET (x) (((x) << 4) & 0x00000010) +#define CLKMGR_BYPASS_PERPLL_SET (x) (((x) << 3) & 0x00000008) +#define CLKMGR_BYPASS_SDRPLLSRC_SET (x) (((x) << 2) & 0x00000004) +#define CLKMGR_BYPASS_SDRPLL_SET (x) (((x) << 1) & 0x00000002) + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 + +/* Main PLL */ +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET (x) (((x) << 0) & 0x00000001) +#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET (x) (((x) << 16) & 0x003f0000) +#define CLKMGR_MAINPLLGRP_VCO_EN_SET (x) (((x) << 1) & 0x00000002) +#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET (x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET (x) (((x) << 2) & 0x00000004) +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d + +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET (x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET (x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 -#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 -#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 -#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 + +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET (x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET (x) (((x) << 2) & 0x0000000c)#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET (x) (((x) << 4) & 0x00000070)#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET (x) (((x) << 7) & 0x00000380) + +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET (x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET (x) (((x) << 2) & 0x0000000c) + +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET (x) (((x) << 0) & 0x00000007) +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET (x) (((x) << 0) & 0x00000001)#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET (x) (((x) << 1) & 0x00000002) -#define CLKMGR_PERPLLGRP_SRC_QSPI_SET (x) (((x) << 4) & 0x00000030) -#define CLKMGR_PERPLLGRP_SRC_NAND_SET (x) (((x) << 2) & 0x0000000c) -#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET (x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET (x) (((x) << 16) & 0x003f0000) -#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET (x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET (x) (((x) << 2) & 0x00000004) -#define CLKMGR_MAINPLLGRP_VCO_EN_SET (x) (((x) << 1) & 0x00000002) -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET (x) (((x) << 0) & 0x00000001) -#define CLKMGR_PERPLLGRP_VCO_PSRC_SET (x) (((x) << 22) & 0x00c00000) +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 + +/* Per PLL */ #define CLKMGR_PERPLLGRP_VCO_DENOM_SET (x) (((x) << 16) & 0x003f0000)#define CLKMGR_PERPLLGRP_VCO_NUMER_SET (x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET (x) (((x) << 25) & 0x7e000000) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET (x) (((x) << 24) & 0x01000000) -#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET (x) (((x) << 22) & 0x00c00000) -#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET (x) (((x) << 16) & 0x003f0000) -#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET (x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET (x) \ - (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_PSRC_SET (x) (((x) << 22) & 0x00c00000) +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET (x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET (x) \ - (((x) << 0) & 0x000001ff) + +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET (x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET (x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET (x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET (x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET (x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET (x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET (x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET (x) (((x) << 2) & 0x0000000c) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET (x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET (x) (((x) << 0) & 0x00000007) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET (x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET (x) (((x) << 2) & 0x0000000c) -#define CLKMGR_BYPASS_PERPLL_SET (x) (((x) << 3) & 0x00000008) -#define CLKMGR_BYPASS_SDRPLL_SET (x) (((x) << 1) & 0x00000002) -#define CLKMGR_BYPASS_MAINPLL_SET (x) (((x) << 0) & 0x00000001) -#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET (x) (((x) << 0) & 0x00000007) -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET (x) (((x) << 3) & 0x00000038) + +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET (x) (((x) << 6) & 0x000001c0)#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET (x) (((x) << 9) & 0x00000e00) -#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 -#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 -#define CLKMGR_CTRL_SAFEMODE_SET (x) (((x) << 0) & 0x00000001) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET (x) (((x) << 24) & 0x01000000) -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET (x) (((x) << 0) & 0x000001ff)#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET (x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET (x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET (x) (((x) << 0) & 0x00000007) +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET (x) (((x) << 0) & 0x00ffffff) -#define CLKMGR_BYPASS_PERPLLSRC_SET (x) (((x) << 4) & 0x00000010) -#define CLKMGR_BYPASS_SDRPLLSRC_SET (x) (((x) << 2) & 0x00000004) + +#define CLKMGR_PERPLLGRP_SRC_NAND_SET (x) (((x) << 2) & 0x0000000c) +#define CLKMGR_PERPLLGRP_SRC_QSPI_SET (x) (((x) << 4) & 0x00000030)#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 -#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 -#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET (x) (((x) << 0) & 0x00000003) + +/* SDR PLL */ +#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET (x) (((x) << 16) & 0x003f0000) +#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET (x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET (x) (((x) << 24) & 0x01000000) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET (x) (((x) << 24) & 0x01000000) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET (x) (((x) << 25) & 0x7e000000)#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET (x) (((x) << 22) & 0x00c00000) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET (x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET (x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET (x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET (x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET (x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET (x) (((x) << 9) & 0x00000e00)#define MAIN_VCO_BASE \ (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
Signature · 1 line
2.0.0
PATCH 13/51 arm: socfpga: clock: Drop nonsense inlining from clock manager code
In reply to Marek VasutThe inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Scrub this hint.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Dinh Nguyen <[email protected]>
--- arch/arm/cpu/armv7/socfpga/clock_manager.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
arch/arm/cpu/armv7/socfpga/clock_manager.c +6 -6
@@ -30,7 +30,7 @@ static const struct socfpga_clock_manager *clock_manager_base = CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) -static inline void cm_wait_for_lock (uint32_t mask) +static void cm_wait_for_lock (uint32_t mask) { registeruint32_t inter_val; do {
@@ -39,7 +39,7 @@ static inline void cm_wait_for_lock(uint32_t mask) }/* function to poll in the fsm busy bit */ -static inline void cm_wait_for_fsm (void ) +static void cm_wait_for_fsm (void ) {while (readl (&clock_manager_base->stat) &CLKMGR_STAT_BUSY ) ;
@@ -49,22 +49,22 @@ static inline void cm_wait_for_fsm(void)* function to write the bypass register which requires a poll of the * busy bit */ -static inline void cm_write_bypass (uint32_t val) +static void cm_write_bypass (uint32_t val) {writel (val, &clock_manager_base->bypass);cm_wait_for_fsm (); }/* function to write the ctrl register which requires a poll of the busy bit */ -static inline void cm_write_ctrl (uint32_t val) +static void cm_write_ctrl (uint32_t val) {writel (val, &clock_manager_base->ctrl);cm_wait_for_fsm (); }/* function to write a clock register that has phase information */ -static inline void cm_write_with_phase (uint32_t value, -uint32_t reg_address,uint32_t mask) +static void cm_write_with_phase (uint32_t value, +uint32_t reg_address,uint32_t mask) {/* poll until phase is zero */ while (readl (reg_address) & mask)
Signature · 1 line
2.0.0
PATCH 14/51 arm: socfpga: clock: Add missing stubs into board file
In reply to Marek VasutAdd some stub defines, which are used by the clock code, but are missing from the auto-generated header file for the SoCFPGA family.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- board/altera/socfpga/pll_config.h | 3 +++ 1 file changed, 3 insertions(+)
board/altera/socfpga/pll_config.h +3 -0
@@ -94,6 +94,9 @@/* Info for driver */ #define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ 0 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)#ifdef CONFIG_SOCFPGA_ARRIA5
Signature · 1 line
2.0.0
PATCH v2 15/51 arm: socfpga: clock: Add code to read clock configuration
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/clock_manager.c | 226 +++++++++++++++++++++- arch/arm/include/asm/arch-socfpga/clock_manager.h | 43 +++- include/configs/socfpga_cyclone5.h | 1 + 3 files changed, 267 insertions(+), 3 deletions(-)
V2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out)
arch/arm/cpu/armv7/socfpga/clock_manager.c +225 -1
@@ -8,8 +8,10 @@#include <asm/io.h> #include <asm/arch/clock_manager.h> +DECLARE_GLOBAL_DATA_PTR ; +static const struct socfpga_clock_manager *clock_manager_base = - (void *)SOCFPGA_CLKMGR_ADDRESS ; + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS ;#define CLKMGR_BYPASS_ENABLE 1#define CLKMGR_BYPASS_DISABLE 0
@@ -358,3 +360,225 @@ void cm_basic_init(const cm_config_t *cfg)writel (~0 , &clock_manager_base->per_pll.en);writel (~0 , &clock_manager_base->sdr_pll.en); } + +unsigned long cm_get_mpu_clk_hz (void ) +{ +uint32_t reg, clock; + +/* get the main VCO clock */ + reg =readl (&clock_manager_base->main_pll.vco); + clock =CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET (reg) +1 ); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET (reg) +1 ); + +/* get the MPU clock */ + reg =readl (&clock_manager_base->altera.mpuclk); + clock /= (reg +1 ); + reg =readl (&clock_manager_base->main_pll.mpuclk); + clock /= (reg +1 ); +return clock; +} + +unsigned long cm_get_sdram_clk_hz (void ) +{ +uint32_t reg, clock =0 ; + +/* identify SDRAM PLL clock source */ + reg =readl (&clock_manager_base->sdr_pll.vco); + reg =CLKMGR_SDRPLLGRP_VCO_SSRC_GET (reg); +if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) + clock =CONFIG_HPS_CLK_OSC1_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) + clock =CONFIG_HPS_CLK_OSC2_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_F2S ) + clock =CONFIG_HPS_CLK_F2S_SDR_REF_HZ ; + +/* get the SDRAM VCO clock */ + reg =readl (&clock_manager_base->sdr_pll.vco); + clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET (reg) +1 ); + clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET (reg) +1 ); + +/* get the SDRAM (DDR_DQS) clock */ + reg =readl (&clock_manager_base->sdr_pll.ddrdqsclk); + reg =CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET (reg); + clock /= (reg +1 ); + +return clock; +} + +unsigned int cm_get_l4_sp_clk_hz (void ) +{ +uint32_t reg, clock =0 ; + +/* identify the source of L4 SP clock */ + reg =readl (&clock_manager_base->main_pll.l4src); + reg =CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET (reg); + +if (reg ==CLKMGR_L4_SP_CLK_SRC_MAINPLL ) { +/* get the main VCO clock */ + reg =readl (&clock_manager_base->main_pll.vco); + clock =CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET (reg) +1 ); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET (reg) +1 ); + +/* get the clock prior L4 SP divider (main clk) */ + reg =readl (&clock_manager_base->altera.mainclk); + clock /= (reg +1 ); + reg =readl (&clock_manager_base->main_pll.mainclk); + clock /= (reg +1 ); + }else if (reg ==CLKMGR_L4_SP_CLK_SRC_PERPLL ) { +/* identify PER PLL clock source */ + reg =readl (&clock_manager_base->per_pll.vco); + reg =CLKMGR_PERPLLGRP_VCO_SSRC_GET (reg); +if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) + clock =CONFIG_HPS_CLK_OSC1_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) + clock =CONFIG_HPS_CLK_OSC2_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_F2S ) + clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; + +/* get the PER VCO clock */ + reg =readl (&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET (reg) +1 ); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET (reg) +1 ); + +/* get the clock prior L4 SP divider (periph_base_clk) */ + reg =readl (&clock_manager_base->per_pll.perbaseclk); + clock /= (reg +1 ); + } + +/* get the L4 SP clock which supplied to UART */ + reg =readl (&clock_manager_base->main_pll.maindiv); + reg =CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET (reg); + clock = clock / (1 << reg); + +return clock; +} + +unsigned int cm_get_mmc_controller_clk_hz (void ) +{ +uint32_t reg, clock =0 ; + +/* identify the source of MMC clock */ + reg =readl (&clock_manager_base->per_pll.src); + reg =CLKMGR_PERPLLGRP_SRC_SDMMC_GET (reg); + +if (reg ==CLKMGR_SDMMC_CLK_SRC_F2S ) { + clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; + }else if (reg ==CLKMGR_SDMMC_CLK_SRC_MAIN ) { +/* get the main VCO clock */ + reg =readl (&clock_manager_base->main_pll.vco); + clock =CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET (reg) +1 ); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET (reg) +1 ); + +/* get the SDMMC clock */ + reg =readl (&clock_manager_base->main_pll.mainnandsdmmcclk); + clock /= (reg +1 ); + }else if (reg ==CLKMGR_SDMMC_CLK_SRC_PER ) { +/* identify PER PLL clock source */ + reg =readl (&clock_manager_base->per_pll.vco); + reg =CLKMGR_PERPLLGRP_VCO_SSRC_GET (reg); +if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) + clock =CONFIG_HPS_CLK_OSC1_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) + clock =CONFIG_HPS_CLK_OSC2_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_F2S ) + clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; + +/* get the PER VCO clock */ + reg =readl (&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET (reg) +1 ); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET (reg) +1 ); + +/* get the SDMMC clock */ + reg =readl (&clock_manager_base->per_pll.pernandsdmmcclk); + clock /= (reg +1 ); + } + +/* further divide by 4 as we have fixed divider at wrapper */ + clock /=4 ; +return clock; +} + +unsigned int cm_get_qspi_controller_clk_hz (void ) +{ +uint32_t reg, clock =0 ; + +/* identify the source of QSPI clock */ + reg =readl (&clock_manager_base->per_pll.src); + reg =CLKMGR_PERPLLGRP_SRC_QSPI_GET (reg); + +if (reg ==CLKMGR_QSPI_CLK_SRC_F2S ) { + clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; + }else if (reg ==CLKMGR_QSPI_CLK_SRC_MAIN ) { +/* get the main VCO clock */ + reg =readl (&clock_manager_base->main_pll.vco); + clock =CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET (reg) +1 ); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET (reg) +1 ); + +/* get the qspi clock */ + reg =readl (&clock_manager_base->main_pll.mainqspiclk); + clock /= (reg +1 ); + }else if (reg ==CLKMGR_QSPI_CLK_SRC_PER ) { +/* identify PER PLL clock source */ + reg =readl (&clock_manager_base->per_pll.vco); + reg =CLKMGR_PERPLLGRP_VCO_SSRC_GET (reg); +if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) + clock =CONFIG_HPS_CLK_OSC1_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) + clock =CONFIG_HPS_CLK_OSC2_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_F2S ) + clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; + +/* get the PER VCO clock */ + reg =readl (&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET (reg) +1 ); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET (reg) +1 ); + +/* get the qspi clock */ + reg =readl (&clock_manager_base->per_pll.perqspiclk); + clock /= (reg +1 ); + } + +return clock; +} + +static void cm_print_clock_quick_summary (void ) +{ +printf ("MPU %10ld kHz\n" ,cm_get_mpu_clk_hz () /1000 ); +printf ("DDR %10ld kHz\n" ,cm_get_sdram_clk_hz () /1000 ); +printf ("EOSC1 %8d kHz\n" ,CONFIG_HPS_CLK_OSC1_HZ /1000 ); +printf ("EOSC2 %8d kHz\n" ,CONFIG_HPS_CLK_OSC2_HZ /1000 ); +printf ("F2S_SDR_REF %8d kHz\n" ,CONFIG_HPS_CLK_F2S_SDR_REF_HZ /1000 ); +printf ("F2S_PER_REF %8d kHz\n" ,CONFIG_HPS_CLK_F2S_PER_REF_HZ /1000 ); +printf ("MMC %8d kHz\n" ,cm_get_mmc_controller_clk_hz () /1000 ); +printf ("QSPI %8d kHz\n" ,cm_get_qspi_controller_clk_hz () /1000 ); +printf ("UART %8d kHz\n" ,cm_get_l4_sp_clk_hz () /1000 ); +} + +int set_cpu_clk_info (void ) +{ +/* Calculate the clock frequencies required for drivers */ +cm_get_l4_sp_clk_hz (); +cm_get_mmc_controller_clk_hz (); + + gd->bd->bi_arm_freq =cm_get_mpu_clk_hz () /1000000 ; + gd->bd->bi_dsp_freq =0 ; + gd->bd->bi_ddr_freq =cm_get_sdram_clk_hz () /1000000 ; + +return 0 ; +} + +int do_showclocks (cmd_tbl_t *cmdtp,int flag,int argc,char *const argv[]) +{ +cm_print_clock_quick_summary (); +return 0 ; +} + +U_BOOT_CMD ( + clocks,CONFIG_SYS_MAXARGS ,1 , do_showclocks, +"display clocks" , +"" +);
arch/arm/include/asm/arch-socfpga/clock_manager.h +41 -2
111 lines not on this page · raw message
include/configs/socfpga_cyclone5.h +1 -0
@@ -24,6 +24,7 @@#define CONFIG_MISC_INIT_R #define CONFIG_SINGLE_BOOTLOADER #define CONFIG_SOCFPGA +#define CONFIG_CLOCKS /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
Signature · 1 line
2.0.0
PATCH 16/51 arm: socfpga: clock: Trim down code duplication
In reply to Marek VasutPull out functions to read frequency of Main clock VCO and PLL clock VCO as the code is duplicated multiple times.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Dinh Nguyen <[email protected]>
--- arch/arm/cpu/armv7/socfpga/clock_manager.c | 96 ++++++++++++------------------ 1 file changed, 38 insertions(+), 58 deletions(-)
arch/arm/cpu/armv7/socfpga/clock_manager.c +38 -58
@@ -361,7 +361,7 @@ void cm_basic_init(const cm_config_t *cfg)writel (~0 , &clock_manager_base->sdr_pll.en); } -unsigned long cm_get_mpu_clk_hz (void ) +static unsigned int cm_get_main_vco_clk_hz (void ) {uint32_t reg, clock;
@@ -371,6 +371,37 @@ unsigned long cm_get_mpu_clk_hz(void) (CLKMGR_MAINPLLGRP_VCO_DENOM_GET (reg) +1 ); clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET (reg) +1 ); +return clock; +} + +static unsigned int cm_get_per_vco_clk_hz (void ) +{ +uint32_t reg, clock =0 ; + +/* identify PER PLL clock source */ + reg =readl (&clock_manager_base->per_pll.vco); + reg =CLKMGR_PERPLLGRP_VCO_SSRC_GET (reg); +if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) + clock =CONFIG_HPS_CLK_OSC1_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) + clock =CONFIG_HPS_CLK_OSC2_HZ ; +else if (reg ==CLKMGR_VCO_SSRC_F2S ) + clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; + +/* get the PER VCO clock */ + reg =readl (&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET (reg) +1 ); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET (reg) +1 ); + +return clock; +} + +unsigned long cm_get_mpu_clk_hz (void ) +{ +uint32_t reg, clock; + + clock =cm_get_main_vco_clk_hz (); +/* get the MPU clock */ reg =readl (&clock_manager_base->altera.mpuclk); clock /= (reg +1 );
@@ -415,11 +446,7 @@ unsigned int cm_get_l4_sp_clk_hz(void) reg =CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET (reg);if (reg ==CLKMGR_L4_SP_CLK_SRC_MAINPLL ) { -/* get the main VCO clock */ - reg =readl (&clock_manager_base->main_pll.vco); - clock =CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET (reg) +1 ); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET (reg) +1 ); + clock =cm_get_main_vco_clk_hz ();/* get the clock prior L4 SP divider (main clk) */ reg =readl (&clock_manager_base->altera.mainclk);
@@ -427,20 +454,7 @@ unsigned int cm_get_l4_sp_clk_hz(void) reg =readl (&clock_manager_base->main_pll.mainclk); clock /= (reg +1 ); }else if (reg ==CLKMGR_L4_SP_CLK_SRC_PERPLL ) { -/* identify PER PLL clock source */ - reg =readl (&clock_manager_base->per_pll.vco); - reg =CLKMGR_PERPLLGRP_VCO_SSRC_GET (reg); -if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) - clock =CONFIG_HPS_CLK_OSC1_HZ ; -else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) - clock =CONFIG_HPS_CLK_OSC2_HZ ; -else if (reg ==CLKMGR_VCO_SSRC_F2S ) - clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; - -/* get the PER VCO clock */ - reg =readl (&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET (reg) +1 ); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET (reg) +1 ); + clock =cm_get_per_vco_clk_hz ();/* get the clock prior L4 SP divider (periph_base_clk) */ reg =readl (&clock_manager_base->per_pll.perbaseclk);
@@ -466,30 +480,13 @@ unsigned int cm_get_mmc_controller_clk_hz(void)if (reg ==CLKMGR_SDMMC_CLK_SRC_F2S ) { clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; }else if (reg ==CLKMGR_SDMMC_CLK_SRC_MAIN ) { -/* get the main VCO clock */ - reg =readl (&clock_manager_base->main_pll.vco); - clock =CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET (reg) +1 ); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET (reg) +1 ); + clock =cm_get_main_vco_clk_hz ();/* get the SDMMC clock */ reg =readl (&clock_manager_base->main_pll.mainnandsdmmcclk); clock /= (reg +1 ); }else if (reg ==CLKMGR_SDMMC_CLK_SRC_PER ) { -/* identify PER PLL clock source */ - reg =readl (&clock_manager_base->per_pll.vco); - reg =CLKMGR_PERPLLGRP_VCO_SSRC_GET (reg); -if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) - clock =CONFIG_HPS_CLK_OSC1_HZ ; -else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) - clock =CONFIG_HPS_CLK_OSC2_HZ ; -else if (reg ==CLKMGR_VCO_SSRC_F2S ) - clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; - -/* get the PER VCO clock */ - reg =readl (&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET (reg) +1 ); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET (reg) +1 ); + clock =cm_get_per_vco_clk_hz ();/* get the SDMMC clock */ reg =readl (&clock_manager_base->per_pll.pernandsdmmcclk);
@@ -512,30 +509,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void)if (reg ==CLKMGR_QSPI_CLK_SRC_F2S ) { clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; }else if (reg ==CLKMGR_QSPI_CLK_SRC_MAIN ) { -/* get the main VCO clock */ - reg =readl (&clock_manager_base->main_pll.vco); - clock =CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET (reg) +1 ); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET (reg) +1 ); + clock =cm_get_main_vco_clk_hz ();/* get the qspi clock */ reg =readl (&clock_manager_base->main_pll.mainqspiclk); clock /= (reg +1 ); }else if (reg ==CLKMGR_QSPI_CLK_SRC_PER ) { -/* identify PER PLL clock source */ - reg =readl (&clock_manager_base->per_pll.vco); - reg =CLKMGR_PERPLLGRP_VCO_SSRC_GET (reg); -if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) - clock =CONFIG_HPS_CLK_OSC1_HZ ; -else if (reg ==CLKMGR_VCO_SSRC_EOSC2 ) - clock =CONFIG_HPS_CLK_OSC2_HZ ; -else if (reg ==CLKMGR_VCO_SSRC_F2S ) - clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ; - -/* get the PER VCO clock */ - reg =readl (&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET (reg) +1 ); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET (reg) +1 ); + clock =cm_get_per_vco_clk_hz ();/* get the qspi clock */ reg =readl (&clock_manager_base->per_pll.perqspiclk);
Signature · 1 line
2.0.0
PATCH 17/51 arm: socfpga: clock: Clean up bit definitions
In reply to Marek VasutClean up the clock code definitions so they are aligned with mainline standards. There are no functional changes in this patch.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/clock_manager.c | 122 +++----- arch/arm/cpu/armv7/socfpga/spl.c | 174 +++++++----- arch/arm/include/asm/arch-socfpga/clock_manager.h | 330 ++++++++++++---------- 3 files changed, 323 insertions(+), 303 deletions(-)
arch/arm/cpu/armv7/socfpga/clock_manager.c +47 -75
@@ -13,25 +13,6 @@ DECLARE_GLOBAL_DATA_PTR;static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS ; -#define CLKMGR_BYPASS_ENABLE 1 -#define CLKMGR_BYPASS_DISABLE 0 -#define CLKMGR_STAT_IDLE 0 -#define CLKMGR_STAT_BUSY 1 -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0 -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1 -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0 -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1 - -#define CLEAR_BGP_EN_PWRDN \ - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) - -#define VCO_EN_BASE \ - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) -static void cm_wait_for_lock (uint32_t mask) { registeruint32_t inter_val;
@@ -130,14 +111,8 @@ void cm_basic_init(const cm_config_t *cfg)writel (0 , &clock_manager_base->per_pll.en);/* Put all plls in bypass */ -cm_write_bypass ( -CLKMGR_BYPASS_PERPLLSRC_SET ( -CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 ) | -CLKMGR_BYPASS_SDRPLLSRC_SET ( -CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 ) | -CLKMGR_BYPASS_PERPLL_SET (CLKMGR_BYPASS_ENABLE ) | -CLKMGR_BYPASS_SDRPLL_SET (CLKMGR_BYPASS_ENABLE ) | -CLKMGR_BYPASS_MAINPLL_SET (CLKMGR_BYPASS_ENABLE )); +cm_write_bypass (CLKMGR_BYPASS_PERPLL |CLKMGR_BYPASS_SDRPLL | +CLKMGR_BYPASS_MAINPLL );/* * Put all plls VCO registers back to reset value.
@@ -172,19 +147,14 @@ void cm_basic_init(const cm_config_t *cfg)* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. */ -writel (cfg->main_vco_base |CLEAR_BGP_EN_PWRDN | -CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK , - &clock_manager_base->main_pll.vco); - -writel (cfg->peri_vco_base |CLEAR_BGP_EN_PWRDN | -CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK , - &clock_manager_base->per_pll.vco); - -writel (CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET (0 ) | -CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET (0 ) | - cfg->sdram_vco_base |CLEAR_BGP_EN_PWRDN | -CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK , - &clock_manager_base->sdr_pll.vco); +writel (cfg->main_vco_base |CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK , + &clock_manager_base->main_pll.vco); + +writel (cfg->peri_vco_base |CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK , + &clock_manager_base->per_pll.vco); + +writel (cfg->sdram_vco_base |CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK , + &clock_manager_base->sdr_pll.vco);/* * Time starts here
@@ -234,18 +204,16 @@ void cm_basic_init(const cm_config_t *cfg)/* Enable vco */ /* main pll vco */ -writel (cfg->main_vco_base |VCO_EN_BASE , +writel (cfg->main_vco_base |CLKMGR_MAINPLLGRP_VCO_EN , &clock_manager_base->main_pll.vco);/* periferal pll */ -writel (cfg->peri_vco_base |VCO_EN_BASE , +writel (cfg->peri_vco_base |CLKMGR_MAINPLLGRP_VCO_EN , &clock_manager_base->per_pll.vco);/* sdram pll vco */ -writel (CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET (0 ) | -CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET (0 ) | - cfg->sdram_vco_base |VCO_EN_BASE , - &clock_manager_base->sdr_pll.vco); +writel (cfg->sdram_vco_base |CLKMGR_MAINPLLGRP_VCO_EN , + &clock_manager_base->sdr_pll.vco);/* L3 MP and L3 SP */ writel (cfg->maindiv, &clock_manager_base->main_pll.maindiv);
@@ -296,8 +264,8 @@ void cm_basic_init(const cm_config_t *cfg) &clock_manager_base->per_pll.vco);/* assert sdram outresetall */ -writel (cfg->sdram_vco_base |VCO_EN_BASE | -CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET (1 ), +writel (cfg->sdram_vco_base |CLKMGR_MAINPLLGRP_VCO_EN | +CLKMGR_SDRPLLGRP_VCO_OUTRESETALL , &clock_manager_base->sdr_pll.vco);/* deassert main outresetall */
@@ -309,9 +277,8 @@ void cm_basic_init(const cm_config_t *cfg) &clock_manager_base->per_pll.vco);/* deassert sdram outresetall */ -writel (CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET (0 ) | - cfg->sdram_vco_base |VCO_EN_BASE , - &clock_manager_base->sdr_pll.vco); +writel (cfg->sdram_vco_base |CLKMGR_MAINPLLGRP_VCO_EN , + &clock_manager_base->sdr_pll.vco);/* * now that we've toggled outreset all, all the clocks
@@ -335,18 +302,10 @@ void cm_basic_init(const cm_config_t *cfg) CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);/* Take all three PLLs out of bypass when safe mode is cleared. */ -cm_write_bypass ( -CLKMGR_BYPASS_PERPLLSRC_SET ( -CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 ) | -CLKMGR_BYPASS_SDRPLLSRC_SET ( -CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 ) | -CLKMGR_BYPASS_PERPLL_SET (CLKMGR_BYPASS_DISABLE ) | -CLKMGR_BYPASS_SDRPLL_SET (CLKMGR_BYPASS_DISABLE ) | -CLKMGR_BYPASS_MAINPLL_SET (CLKMGR_BYPASS_DISABLE )); +cm_write_bypass (0 );/* clear safe mode */ -cm_write_ctrl (readl (&clock_manager_base->ctrl) | -CLKMGR_CTRL_SAFEMODE_SET (CLKMGR_CTRL_SAFEMODE_MASK )); +cm_write_ctrl (readl (&clock_manager_base->ctrl) |CLKMGR_CTRL_SAFEMODE );/* * now that safe mode is clear with clocks gated
@@ -367,9 +326,11 @@ static unsigned int cm_get_main_vco_clk_hz(void)/* get the main VCO clock */ reg =readl (&clock_manager_base->main_pll.vco); - clock =CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET (reg) +1 ); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET (reg) +1 ); + clock =CONFIG_HPS_CLK_OSC1_HZ ; + clock /= ((reg &CLKMGR_MAINPLLGRP_VCO_DENOM_MASK ) >> +CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET ) +1 ; + clock *= ((reg &CLKMGR_MAINPLLGRP_VCO_NUMER_MASK ) >> +CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET ) +1 ;return clock; }
@@ -380,7 +341,8 @@ static unsigned int cm_get_per_vco_clk_hz(void)/* identify PER PLL clock source */ reg =readl (&clock_manager_base->per_pll.vco); - reg =CLKMGR_PERPLLGRP_VCO_SSRC_GET (reg); + reg = (reg &CLKMGR_PERPLLGRP_VCO_SSRC_MASK ) >> +CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET ;if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) clock =CONFIG_HPS_CLK_OSC1_HZ ;else if (reg ==CLKMGR_VCO_SSRC_EOSC2 )
@@ -390,8 +352,10 @@ static unsigned int cm_get_per_vco_clk_hz(void)/* get the PER VCO clock */ reg =readl (&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET (reg) +1 ); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET (reg) +1 ); + clock /= ((reg &CLKMGR_PERPLLGRP_VCO_DENOM_MASK ) >> +CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET ) +1 ; + clock *= ((reg &CLKMGR_PERPLLGRP_VCO_NUMER_MASK ) >> +CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET ) +1 ;return clock; }
@@ -416,7 +380,8 @@ unsigned long cm_get_sdram_clk_hz(void)/* identify SDRAM PLL clock source */ reg =readl (&clock_manager_base->sdr_pll.vco); - reg =CLKMGR_SDRPLLGRP_VCO_SSRC_GET (reg); + reg = (reg &CLKMGR_SDRPLLGRP_VCO_SSRC_MASK ) >> +CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET ;if (reg ==CLKMGR_VCO_SSRC_EOSC1 ) clock =CONFIG_HPS_CLK_OSC1_HZ ;else if (reg ==CLKMGR_VCO_SSRC_EOSC2 )
@@ -426,12 +391,15 @@ unsigned long cm_get_sdram_clk_hz(void)/* get the SDRAM VCO clock */ reg =readl (&clock_manager_base->sdr_pll.vco); - clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET (reg) +1 ); - clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET (reg) +1 ); + clock /= ((reg &CLKMGR_SDRPLLGRP_VCO_DENOM_MASK ) >> +CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET ) +1 ; + clock *= ((reg &CLKMGR_SDRPLLGRP_VCO_NUMER_MASK ) >> +CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET ) +1 ;/* get the SDRAM (DDR_DQS) clock */ reg =readl (&clock_manager_base->sdr_pll.ddrdqsclk); - reg =CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET (reg); + reg = (reg &CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK ) >> +CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET ; clock /= (reg +1 );return clock;
@@ -443,7 +411,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)/* identify the source of L4 SP clock */ reg =readl (&clock_manager_base->main_pll.l4src); - reg =CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET (reg); + reg = (reg &CLKMGR_MAINPLLGRP_L4SRC_L4SP ) >> +CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET ;if (reg ==CLKMGR_L4_SP_CLK_SRC_MAINPLL ) { clock =cm_get_main_vco_clk_hz ();
@@ -463,7 +432,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)/* get the L4 SP clock which supplied to UART */ reg =readl (&clock_manager_base->main_pll.maindiv); - reg =CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET (reg); + reg = (reg &CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK ) >> +CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET ; clock = clock / (1 << reg);return clock;
@@ -475,7 +445,8 @@ unsigned int cm_get_mmc_controller_clk_hz(void)/* identify the source of MMC clock */ reg =readl (&clock_manager_base->per_pll.src); - reg =CLKMGR_PERPLLGRP_SRC_SDMMC_GET (reg); + reg = (reg &CLKMGR_PERPLLGRP_SRC_SDMMC_MASK ) >> +CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET ;if (reg ==CLKMGR_SDMMC_CLK_SRC_F2S ) { clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ;
@@ -504,7 +475,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void)/* identify the source of QSPI clock */ reg =readl (&clock_manager_base->per_pll.src); - reg =CLKMGR_PERPLLGRP_SRC_QSPI_GET (reg); + reg = (reg &CLKMGR_PERPLLGRP_SRC_QSPI_MASK ) >> +CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET ;if (reg ==CLKMGR_QSPI_CLK_SRC_F2S ) { clock =CONFIG_HPS_CLK_F2S_PER_REF_HZ ;
arch/arm/cpu/armv7/socfpga/spl.c +100 -74
192 lines not on this page · raw message
arch/arm/include/asm/arch-socfpga/clock_manager.h +176 -154
341 lines not on this page · raw message
Signature · 1 line
2.0.0
PATCH 18/51 arm: socfpga: clock: Sync with reference code
In reply to Marek VasutAdd the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/clock_manager.c | 42 ++++++++++++++--------- arch/arm/include/asm/arch-socfpga/clock_manager.h | 3 ++ 2 files changed, 29 insertions(+), 16 deletions(-)
arch/arm/cpu/armv7/socfpga/clock_manager.c +26 -16
@@ -16,9 +16,16 @@ static const struct socfpga_clock_manager *clock_manager_base =static void cm_wait_for_lock (uint32_t mask) { registeruint32_t inter_val; +uint32_t retry =0 ;do { inter_val =readl (&clock_manager_base->inter) & mask; - }while (inter_val != mask); +if (inter_val == mask) + retry++; +else + retry =0 ; +if (retry >=10 ) +break ; + }while (1 ); }/* function to poll in the fsm busy bit */
@@ -114,15 +121,15 @@ void cm_basic_init(const cm_config_t *cfg)cm_write_bypass (CLKMGR_BYPASS_PERPLL |CLKMGR_BYPASS_SDRPLL |CLKMGR_BYPASS_MAINPLL ); -/* -* Put all plls VCO registers back to reset value. -* Some code might have messed with them. -*/ -writel (CLKMGR_MAINPLLGRP_VCO_RESET_VALUE , +/* Put all plls VCO registers back to reset value. */ +writel (CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK , &clock_manager_base->main_pll.vco); -writel (CLKMGR_PERPLLGRP_VCO_RESET_VALUE , +writel (CLKMGR_PERPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK , &clock_manager_base->per_pll.vco); -writel (CLKMGR_SDRPLLGRP_VCO_RESET_VALUE , +writel (CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK , &clock_manager_base->sdr_pll.vco);/*
@@ -147,14 +154,9 @@ void cm_basic_init(const cm_config_t *cfg)* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. */ -writel (cfg->main_vco_base |CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK , - &clock_manager_base->main_pll.vco); - -writel (cfg->peri_vco_base |CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK , - &clock_manager_base->per_pll.vco); - -writel (cfg->sdram_vco_base |CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK , - &clock_manager_base->sdr_pll.vco); +writel (cfg->main_vco_base, &clock_manager_base->main_pll.vco); +writel (cfg->peri_vco_base, &clock_manager_base->per_pll.vco); +writel (cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);/* * Time starts here
@@ -189,6 +191,9 @@ void cm_basic_init(const cm_config_t *cfg)writel (cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);/* Peri pernandsdmmcclk */ +writel (cfg->mainnandsdmmcclk, + &clock_manager_base->main_pll.mainnandsdmmcclk); +writel (cfg->pernandsdmmcclk, &clock_manager_base->per_pll.pernandsdmmcclk);
@@ -318,6 +323,11 @@ void cm_basic_init(const cm_config_t *cfg)writel (~0 , &clock_manager_base->main_pll.en);writel (~0 , &clock_manager_base->per_pll.en);writel (~0 , &clock_manager_base->sdr_pll.en); + +/* Clear the loss of lock bits (write 1 to clear) */ +writel (CLKMGR_INTER_SDRPLLLOST_MASK |CLKMGR_INTER_PERPLLLOST_MASK | +CLKMGR_INTER_MAINPLLLOST_MASK , + &clock_manager_base->inter); }static unsigned int cm_get_main_vco_clk_hz (void )
arch/arm/include/asm/arch-socfpga/clock_manager.h +3 -0
@@ -135,6 +135,9 @@ struct socfpga_clock_manager {#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010 +#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008#define CLKMGR_STAT_BUSY (1 << 0)
Signature · 1 line
2.0.0
PATCH 19/51 arm: socfpga: mmc: Pick the clock from clock manager
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Make the SoCFPGA MMC stub pick clock via the clock manager frequency accessors instead of hard-coding the frequency.
Also fix calloc() misuse.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Dinh Nguyen <[email protected]>
--- drivers/mmc/socfpga_dw_mmc.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)
drivers/mmc/socfpga_dw_mmc.c +11 -4
@@ -7,6 +7,7 @@#include <common.h> #include <malloc.h> #include <dwmmc.h> +#include <errno.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h>
@@ -44,12 +45,18 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)int socfpga_dwmmc_init (u32 regbase,int bus_width,int index) {struct dwmci_host *host; +unsigned long clk =cm_get_mmc_controller_clk_hz (); + +if (clk ==0 ) { +printf ("%s: MMC clock is zero!" , __func__); +return -EINVAL ; + }/* calloc for zero init */ - host =calloc (sizeof (struct dwmci_host ),1 ); + host =calloc (1 ,sizeof (struct dwmci_host ));if (!host) { -printf ("dwmci_host calloc fail!\n" ); -return -1 ; +printf ("%s: calloc() failed!\n" , __func__); +return -ENOMEM ; } host->name ="SOCFPGA DWMMC" ;
@@ -58,7 +65,7 @@ int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) host->clksel = socfpga_dwmci_clksel; host->dev_index = index;/* fixed clock divide by 4 which due to the SDMMC wrapper */ - host->bus_hz =CONFIG_SOCFPGA_DWMMC_BUS_HZ ; + host->bus_hz = clk; host->fifoth_val =MSIZE (0x2 ) |RX_WMARK (CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH /2 -1 ) |TX_WMARK (CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH /2 );
Signature · 1 line
2.0.0
PATCH 20/51 arm: socfpga: timer: Pull the timer reload value from config file
In reply to Marek VasutThe timer reload value is a property of the timer hardware and there is no reason for this to be configurable. Place this into the timer driver just like on the other hardware.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Dinh Nguyen <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/timer.c | 2 ++ include/configs/socfpga_cyclone5.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/cpu/armv7/socfpga/timer.c +2 -0
@@ -8,6 +8,8 @@#include <asm/io.h> #include <asm/arch/timer.h> +#define TIMER_LOAD_VAL 0xFFFFFFFF +static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE ;/*
include/configs/socfpga_cyclone5.h +0 -2
@@ -195,8 +195,6 @@/* This timer use eosc1 where the clock frequency is fixed * throughout any condition */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0xFFFFFFFF/* Timer info */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TIMER_RATE 2400000
Signature · 1 line
2.0.0
PATCH 21/51 arm: socfpga: reset: Add EMAC reset functions
In reply to Marek VasutAdd functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/reset_manager.c | 17 +++++++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 3 +++ 2 files changed, 20 insertions(+)
arch/arm/cpu/armv7/socfpga/reset_manager.c +17 -0
@@ -49,3 +49,20 @@ void reset_deassert_peripherals_handoff(void) {writel (0 , &reset_manager_base->per_mod_reset); } + +/* Change the reset state for EMAC 0 and EMAC 1 */ +void socfpga_emac_reset (int enable) +{ +const void *reset = &reset_manager_base->per_mod_reset; + +if (enable) { +setbits_le32 (reset,1 <<RSTMGR_PERMODRST_EMAC0_LSB ); +setbits_le32 (reset,1 <<RSTMGR_PERMODRST_EMAC1_LSB ); + }else { +#if (CONFIG_EMAC_BASE ==SOCFPGA_EMAC0_ADDRESS ) +clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_EMAC0_LSB ); +#elif (CONFIG_EMAC_BASE ==SOCFPGA_EMAC1_ADDRESS ) +clrbits_le32 (reset,1 <<RSTMGR_PERMODRST_EMAC1_LSB ); +#endif + } +}
arch/arm/include/asm/arch-socfpga/reset_manager.h +3 -0
@@ -10,6 +10,7 @@void reset_cpu (ulong addr);void reset_deassert_peripherals_handoff (void ); +void socfpga_emac_reset (int enable);void socfpga_watchdog_reset (void );struct socfpga_reset_manager {
@@ -29,6 +30,8 @@ struct socfpga_reset_manager {#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1#endif +#define RSTMGR_PERMODRST_EMAC0_LSB 0 +#define RSTMGR_PERMODRST_EMAC1_LSB 1#define RSTMGR_PERMODRST_L4WD0_LSB 6#endif /* _RESET_MANAGER_H_ */
Signature · 1 line
2.0.0
PATCH 22/51 arm: socfpga: misc: Add proper ethernet initialization
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.
We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/misc.c | 58 ++++++++++++++++------ arch/arm/include/asm/arch-socfpga/system_manager.h | 9 ++++ 2 files changed, 52 insertions(+), 15 deletions(-)
arch/arm/cpu/armv7/socfpga/misc.c +43 -15
@@ -9,15 +9,58 @@#include <miiphy.h> #include <netdev.h> #include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> DECLARE_GLOBAL_DATA_PTR ; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +int dram_init (void ) { gd->ram_size =get_ram_size ((long *)PHYS_SDRAM_1 ,PHYS_SDRAM_1_SIZE );return 0 ; } +/* +* DesignWare Ethernet initialization +*/ +#ifdef CONFIG_DESIGNWARE_ETH +int cpu_eth_init (bd_t *bis) +{ +#if CONFIG_EMAC_BASE ==SOCFPGA_EMAC0_ADDRESS +const int physhift =SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB ; +#elif CONFIG_EMAC_BASE ==SOCFPGA_EMAC1_ADDRESS +const int physhift =SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB ; +#else +#error "Incorrect CONFIG_EMAC_BASE value!" +#endif + +/* Initialize EMAC. This needs to be done at least once per boot. */ + +/* +* Putting the EMAC controller to reset when configuring the PHY +* interface select at System Manager +*/ +socfpga_emac_reset (1 ); + +/* Clearing emac0 PHY interface select to 0 */ +clrbits_le32 (&sysmgr_regs->emacgrp_ctrl, +SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); + +/* configure to PHY interface select choosed */ +setbits_le32 (&sysmgr_regs->emacgrp_ctrl, +SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); + +/* Release the EMAC controller from reset */ +socfpga_emac_reset (0 ); + +/* initialize and register the emac */ +return designware_initialize (CONFIG_EMAC_BASE , +CONFIG_PHY_INTERFACE_MODE ); +} +#endif +#if defined(CONFIG_DISPLAY_CPUINFO )/* * Print CPU information
@@ -50,18 +93,3 @@ int misc_init_r(void)return 0 ; } - - -/* -* DesignWare Ethernet initialization -*/ -int cpu_eth_init (bd_t *bis) -{ -#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET ) && !defined(CONFIG_SPL_BUILD ) -/* initialize and register the emac */ -return designware_initialize (CONFIG_EMAC_BASE , -CONFIG_PHY_INTERFACE_MODE ); -#else -return 0 ; -#endif -}
arch/arm/include/asm/arch-socfpga/system_manager.h +9 -0
@@ -134,4 +134,13 @@ struct socfpga_system_manager {#define SYSMGR_SDMMC_CTRL_SET (smplsel, drvsel) \ ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) +/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 +#endif /* _SYSTEM_MANAGER_H_ */
Signature · 1 line
2.0.0
PATCH 23/51 arm: socfpga: misc: Add SD controller init
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Add CPU function to register and initialize the dw_mmc SD controller. This allows us to use the HPS SDMMC block.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/misc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm/cpu/armv7/socfpga/misc.c +13 -0
@@ -10,6 +10,7 @@#include <netdev.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> +#include <asm/arch/dwmmc.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -61,6 +62,18 @@ int cpu_eth_init(bd_t *bis) }#endif +#ifdef CONFIG_DWMMC +/* +* Initializes MMC controllers. +* to override, implement board_mmc_init() +*/ +int cpu_mmc_init (bd_t *bis) +{ +return socfpga_dwmmc_init (SOCFPGA_SDMMC_ADDRESS , +CONFIG_HPS_SDMMC_BUSWIDTH ,0 ); +} +#endif +#if defined(CONFIG_DISPLAY_CPUINFO )/* * Print CPU information
Signature · 1 line
2.0.0
PATCH 24/51 arm: socfpga: misc: Align print_cpuinfo() output
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Cosmetic change to the print_cpuinfo() function output. Align the output with the rest of initial output produced by U-Boot.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/misc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/cpu/armv7/socfpga/misc.c +1 -1
@@ -80,7 +80,7 @@ int cpu_mmc_init(bd_t *bis)*/ int print_cpuinfo (void ) { -puts ("CPU : Altera SOCFPGA Platform\n" ); +puts ("CPU: Altera SoCFPGA Platform\n" );return 0 ; }#endif
Signature · 1 line
2.0.0
PATCH 25/51 arm: socfpga: board: Correctly set ATAG position
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- board/altera/socfpga/socfpga_cyclone5.c | 4 ++++ 1 file changed, 4 insertions(+)
board/altera/socfpga/socfpga_cyclone5.c +4 -0
@@ -35,5 +35,9 @@ int board_early_init_f(void)int board_init (void ) {icache_enable (); + +/* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params =CONFIG_SYS_SDRAM_BASE +0x100 ; +return 0 ; }
Signature · 1 line
2.0.0
PATCH 26/51 arm: socfpga: board: Align checkboard() output
In reply to Marek VasutCosmetic change to the checkboard() function output. Align the output with the rest of initial output produced by U-Boot.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- board/altera/socfpga/socfpga_cyclone5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
board/altera/socfpga/socfpga_cyclone5.c +1 -1
@@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;*/ int checkboard (void ) { -puts ("BOARD : Altera SOCFPGA Cyclone5 Board\n" ); +puts ("BOARD: Altera SoCFPGA Cyclone5 Board\n" );return 0 ; }
Signature · 1 line
2.0.0
PATCH 27/51 fpga: altera: Clean up the printing and debug
In reply to Marek VasutClean up the printf() statements and get rid of the PRINTF() macro by replacing it with debug_cond().
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- drivers/fpga/altera.c | 117 +++++++++++++++++++++++++------------------------- 1 file changed, 58 insertions(+), 59 deletions(-)
drivers/fpga/altera.c +58 -59
@@ -15,14 +15,8 @@#include <ACEX1K.h> #include <stratixII.h> -/* Define FPGA_DEBUG to get debug printf's */ -/* #define FPGA_DEBUG */ - -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif +/* Define FPGA_DEBUG to 1 to get debug printf's */ +#define FPGA_DEBUG 0/* Local Static Functions */ static int altera_validate (Altera_desc * desc,const char *fn);
@@ -32,36 +26,39 @@ int altera_load(Altera_desc *desc, const void *buf, size_t bsize) {int ret_val =FPGA_FAIL ;/* assume a failure */ -if (!altera_validate (desc, (char *)__FUNCTION__)) { -printf ("%s: Invalid device descriptor\n" , __FUNCTION__); +if (!altera_validate (desc, (char *)__func__)) { +printf ("%s: Invalid device descriptor\n" , __func__); }else {switch (desc->family) {case Altera_ACEX1K:case Altera_CYC2:#if defined(CONFIG_FPGA_ACEX1K ) -PRINTF ("%s: Launching the ACEX1K Loader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the ACEX1K Loader...\n" , + __func__); ret_val =ACEX1K_load (desc, buf, bsize);#elif defined(CONFIG_FPGA_CYCLON2 ) -PRINTF ("%s: Launching the CYCLONE II Loader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the CYCLONE II Loader...\n" , + __func__); ret_val =CYC2_load (desc, buf, bsize);#else -printf ("%s: No support for ACEX1K devices.\n" , - __FUNCTION__); +printf ("%s: No support for ACEX1K devices.\n" , + __func__);#endif break ;#if defined(CONFIG_FPGA_STRATIX_II )case Altera_StratixII: -PRINTF ("%s: Launching the Stratix II Loader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the Stratix II Loader...\n" , + __func__); ret_val =StratixII_load (desc, buf, bsize);break ;#endif default : -printf ("%s: Unsupported family type, %d\n" , - __FUNCTION__, desc->family); +printf ("%s: Unsupported family type, %d\n" , + __func__, desc->family); } }
@@ -72,31 +69,33 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) {int ret_val =FPGA_FAIL ;/* assume a failure */ -if (!altera_validate (desc, (char *)__FUNCTION__)) { -printf ("%s: Invalid device descriptor\n" , __FUNCTION__); +if (!altera_validate (desc, (char *)__func__)) { +printf ("%s: Invalid device descriptor\n" , __func__); }else {switch (desc->family) {case Altera_ACEX1K:#if defined(CONFIG_FPGA_ACEX ) -PRINTF ("%s: Launching the ACEX1K Reader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the ACEX1K Reader...\n" , + __func__); ret_val =ACEX1K_dump (desc, buf, bsize);#else -printf ("%s: No support for ACEX1K devices.\n" , - __FUNCTION__); +printf ("%s: No support for ACEX1K devices.\n" , + __func__);#endif break ;#if defined(CONFIG_FPGA_STRATIX_II )case Altera_StratixII: -PRINTF ("%s: Launching the Stratix II Reader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the Stratix II Reader...\n" , + __func__); ret_val =StratixII_dump (desc, buf, bsize);break ;#endif default : -printf ("%s: Unsupported family type, %d\n" , - __FUNCTION__, desc->family); +printf ("%s: Unsupported family type, %d\n" , + __func__, desc->family); } }
@@ -107,42 +106,42 @@ int altera_info( Altera_desc *desc ) {int ret_val =FPGA_FAIL ; -if (altera_validate (desc, (char *)__FUNCTION__)) { -printf ("Family: \t" ); +if (altera_validate (desc, (char *)__func__)) { +printf ("Family: \t" );switch (desc->family) {case Altera_ACEX1K: -printf ("ACEX1K\n" ); +printf ("ACEX1K\n" );break ;case Altera_CYC2: -printf ("CYCLON II\n" ); +printf ("CYCLON II\n" );break ;case Altera_StratixII: -printf ("Stratix II\n" ); +printf ("Stratix II\n" );break ;/* Add new family types here */ default : -printf ("Unknown family type, %d\n" , desc->family); +printf ("Unknown family type, %d\n" , desc->family); } -printf ("Interface type:\t" ); +printf ("Interface type:\t" );switch (desc->iface) {case passive_serial: -printf ("Passive Serial (PS)\n" ); +printf ("Passive Serial (PS)\n" );break ;case passive_parallel_synchronous: -printf ("Passive Parallel Synchronous (PPS)\n" ); +printf ("Passive Parallel Synchronous (PPS)\n" );break ;case passive_parallel_asynchronous: -printf ("Passive Parallel Asynchronous (PPA)\n" ); +printf ("Passive Parallel Asynchronous (PPA)\n" );break ;case passive_serial_asynchronous: -printf ("Passive Serial Asynchronous (PSA)\n" ); +printf ("Passive Serial Asynchronous (PSA)\n" );break ;case altera_jtag_mode:/* Not used */ -printf ("JTAG Mode\n" ); +printf ("JTAG Mode\n" );break ;case fast_passive_parallel: -printf ("Fast Passive Parallel (FPP)\n" ); +printf ("Fast Passive Parallel (FPP)\n" );break ;case fast_passive_parallel_security: printf
@@ -150,31 +149,31 @@ int altera_info( Altera_desc *desc )break ;/* Add new interface types here */ default : -printf ("Unsupported interface type, %d\n" , desc->iface); +printf ("Unsupported interface type, %d\n" , desc->iface); }printf ("Device Size: \t%zd bytes\n" -"Cookie: \t0x%x (%d)\n" , - desc->size, desc->cookie, desc->cookie); +"Cookie: \t0x%x (%d)\n" , + desc->size, desc->cookie, desc->cookie);if (desc->iface_fns) { -printf ("Device Function Table @ 0x%p\n" , desc->iface_fns); +printf ("Device Function Table @ 0x%p\n" , desc->iface_fns);switch (desc->family) {case Altera_ACEX1K:case Altera_CYC2:#if defined(CONFIG_FPGA_ACEX1K ) -ACEX1K_info (desc); +ACEX1K_info (desc);#elif defined(CONFIG_FPGA_CYCLON2 ) -CYC2_info (desc); +CYC2_info (desc);#else /* just in case */ -printf ("%s: No support for ACEX1K devices.\n" , - __FUNCTION__); +printf ("%s: No support for ACEX1K devices.\n" , + __func__);#endif break ;#if defined(CONFIG_FPGA_STRATIX_II )case Altera_StratixII: -StratixII_info (desc); +StratixII_info (desc);break ;#endif /* Add new family types here */
@@ -183,12 +182,12 @@ int altera_info( Altera_desc *desc )break ; } }else { -printf ("No Device Function Table.\n" ); +printf ("No Device Function Table.\n" ); } ret_val =FPGA_SUCCESS ; }else { -printf ("%s: Invalid device descriptor\n" , __FUNCTION__); +printf ("%s: Invalid device descriptor\n" , __func__); }return ret_val;
@@ -208,17 +207,17 @@ static int altera_validate (Altera_desc * desc, const char *fn)if (desc->size) { ret_val = true; }else { -printf ("%s: NULL part size\n" , fn); +printf ("%s: NULL part size\n" , fn); } }else { -printf ("%s: Invalid Interface type, %d\n" , - fn, desc->iface); +printf ("%s: Invalid Interface type, %d\n" , + fn, desc->iface); } }else { -printf ("%s: Invalid family type, %d\n" , fn, desc->family); +printf ("%s: Invalid family type, %d\n" , fn, desc->family); } }else { -printf ("%s: NULL descriptor!\n" , fn); +printf ("%s: NULL descriptor!\n" , fn); }return ret_val;
Signature · 1 line
2.0.0
PATCH 27/51 fpga: altera: Clean up the printing and debug
Quoted 257 lines · Marek Vasut
Clean up the
printf()statements and get rid of thePRINTF()macro by replacing it withdebug_cond().Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>--- drivers/fpga/altera.c | 117 +++++++++++++++++++++++++------------------------- 1 file changed, 58 insertions(+), 59 deletions(-)drivers/fpga/altera.c +56
-57@@ -15,14 +15,8 @@#include <ACEX1K.h> #include <stratixII.h> -/* Define FPGA_DEBUG to get debug printf's */ -/* #define FPGA_DEBUG */ - -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif +/* Define FPGA_DEBUG to 1 to get debug printf's */ +#define FPGA_DEBUG 0/* Local Static Functions */ static int altera_validate (Altera_desc * desc,const char *fn);@@ -32,36 +26,39 @@ int altera_load(Altera_desc *desc, const void *buf, size_t bsize) {int ret_val =FPGA_FAIL ;/* assume a failure */ -if (!altera_validate (desc, (char *)__FUNCTION__)) { -printf ("%s: Invalid device descriptor\n" , __FUNCTION__); +if (!altera_validate (desc, (char *)__func__)) { +printf ("%s: Invalid device descriptor\n" , __func__); }else {switch (desc->family) {case Altera_ACEX1K:case Altera_CYC2:#if defined(CONFIG_FPGA_ACEX1K ) -PRINTF ("%s: Launching the ACEX1K Loader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the ACEX1K Loader...\n" , + __func__); ret_val =ACEX1K_load (desc, buf, bsize);#elif defined(CONFIG_FPGA_CYCLON2 ) -PRINTF ("%s: Launching the CYCLONE II Loader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the CYCLONE II Loader...\n" , + __func__); ret_val =CYC2_load (desc, buf, bsize);#else -printf ("%s: No support for ACEX1K devices.\n" , - __FUNCTION__); +printf ("%s: No support for ACEX1K devices.\n" , + __func__);#endif break ;#if defined(CONFIG_FPGA_STRATIX_II )case Altera_StratixII: -PRINTF ("%s: Launching the Stratix II Loader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the Stratix II Loader...\n" , + __func__); ret_val =StratixII_load (desc, buf, bsize);break ;#endif default : -printf ("%s: Unsupported family type, %d\n" , - __FUNCTION__, desc->family); +printf ("%s: Unsupported family type, %d\n" , + __func__, desc->family); } }@@ -72,31 +69,33 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) {int ret_val =FPGA_FAIL ;/* assume a failure */ -if (!altera_validate (desc, (char *)__FUNCTION__)) { -printf ("%s: Invalid device descriptor\n" , __FUNCTION__); +if (!altera_validate (desc, (char *)__func__)) { +printf ("%s: Invalid device descriptor\n" , __func__); }else {switch (desc->family) {case Altera_ACEX1K:#if defined(CONFIG_FPGA_ACEX ) -PRINTF ("%s: Launching the ACEX1K Reader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the ACEX1K Reader...\n" , + __func__); ret_val =ACEX1K_dump (desc, buf, bsize);#else -printf ("%s: No support for ACEX1K devices.\n" , - __FUNCTION__); +printf ("%s: No support for ACEX1K devices.\n" , + __func__);#endif break ;#if defined(CONFIG_FPGA_STRATIX_II )case Altera_StratixII: -PRINTF ("%s: Launching the Stratix II Reader...\n" , - __FUNCTION__); +debug_cond (FPGA_DEBUG , +"%s: Launching the Stratix II Reader...\n" , + __func__); ret_val =StratixII_dump (desc, buf, bsize);break ;#endif default : -printf ("%s: Unsupported family type, %d\n" , - __FUNCTION__, desc->family); +printf ("%s: Unsupported family type, %d\n" , + __func__, desc->family); } }@@ -107,42 +106,42 @@ int altera_info( Altera_desc *desc ) {int ret_val =FPGA_FAIL ; -if (altera_validate (desc, (char *)__FUNCTION__)) { -printf ("Family: \t" ); +if (altera_validate (desc, (char *)__func__)) { +printf ("Family: \t" );switch (desc->family) {case Altera_ACEX1K: -printf ("ACEX1K\n" ); +printf ("ACEX1K\n" );break ;case Altera_CYC2: -printf ("CYCLON II\n" ); +printf ("CYCLON II\n" );break ;case Altera_StratixII: -printf ("Stratix II\n" ); +printf ("Stratix II\n" );break ;/* Add new family types here */ default : -printf ("Unknown family type, %d\n" , desc->family); +printf ("Unknown family type, %d\n" , desc->family); } -printf ("Interface type:\t" ); +printf ("Interface type:\t" );switch (desc->iface) {case passive_serial: -printf ("Passive Serial (PS)\n" ); +printf ("Passive Serial (PS)\n" );break ;case passive_parallel_synchronous: -printf ("Passive Parallel Synchronous (PPS)\n" ); +printf ("Passive Parallel Synchronous (PPS)\n" );break ;case passive_parallel_asynchronous: -printf ("Passive Parallel Asynchronous (PPA)\n" ); +printf ("Passive Parallel Asynchronous (PPA)\n" );break ;case passive_serial_asynchronous: -printf ("Passive Serial Asynchronous (PSA)\n" ); +printf ("Passive Serial Asynchronous (PSA)\n" );break ;case altera_jtag_mode:/* Not used */ -printf ("JTAG Mode\n" ); +printf ("JTAG Mode\n" );break ;case fast_passive_parallel: -printf ("Fast Passive Parallel (FPP)\n" ); +printf ("Fast Passive Parallel (FPP)\n" );break ;case fast_passive_parallel_security: printf@@ -150,31 +149,31 @@ int altera_info( Altera_desc *desc )break ;/* Add new interface types here */ default : -printf ("Unsupported interface type, %d\n" , desc->iface); +printf ("Unsupported interface type, %d\n" , desc->iface); }printf ("Device Size: \t%zd bytes\n" -"Cookie: \t0x%x (%d)\n" , - desc->size, desc->cookie, desc->cookie); +"Cookie: \t0x%x (%d)\n" , + desc->size, desc->cookie, desc->cookie);if (desc->iface_fns) { -printf ("Device Function Table @ 0x%p\n" , desc->iface_fns); +printf ("Device Function Table @ 0x%p\n" , desc->iface_fns);switch (desc->family) {case Altera_ACEX1K:case Altera_CYC2:#if defined(CONFIG_FPGA_ACEX1K ) -ACEX1K_info (desc); +ACEX1K_info (desc);#elif defined(CONFIG_FPGA_CYCLON2 ) -CYC2_info (desc); +CYC2_info (desc);#else /* just in case */ -printf ("%s: No support for ACEX1K devices.\n" , - __FUNCTION__); +printf ("%s: No support for ACEX1K devices.\n" , + __func__);#endif break ;#if defined(CONFIG_FPGA_STRATIX_II )case Altera_StratixII: -StratixII_info (desc); +StratixII_info (desc);break ;#endif /* Add new family types here */ @@ -183,12 +182,12 @@ int altera_info( Altera_desc *desc )break ; } }else { -printf ("No Device Function Table.\n" ); +printf ("No Device Function Table.\n" ); } ret_val =FPGA_SUCCESS ; }else { -printf ("%s: Invalid device descriptor\n" , __FUNCTION__); +printf ("%s: Invalid device descriptor\n" , __func__); }return ret_val;@@ -208,17 +207,17 @@ static int altera_validate (Altera_desc * desc, const char *fn)if (desc->size) { ret_val = true; }else { -printf ("%s: NULL part size\n" , fn); +printf ("%s: NULL part size\n" , fn); } }else { -printf ("%s: Invalid Interface type, %d\n" , - fn, desc->iface); +printf ("%s: Invalid Interface type, %d\n" , + fn, desc->iface); }
drivers/fpga/altera.c static int altera_validate (Altera_desc * desc, const char *fn) · line 223
Quoted 10 lines
drivers/fpga/altera.c +2
-2}else { -printf ("%s: Invalid family type, %d\n" , fn, desc->family); +printf ("%s: Invalid family type, %d\n" , fn, desc->family); } }else { -printf ("%s: NULL descriptor!\n" , fn); +printf ("%s: NULL descriptor!\n" , fn); }return ret_val;
WARNING: space prohibited between function name and open parenthesis '(' #113: FILE: drivers/fpga/altera.c:29:
+ if (!altera_validate (desc, (char *)__func__)) {
WARNING: space prohibited between function name and open parenthesis '(' #165: FILE: drivers/fpga/altera.c:72:
+ if (!altera_validate (desc, (char *)__func__)) {
WARNING: space prohibited between function name and open parenthesis '(' #209: FILE: drivers/fpga/altera.c:109:
+ if (altera_validate (desc, (char *)__func__)) {
WARNING: line over 80 characters
#275: FILE: drivers/fpga/altera.c:160:
+ printf("Device Function Table @ 0x%p\n", desc->iface_fns);
CHECK: Alignment should match open parenthesis
#290: FILE: drivers/fpga/altera.c:171:
+ printf("%s: No support for ACEX1K devices.\n",
+ __func__);
WARNING: line over 80 characters
#330: FILE: drivers/fpga/altera.c:217:
+ printf("%s: Invalid family type, %d\n", fn, desc->family);
M
Signature · 14 lines
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: OpenPGP digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140924/47e246ac/attachment.pgp>
PATCH 27/51 fpga: altera: Clean up the printing and debug
Quoted 11 lines · Michal Simek
Quoted 10 lines · Marek Vasut
Clean up the
printf()statements and get rid of thePRINTF()macro by replacing it withdebug_cond().Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>
[...]
Quoted 26 lines
WARNING: space prohibited between function name and open parenthesis '(' #113: FILE:
drivers/fpga/altera.c:29:(quoted diff) +1
-0+ if (!altera_validate (desc, (char *)__func__)) {WARNING: space prohibited between function name and open parenthesis '(' #165: FILE:
drivers/fpga/altera.c:72:(quoted diff) +1
-0+ if (!altera_validate (desc, (char *)__func__)) {WARNING: space prohibited between function name and open parenthesis '(' #209: FILE:
drivers/fpga/altera.c:109:drivers/fpga/altera.c +1
-0+if (altera_validate (desc, (char *)__func__)) {WARNING: line over 80 characters
#275: FILE:drivers/fpga/altera.c:160:(quoted diff) +1
-0+ printf("Device Function Table @ 0x%p\n", desc-
iface_fns);CHECK: Alignment should match open parenthesis
#290: FILE:drivers/fpga/altera.c:171:(quoted diff) +2
-0+ printf("%s: No support for ACEX1K devices.\n", + __func__);WARNING: line over 80 characters
#330: FILE:drivers/fpga/altera.c:217:(quoted diff) +1
-0+ printf("%s: Invalid family type, %d\n", fn, desc-
Quoted 1 line
family);
The patch does not address this issue, this is addressed by one of the patches further down the pipe (but it is addressed). I tried to keep these patches somewhat separated to keep the changes reasonably contained, but the file was a mess. The best suggestion I can give you is to use checkpatch -f on the resulting altera.c file ; there are still a few warnings, but it's much better than it was.
Best regards,
Marek Vasut
PATCH 28/51 fpga: altera: Clean up altera_validate function
In reply to Marek VasutBoldly go, where no programmer has gone before and just clean up the indentation mayhem. No functional change.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- drivers/fpga/altera.c | 43 +++++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 22 deletions(-)
drivers/fpga/altera.c +21 -22
@@ -195,32 +195,31 @@ int altera_info( Altera_desc *desc )/* ------------------------------------------------------------------------- */ -static int altera_validate (Altera_desc * desc,const char *fn) +static int altera_validate (Altera_desc *desc,const char *fn) { -int ret_val = false; - -if (desc) { -if ((desc->family > min_altera_type) && - (desc->family < max_altera_type)) { -if ((desc->iface > min_altera_iface_type) && - (desc->iface < max_altera_iface_type)) { -if (desc->size) { - ret_val = true; - }else { -printf ("%s: NULL part size\n" , fn); - } - }else { -printf ("%s: Invalid Interface type, %d\n" , - fn, desc->iface); - } - }else { -printf ("%s: Invalid family type, %d\n" , fn, desc->family); - } - }else { +if (!desc) {printf ("%s: NULL descriptor!\n" , fn); +return false; } -return ret_val; +if ((desc->family < min_altera_type) || + (desc->family > max_altera_type)) { +printf ("%s: Invalid family type, %d\n" , fn, desc->family); +return false; + } + +if ((desc->iface < min_altera_iface_type) || + (desc->iface > max_altera_iface_type)) { +printf ("%s: Invalid Interface type, %d\n" , fn, desc->iface); +return false; + } + +if (!desc->size) { +printf ("%s: NULL part size\n" , fn); +return false; + } + +return true; }/* ------------------------------------------------------------------------- */
Signature · 1 line
2.0.0
PATCH 29/51 fpga: altera: More indentation trimdown
Further improve the indentation in the rest of the file, where the indentation is initially a bit less brutal. There is no functional change in this patch.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- drivers/fpga/altera.c | 238 +++++++++++++++++++++++++------------------------- 1 file changed, 120 insertions(+), 118 deletions(-)
drivers/fpga/altera.c +120 -118
@@ -26,40 +26,41 @@ int altera_load(Altera_desc *desc, const void *buf, size_t bsize) {int ret_val =FPGA_FAIL ;/* assume a failure */ -if (!altera_validate (desc, (char *)__func__)) { +if (!altera_validate (desc, (char *)__func__)) {printf ("%s: Invalid device descriptor\n" , __func__); - }else { -switch (desc->family) { -case Altera_ACEX1K: -case Altera_CYC2: +return FPGA_FAIL ; + } + +switch (desc->family) { +case Altera_ACEX1K: +case Altera_CYC2:#if defined(CONFIG_FPGA_ACEX1K ) -debug_cond (FPGA_DEBUG , -"%s: Launching the ACEX1K Loader...\n" , - __func__); - ret_val =ACEX1K_load (desc, buf, bsize); +debug_cond (FPGA_DEBUG , +"%s: Launching the ACEX1K Loader...\n" , + __func__); + ret_val =ACEX1K_load (desc, buf, bsize);#elif defined(CONFIG_FPGA_CYCLON2 ) -debug_cond (FPGA_DEBUG , -"%s: Launching the CYCLONE II Loader...\n" , - __func__); - ret_val =CYC2_load (desc, buf, bsize); +debug_cond (FPGA_DEBUG , +"%s: Launching the CYCLONE II Loader...\n" , + __func__); + ret_val =CYC2_load (desc, buf, bsize);#else -printf ("%s: No support for ACEX1K devices.\n" , - __func__); +printf ("%s: No support for ACEX1K devices.\n" , + __func__);#endif -break ; +break ;#if defined(CONFIG_FPGA_STRATIX_II ) -case Altera_StratixII: -debug_cond (FPGA_DEBUG , -"%s: Launching the Stratix II Loader...\n" , - __func__); - ret_val =StratixII_load (desc, buf, bsize); -break ; +case Altera_StratixII: +debug_cond (FPGA_DEBUG , +"%s: Launching the Stratix II Loader...\n" , + __func__); + ret_val =StratixII_load (desc, buf, bsize); +break ;#endif -default : -printf ("%s: Unsupported family type, %d\n" , - __func__, desc->family); - } +default : +printf ("%s: Unsupported family type, %d\n" , + __func__, desc->family); }return ret_val;
@@ -71,125 +72,126 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)if (!altera_validate (desc, (char *)__func__)) {printf ("%s: Invalid device descriptor\n" , __func__); - }else { -switch (desc->family) { -case Altera_ACEX1K: +return FPGA_FAIL ; + } + +switch (desc->family) { +case Altera_ACEX1K:#if defined(CONFIG_FPGA_ACEX ) -debug_cond (FPGA_DEBUG , -"%s: Launching the ACEX1K Reader...\n" , - __func__); - ret_val =ACEX1K_dump (desc, buf, bsize); +debug_cond (FPGA_DEBUG , +"%s: Launching the ACEX1K Reader...\n" , + __func__); + ret_val =ACEX1K_dump (desc, buf, bsize);#else -printf ("%s: No support for ACEX1K devices.\n" , - __func__); +printf ("%s: No support for ACEX1K devices.\n" , + __func__);#endif -break ; +break ;#if defined(CONFIG_FPGA_STRATIX_II ) -case Altera_StratixII: -debug_cond (FPGA_DEBUG , -"%s: Launching the Stratix II Reader...\n" , - __func__); - ret_val =StratixII_dump (desc, buf, bsize); -break ; +case Altera_StratixII: +debug_cond (FPGA_DEBUG , +"%s: Launching the Stratix II Reader...\n" , + __func__); + ret_val =StratixII_dump (desc, buf, bsize); +break ;#endif -default : -printf ("%s: Unsupported family type, %d\n" , - __func__, desc->family); - } +default : +printf ("%s: Unsupported family type, %d\n" , + __func__, desc->family); }return ret_val; } -int altera_info (Altera_desc *desc ) +int altera_info (Altera_desc *desc) {int ret_val =FPGA_FAIL ; -if (altera_validate (desc, (char *)__func__)) { -printf ("Family: \t" ); -switch (desc->family) { -case Altera_ACEX1K: -printf ("ACEX1K\n" ); -break ; -case Altera_CYC2: -printf ("CYCLON II\n" ); -break ; -case Altera_StratixII: -printf ("Stratix II\n" ); -break ; -/* Add new family types here */ -default : -printf ("Unknown family type, %d\n" , desc->family); - } +if (!altera_validate (desc, (char *)__func__)) { +printf ("%s: Invalid device descriptor\n" , __func__); +return FPGA_FAIL ; + } -printf ("Interface type:\t" ); -switch (desc->iface) { -case passive_serial: -printf ("Passive Serial (PS)\n" ); -break ; -case passive_parallel_synchronous: -printf ("Passive Parallel Synchronous (PPS)\n" ); -break ; -case passive_parallel_asynchronous: -printf ("Passive Parallel Asynchronous (PPA)\n" ); -break ; -case passive_serial_asynchronous: -printf ("Passive Serial Asynchronous (PSA)\n" ); -break ; -case altera_jtag_mode:/* Not used */ -printf ("JTAG Mode\n" ); -break ; -case fast_passive_parallel: -printf ("Fast Passive Parallel (FPP)\n" ); -break ; -case fast_passive_parallel_security: -printf - ("Fast Passive Parallel with Security (FPPS) \n" ); -break ; -/* Add new interface types here */ -default : -printf ("Unsupported interface type, %d\n" , desc->iface); - } +printf ("Family: \t" ); +switch (desc->family) { +case Altera_ACEX1K: +printf ("ACEX1K\n" ); +break ; +case Altera_CYC2: +printf ("CYCLON II\n" ); +break ; +case Altera_StratixII: +printf ("Stratix II\n" ); +break ; +/* Add new family types here */ +default : +printf ("Unknown family type, %d\n" , desc->family); + } -printf ("Device Size: \t%zd bytes\n" -"Cookie: \t0x%x (%d)\n" , - desc->size, desc->cookie, desc->cookie); +printf ("Interface type:\t" ); +switch (desc->iface) { +case passive_serial: +printf ("Passive Serial (PS)\n" ); +break ; +case passive_parallel_synchronous: +printf ("Passive Parallel Synchronous (PPS)\n" ); +break ; +case passive_parallel_asynchronous: +printf ("Passive Parallel Asynchronous (PPA)\n" ); +break ; +case passive_serial_asynchronous: +printf ("Passive Serial Asynchronous (PSA)\n" ); +break ; +case altera_jtag_mode:/* Not used */ +printf ("JTAG Mode\n" ); +break ; +case fast_passive_parallel: +printf ("Fast Passive Parallel (FPP)\n" ); +break ; +case fast_passive_parallel_security: +printf ("Fast Passive Parallel with Security (FPPS)\n" ); +break ; +/* Add new interface types here */ +default : +printf ("Unsupported interface type, %d\n" , desc->iface); + } + +printf ("Device Size: \t%zd bytes\n" +"Cookie: \t0x%x (%d)\n" , + desc->size, desc->cookie, desc->cookie); -if (desc->iface_fns) { -printf ("Device Function Table @ 0x%p\n" , desc->iface_fns); -switch (desc->family) { -case Altera_ACEX1K: -case Altera_CYC2: +if (desc->iface_fns) { +printf ("Device Function Table @ 0x%p\n" , desc->iface_fns); +switch (desc->family) { +case Altera_ACEX1K: +case Altera_CYC2:#if defined(CONFIG_FPGA_ACEX1K ) -ACEX1K_info (desc); +ACEX1K_info (desc);#elif defined(CONFIG_FPGA_CYCLON2 ) -CYC2_info (desc); +CYC2_info (desc);#else -/* just in case */ -printf ("%s: No support for ACEX1K devices.\n" , - __func__); +/* just in case */ +printf ("%s: No support for ACEX1K devices.\n" , + __func__);#endif -break ; +break ;#if defined(CONFIG_FPGA_STRATIX_II ) -case Altera_StratixII: -StratixII_info (desc); -break ; +case Altera_StratixII: +StratixII_info (desc); +break ;#endif -/* Add new family types here */ -default : -/* we don't need a message here - we give one up above */ -break ; - } - }else { -printf ("No Device Function Table.\n" ); +/* Add new family types here */ +default : +/* we don't need a message here - we give one up above */ +break ; } - - ret_val =FPGA_SUCCESS ; }else { -printf ("%s: Invalid device descriptor\n" , __func__); +printf ("No Device Function Table.\n" ); } + ret_val =FPGA_SUCCESS ; +return ret_val; }
Signature · 1 line
2.0.0
PATCH 30/51 fpga: altera: Move altera_validate to the top
In reply to Marek VasutMove the function to the top of the file to avoid forward declaration. No functional change.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- drivers/fpga/altera.c | 58 +++++++++++++++++++++++---------------------------- 1 file changed, 26 insertions(+), 32 deletions(-)
drivers/fpga/altera.c +26 -32
@@ -19,7 +19,32 @@#define FPGA_DEBUG 0/* Local Static Functions */ -static int altera_validate (Altera_desc * desc,const char *fn); +static int altera_validate (Altera_desc *desc,const char *fn) +{ +if (!desc) { +printf ("%s: NULL descriptor!\n" , fn); +return false; + } + +if ((desc->family < min_altera_type) || + (desc->family > max_altera_type)) { +printf ("%s: Invalid family type, %d\n" , fn, desc->family); +return false; + } + +if ((desc->iface < min_altera_iface_type) || + (desc->iface > max_altera_iface_type)) { +printf ("%s: Invalid Interface type, %d\n" , fn, desc->iface); +return false; + } + +if (!desc->size) { +printf ("%s: NULL part size\n" , fn); +return false; + } + +return true; +}/* ------------------------------------------------------------------------- */ int altera_load (Altera_desc *desc,const void *buf,size_t bsize)
@@ -194,34 +219,3 @@ int altera_info(Altera_desc *desc)return ret_val; } - -/* ------------------------------------------------------------------------- */ - -static int altera_validate (Altera_desc *desc,const char *fn) -{ -if (!desc) { -printf ("%s: NULL descriptor!\n" , fn); -return false; - } - -if ((desc->family < min_altera_type) || - (desc->family > max_altera_type)) { -printf ("%s: Invalid family type, %d\n" , fn, desc->family); -return false; - } - -if ((desc->iface < min_altera_iface_type) || - (desc->iface > max_altera_iface_type)) { -printf ("%s: Invalid Interface type, %d\n" , fn, desc->iface); -return false; - } - -if (!desc->size) { -printf ("%s: NULL part size\n" , fn); -return false; - } - -return true; -} - -/* ------------------------------------------------------------------------- */
Signature · 1 line
2.0.0
PATCH 31/51 fpga: altera: Make altera_validate return normal values
In reply to Marek VasutMake the function return either 0 or -EINVAL, that is, normal expected error codes and success codes instead of true/false nonsense.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- drivers/fpga/altera.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
drivers/fpga/altera.c +9 -9
@@ -12,38 +12,38 @@* Altera FPGA support */ #include <common.h> +#include <errno.h> #include <ACEX1K.h> #include <stratixII.h> /* Define FPGA_DEBUG to 1 to get debug printf's */ #define FPGA_DEBUG 0 -/* Local Static Functions */ static int altera_validate (Altera_desc *desc,const char *fn) {if (!desc) {printf ("%s: NULL descriptor!\n" , fn); -return false; +return -EINVAL ; }if ((desc->family < min_altera_type) || (desc->family > max_altera_type)) {printf ("%s: Invalid family type, %d\n" , fn, desc->family); -return false; +return -EINVAL ; }if ((desc->iface < min_altera_iface_type) || (desc->iface > max_altera_iface_type)) {printf ("%s: Invalid Interface type, %d\n" , fn, desc->iface); -return false; +return -EINVAL ; }if (!desc->size) {printf ("%s: NULL part size\n" , fn); -return false; +return -EINVAL ; } -return true; +return 0 ; }/* ------------------------------------------------------------------------- */
@@ -51,7 +51,7 @@ int altera_load(Altera_desc *desc, const void *buf, size_t bsize) {int ret_val =FPGA_FAIL ;/* assume a failure */ -if (!altera_validate (desc, (char *)__func__)) { +if (altera_validate (desc, (char *)__func__)) {printf ("%s: Invalid device descriptor\n" , __func__);return FPGA_FAIL ; }
@@ -95,7 +95,7 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) {int ret_val =FPGA_FAIL ;/* assume a failure */ -if (!altera_validate (desc, (char *)__func__)) { +if (altera_validate (desc, (char *)__func__)) {printf ("%s: Invalid device descriptor\n" , __func__);return FPGA_FAIL ; }
@@ -133,7 +133,7 @@ int altera_info(Altera_desc *desc) {int ret_val =FPGA_FAIL ; -if (!altera_validate (desc, (char *)__func__)) { +if (altera_validate (desc, (char *)__func__)) {printf ("%s: Invalid device descriptor\n" , __func__);return FPGA_FAIL ; }
Signature · 1 line
2.0.0
PATCH 31/51 fpga: altera: Make altera_validate return normal values
Quoted 10 lines · Marek Vasut
Make the function return either 0 or
-EINVAL, that is, normal expected error codes and success codes instead of true/false nonsense.Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>
Acked-by Pavel Machek <[email protected]>
drivers/fpga/altera.c int altera_info(Altera_desc *desc) · line 136
Quoted 6 lines
drivers/fpga/altera.c +1
-1@@ -133,7 +133,7 @@ int altera_info(Altera_desc *desc) {int ret_val =FPGA_FAIL ; -if (!altera_validate (desc, (char *)__func__)) { +if (altera_validate (desc, (char *)__func__)) {
+ if (altera_validate(desc, (char *)__func__)) {
You have extra space there, checkpatch would be angry.
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH 31/51 fpga: altera: Make altera_validate return normal values
Quoted 18 lines · Pavel Machek
Quoted 10 lines · Marek Vasut
Make the function return either 0 or
-EINVAL, that is, normal expected error codes and success codes instead of true/false nonsense.Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Acked-by Pavel Machek <[email protected]>Quoted 4 lines
(quoted diff) +0
-0@@ -133,7 +133,7 @@ int altera_info(Altera_desc *desc) {
Quoted 8 lines
drivers/fpga/altera.c int altera_info(Altera_desc *desc) · line 136
Quoted 4 lines
drivers/fpga/altera.c +1
-1int ret_val =FPGA_FAIL ; -if (!altera_validate (desc, (char *)__func__)) { +if (altera_validate (desc, (char *)__func__)) {+ if (
altera_validate(desc, (char *)__func__)) {You have extra space there, checkpatch would be angry.
I'm sure it will, but this was resolved somewhere down the patch stack. The final result doesn't have this warning.
Best regards,
Marek Vasut
PATCH 32/51 fpga: altera: Clean up enums in altera.h
In reply to Marek VasutGet rid of the line-over-80 problems and zap the typedef that went alongside those enums.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- include/altera.h | 76 ++++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 49 insertions(+), 27 deletions(-)
include/altera.h +49 -27
@@ -10,35 +10,57 @@#ifndef _ALTERA_H_#define _ALTERA_H_ -typedef enum {/* typedef Altera_iface */ - min_altera_iface_type,/* insert all new types after this */ - passive_serial,/* serial data and external clock */ - passive_parallel_synchronous,/* parallel data */ - passive_parallel_asynchronous,/* parallel data */ - passive_serial_asynchronous,/* serial data w/ internal clock (not used) */ - altera_jtag_mode,/* jtag/tap serial (not used ) */ - fast_passive_parallel,/* fast passive parallel (FPP) */ - fast_passive_parallel_security,/* fast passive parallel with security (FPPS) */ - max_altera_iface_type/* insert all new types before this */ -}Altera_iface ;/* end, typedef Altera_iface */ +enum altera_iface { +/* insert all new types after this */ + min_altera_iface_type, +/* serial data and external clock */ + passive_serial, +/* parallel data */ + passive_parallel_synchronous, +/* parallel data */ + passive_parallel_asynchronous, +/* serial data w/ internal clock (not used) */ + passive_serial_asynchronous, +/* jtag/tap serial (not used ) */ + altera_jtag_mode, +/* fast passive parallel (FPP) */ + fast_passive_parallel, +/* fast passive parallel with security (FPPS) */ + fast_passive_parallel_security, +/* insert all new types before this */ + max_altera_iface_type, +}; -typedef enum {/* typedef Altera_Family */ - min_altera_type,/* insert all new types after this */ - Altera_ACEX1K,/* ACEX1K Family */ - Altera_CYC2,/* CYCLONII Family */ - Altera_StratixII,/* StratixII Family */ -/* Add new models here */ - max_altera_type/* insert all new types before this */ -}Altera_Family ;/* end, typedef Altera_Family */ +enum altera_family { +/* insert all new types after this */ + min_altera_type, +/* ACEX1K Family */ + Altera_ACEX1K, +/* CYCLONII Family */ + Altera_CYC2, +/* StratixII Family */ + Altera_StratixII, -typedef struct {/* typedef Altera_desc */ -Altera_Family family;/* part type */ -Altera_iface iface;/* interface type */ -size_t size;/* bytes of data part can accept */ -void * iface_fns;/* interface function table */ -void * base;/* base interface address */ -int cookie;/* implementation specific cookie */ -}Altera_desc ;/* end, typedef Altera_desc */ +/* Add new models here */ + +/* insert all new types before this */ + max_altera_type, +}; + +typedef struct { +/* part type */ +enum altera_family family; +/* interface type */ +enum altera_iface iface; +/* bytes of data part can accept */ +size_t size; +/* interface function table */ +void *iface_fns; +/* base interface address */ +void *base; +/* implementation specific cookie */ +int cookie; +}Altera_desc ;/* Generic Altera Functions *********************************************************************/
Signature · 1 line
2.0.0
PATCH 33/51 fpga: altera: Turn the switches into table lookup
In reply to Marek VasutAdd a table of FPGA family with matching functions associated with it and make all the code just look up the family in that table and call the associated function instead of the horrible switch voodoo which was duplicated all over the place.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- drivers/fpga/altera.c | 171 ++++++++++++++++++-------------------------------- 1 file changed, 60 insertions(+), 111 deletions(-)
drivers/fpga/altera.c +60 -111
@@ -19,6 +19,26 @@/* Define FPGA_DEBUG to 1 to get debug printf's */ #define FPGA_DEBUG 0 +static const struct altera_fpga { +enum altera_family family; +const char *name; +int (*load)(Altera_desc *,const void *,size_t ); +int (*dump)(Altera_desc *,const void *,size_t ); +int (*info)(Altera_desc *); +} altera_fpga[] = { +#if defined(CONFIG_FPGA_ACEX1K) + { Altera_ACEX1K,"ACEX1K" , ACEX1K_load, ACEX1K_dump, ACEX1K_info }, + { Altera_CYC2,"ACEX1K" , ACEX1K_load, ACEX1K_dump, ACEX1K_info }, +#elif defined(CONFIG_FPGA_CYCLON2) + { Altera_ACEX1K,"CycloneII" , CYC2_load, CYC2_dump, CYC2_info }, + { Altera_CYC2,"CycloneII" , CYC2_load, CYC2_dump, CYC2_info }, +#endif +#if defined(CONFIG_FPGA_STRATIX_II) + { Altera_StratixII,"StratixII" , StratixII_load, + StratixII_dump, StratixII_info }, +#endif +}; +static int altera_validate (Altera_desc *desc,const char *fn) {if (!desc) {
@@ -46,113 +66,65 @@ static int altera_validate(Altera_desc *desc, const char *fn)return 0 ; } -/* ------------------------------------------------------------------------- */ -int altera_load (Altera_desc *desc,const void *buf,size_t bsize) +static const struct altera_fpga * +altera_desc_to_fpga (Altera_desc *desc,const char *fn) { -int ret_val =FPGA_FAIL ;/* assume a failure */ +int i; -if (altera_validate (desc, (char *)__func__)) { -printf ("%s: Invalid device descriptor\n" , __func__); -return FPGA_FAIL ; +if (altera_validate (desc, fn)) { +printf ("%s: Invalid device descriptor\n" , fn); +return NULL ; } -switch (desc->family) { -case Altera_ACEX1K: -case Altera_CYC2: -#if defined(CONFIG_FPGA_ACEX1K ) -debug_cond (FPGA_DEBUG , -"%s: Launching the ACEX1K Loader...\n" , - __func__); - ret_val =ACEX1K_load (desc, buf, bsize); -#elif defined(CONFIG_FPGA_CYCLON2 ) -debug_cond (FPGA_DEBUG , -"%s: Launching the CYCLONE II Loader...\n" , - __func__); - ret_val =CYC2_load (desc, buf, bsize); -#else -printf ("%s: No support for ACEX1K devices.\n" , - __func__); -#endif -break ; +for (i =0 ; i <ARRAY_SIZE (altera_fpga); i++) { +if (desc->family == altera_fpga[i].family) +break ; + } -#if defined(CONFIG_FPGA_STRATIX_II ) -case Altera_StratixII: -debug_cond (FPGA_DEBUG , -"%s: Launching the Stratix II Loader...\n" , - __func__); - ret_val =StratixII_load (desc, buf, bsize); -break ; -#endif -default : -printf ("%s: Unsupported family type, %d\n" , - __func__, desc->family); +if (i ==ARRAY_SIZE (altera_fpga)) { +printf ("%s: Unsupported family type, %d\n" , fn, desc->family); +return NULL ; } -return ret_val; +return &altera_fpga[i]; } -int altera_dump (Altera_desc *desc,const void *buf,size_t bsize) +int altera_load (Altera_desc *desc,const void *buf,size_t bsize) { -int ret_val =FPGA_FAIL ;/* assume a failure */ +const struct altera_fpga *fpga =altera_desc_to_fpga (desc, __func__); -if (altera_validate (desc, (char *)__func__)) { -printf ("%s: Invalid device descriptor\n" , __func__); +if (!fpga)return FPGA_FAIL ; - } -switch (desc->family) { -case Altera_ACEX1K: -#if defined(CONFIG_FPGA_ACEX ) -debug_cond (FPGA_DEBUG , -"%s: Launching the ACEX1K Reader...\n" , - __func__); - ret_val =ACEX1K_dump (desc, buf, bsize); -#else -printf ("%s: No support for ACEX1K devices.\n" , - __func__); -#endif -break ; +debug_cond (FPGA_DEBUG ,"%s: Launching the %s Loader...\n" , + __func__, fpga->name); +if (fpga->load) +return fpga->load (desc, buf, bsize); +return 0 ; +} -#if defined(CONFIG_FPGA_STRATIX_II ) -case Altera_StratixII: -debug_cond (FPGA_DEBUG , -"%s: Launching the Stratix II Reader...\n" , - __func__); - ret_val =StratixII_dump (desc, buf, bsize); -break ; -#endif -default : -printf ("%s: Unsupported family type, %d\n" , - __func__, desc->family); - } +int altera_dump (Altera_desc *desc,const void *buf,size_t bsize) +{ +const struct altera_fpga *fpga =altera_desc_to_fpga (desc, __func__); -return ret_val; +if (!fpga) +return FPGA_FAIL ; + +debug_cond (FPGA_DEBUG ,"%s: Launching the %s Reader...\n" , + __func__, fpga->name); +if (fpga->dump) +return fpga->dump (desc, buf, bsize); +return 0 ; }int altera_info (Altera_desc *desc) { -int ret_val =FPGA_FAIL ; +const struct altera_fpga *fpga =altera_desc_to_fpga (desc, __func__); -if (altera_validate (desc, (char *)__func__)) { -printf ("%s: Invalid device descriptor\n" , __func__); +if (!fpga)return FPGA_FAIL ; - } -printf ("Family: \t" ); -switch (desc->family) { -case Altera_ACEX1K: -printf ("ACEX1K\n" ); -break ; -case Altera_CYC2: -printf ("CYCLON II\n" ); -break ; -case Altera_StratixII: -printf ("Stratix II\n" ); -break ; -/* Add new family types here */ -default : -printf ("Unknown family type, %d\n" , desc->family); - } +printf ("Family: \t%s\n" , fpga->name);printf ("Interface type:\t" );switch (desc->iface) {
@@ -188,34 +160,11 @@ int altera_info(Altera_desc *desc)if (desc->iface_fns) {printf ("Device Function Table @ 0x%p\n" , desc->iface_fns); -switch (desc->family) { -case Altera_ACEX1K: -case Altera_CYC2: -#if defined(CONFIG_FPGA_ACEX1K ) -ACEX1K_info (desc); -#elif defined(CONFIG_FPGA_CYCLON2 ) -CYC2_info (desc); -#else -/* just in case */ -printf ("%s: No support for ACEX1K devices.\n" , - __func__); -#endif -break ; -#if defined(CONFIG_FPGA_STRATIX_II ) -case Altera_StratixII: -StratixII_info (desc); -break ; -#endif -/* Add new family types here */ -default : -/* we don't need a message here - we give one up above */ -break ; - } +if (fpga->info) + fpga->info (desc); }else {printf ("No Device Function Table.\n" ); } - ret_val =FPGA_SUCCESS ; - -return ret_val; +return FPGA_SUCCESS ; }
Signature · 1 line
2.0.0
PATCH v2 34/51 arm: socfpga: fpga: Add SoCFPGA FPGA programming interface
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/Makefile | 3 +- arch/arm/cpu/armv7/socfpga/fpga_manager.c | 78 ++++++ arch/arm/cpu/armv7/socfpga/misc.c | 37 +++ arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 ++++++ drivers/fpga/Makefile | 1 + drivers/fpga/altera.c | 3 + drivers/fpga/socfpga.c | 301 +++++++++++++++++++++++ include/altera.h | 6 + 8 files changed, 505 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/fpga_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/fpga_manager.h create mode 100644 drivers/fpga/socfpga.c
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
arch/arm/cpu/armv7/socfpga/Makefile +2 -1
@@ -8,5 +8,6 @@ # obj-y := lowlevel_init.o -obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o +obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ + fpga_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
arch/arm/cpu/armv7/socfpga/fpga_manager.c new file +78 -0
78 lines not on this page · raw message
arch/arm/cpu/armv7/socfpga/misc.c +37 -0
@@ -6,6 +6,7 @@#include <common.h> #include <asm/io.h> +#include <altera.h> #include <miiphy.h> #include <netdev.h> #include <asm/arch/reset_manager.h>
@@ -93,8 +94,44 @@ int overwrite_console(void) }#endif +#ifdef CONFIG_FPGA +/* +* FPGA programming support for SoC FPGA Cyclone V +*/ +static Altera_desc altera_fpga[] = { + { +/* Family */ + Altera_SoCFPGA, +/* Interface type */ + fast_passive_parallel, +/* No limitation as additional data will be ignored */ +-1 , +/* No device function table */ +NULL , +/* Base interface address specified in driver */ +NULL , +/* No cookie implementation */ +0 + }, +}; + +/* add device descriptor to FPGA device table */ +static void socfpga_fpga_add (void ) +{ +int i; +fpga_init (); +for (i =0 ; i <ARRAY_SIZE (altera_fpga); i++) +fpga_add (fpga_altera, &altera_fpga[i]); +} +#else +static inline void socfpga_fpga_add (void ) {} +#endif +int misc_init_r (void ) { +/* Add device descriptor to FPGA device table */ +socfpga_fpga_add (); +/* * If the HW watchdog is NOT enabled, make sure it is not running, * for example because it was enabled in the preloader. This might
arch/arm/include/asm/arch-socfpga/fpga_manager.h new file +77 -0
77 lines not on this page · raw message
drivers/fpga/Makefile +1 -0
@@ -17,4 +17,5 @@ obj-y += altera.o obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o +obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o endif
drivers/fpga/altera.c +3 -0
@@ -37,6 +37,9 @@ static const struct altera_fpga { { Altera_StratixII, "StratixII", StratixII_load, StratixII_dump, StratixII_info }, #endif +#if defined(CONFIG_FPGA_SOCFPGA) + { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, +#endif }; static int altera_validate(Altera_desc *desc, const char *fn)
drivers/fpga/socfpga.c new file +301 -0
301 lines not on this page · raw message
include/altera.h +6 -0
@@ -40,6 +40,8 @@ enum altera_family { Altera_CYC2,/* StratixII Family */ Altera_StratixII, +/* SoCFPGA Family */ + Altera_SoCFPGA,/* Add new models here */
@@ -91,4 +93,8 @@ typedef struct { Altera_post_fn post; } altera_board_specific_func; +#ifdef CONFIG_FPGA_SOCFPGA +int socfpga_load (Altera_desc *desc,const void *rbf_data,size_t rbf_size); +#endif +#endif /* _ALTERA_H_ */
Signature · 1 line
2.0.0
PATCH 35/51 arm: socfpga: reset: Add function to reset FPGA bridges
In reply to Marek VasutAdd function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/reset_manager.c | 38 +++++++++++++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 2 ++ 2 files changed, 40 insertions(+)
arch/arm/cpu/armv7/socfpga/reset_manager.c +38 -0
@@ -8,6 +8,7 @@#include <common.h> #include <asm/io.h> #include <asm/arch/reset_manager.h> +#include <asm/arch/fpga_manager.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -50,6 +51,43 @@ void reset_deassert_peripherals_handoff(void)writel (0 , &reset_manager_base->per_mod_reset); } +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET ) +void socfpga_bridges_reset (int enable) +{ +/* For SoCFPGA-VT, this is NOP. */ +} +#else + +#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 +#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 +#define L3REGS_REMAP_OCRAM_MASK 0x01 + +void socfpga_bridges_reset (int enable) +{ +const uint32_t l3mask =L3REGS_REMAP_LWHPS2FPGA_MASK | +L3REGS_REMAP_HPS2FPGA_MASK | +L3REGS_REMAP_OCRAM_MASK ; + +if (enable) { +/* brdmodrst */ +writel (0xffffffff , &reset_manager_base->brg_mod_reset); + }else { +/* Check signal from FPGA. */ +if (fpgamgr_poll_fpga_ready ()) { +/* FPGA not ready. Wait for watchdog timeout. */ +printf ("%s: fpga not ready, hanging.\n" , __func__); +hang (); + } + +/* brdmodrst */ +writel (0 , &reset_manager_base->brg_mod_reset); + +/* Remap the bridges into memory map */ +writel (l3mask,SOCFPGA_L3REGS_ADDRESS ); + } +} +#endif +/* Change the reset state for EMAC 0 and EMAC 1 */ void socfpga_emac_reset (int enable) {
arch/arm/include/asm/arch-socfpga/reset_manager.h +2 -0
@@ -10,6 +10,8 @@void reset_cpu (ulong addr);void reset_deassert_peripherals_handoff (void ); +void socfpga_bridges_reset (int enable); +void socfpga_emac_reset (int enable);void socfpga_watchdog_reset (void );
Signature · 1 line
2.0.0
PATCH 36/51 arm: socfpga: sysmgr: Add FPGA bits into system manager
In reply to Marek VasutAdd missing system manager bits from Altera U-Boot to make the code comparable. These are the bits which depend on the FPGA manager.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/system_manager.c | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
arch/arm/cpu/armv7/socfpga/system_manager.c +39 -0
@@ -15,6 +15,43 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ;/* +* Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. +* The value is not wrote to SYSMGR.FPGAINTF.MODULE but +* CONFIG_SYSMGR_ISWGRP_HANDOFF. +*/ +static void populate_sysmgr_fpgaintf_module (void ) +{ +uint32_t handoff_val =0 ; + +/* ISWGRP_HANDOFF_FPGAINTF */ +writel (0 , &sysmgr_regs->iswgrp_handoff[2 ]); + +/* Enable the signal for those HPS peripherals that use FPGA. */ +if (readl (&sysmgr_regs->nandusefpga) ==SYSMGR_FPGAINTF_USEFPGA ) + handoff_val |=SYSMGR_FPGAINTF_NAND ; +if (readl (&sysmgr_regs->rgmii1usefpga) ==SYSMGR_FPGAINTF_USEFPGA ) + handoff_val |=SYSMGR_FPGAINTF_EMAC1 ; +if (readl (&sysmgr_regs->sdmmcusefpga) ==SYSMGR_FPGAINTF_USEFPGA ) + handoff_val |=SYSMGR_FPGAINTF_SDMMC ; +if (readl (&sysmgr_regs->rgmii0usefpga) ==SYSMGR_FPGAINTF_USEFPGA ) + handoff_val |=SYSMGR_FPGAINTF_EMAC0 ; +if (readl (&sysmgr_regs->spim0usefpga) ==SYSMGR_FPGAINTF_USEFPGA ) + handoff_val |=SYSMGR_FPGAINTF_SPIM0 ; +if (readl (&sysmgr_regs->spim1usefpga) ==SYSMGR_FPGAINTF_USEFPGA ) + handoff_val |=SYSMGR_FPGAINTF_SPIM1 ; + +/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE +based on pinmux setting */ +setbits_le32 (&sysmgr_regs->iswgrp_handoff[2 ], handoff_val); + + handoff_val =readl (&sysmgr_regs->iswgrp_handoff[2 ]); +if (fpgamgr_test_fpga_ready ()) { +/* Enable the required signals only */ +writel (handoff_val, &sysmgr_regs->fpgaintfgrp_module); + } +} + +/* * Configure all the pin muxes */ void sysmgr_pinmux_init (void )
@@ -26,4 +63,6 @@ void sysmgr_pinmux_init(void)writel (sys_mgr_init_table[i], regs); regs +=sizeof (regs); } + +populate_sysmgr_fpgaintf_module (); }
Signature · 1 line
2.0.0
PATCH 37/51 arm: cache: Add support for write-allocate D-Cache
In reply to Marek VasutAdd configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- arch/arm/include/asm/system.h | 1 + arch/arm/lib/cache-cp15.c | 2 ++ 2 files changed, 3 insertions(+)
arch/arm/include/asm/system.h +1 -0
@@ -185,6 +185,7 @@ enum dcache_option {DCACHE_OFF =0x12 ,DCACHE_WRITETHROUGH =0x1a ,DCACHE_WRITEBACK =0x1e , + DCACHE_WRITEALLOC = 0x16, };/* Size of an MMU section */
arch/arm/lib/cache-cp15.c +2 -0
@@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank) i++) {#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH )set_section_dcache (i,DCACHE_WRITETHROUGH ); +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC ) +set_section_dcache (i,DCACHE_WRITEALLOC );#else set_section_dcache (i,DCACHE_WRITEBACK );#endif
Signature · 1 line
2.0.0
PATCH 38/51 arm: socfpga: cache: Define cacheline size
In reply to Marek VasutThe Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- include/configs/socfpga_cyclone5.h | 2 ++ 1 file changed, 2 insertions(+)
include/configs/socfpga_cyclone5.h +2 -0
@@ -26,6 +26,8 @@#define CONFIG_SOCFPGA #define CONFIG_CLOCKS +#define CONFIG_SYS_CACHELINE_SIZE 32 +/* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x08000040
Signature · 1 line
2.0.0
PATCH 39/51 arm: socfpga: cache: Enable D-Cache
In reply to Marek VasutThe code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- board/altera/socfpga/socfpga_cyclone5.c | 1 + include/configs/socfpga_cyclone5.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)
board/altera/socfpga/socfpga_cyclone5.c +1 -0
@@ -35,6 +35,7 @@ int board_early_init_f(void)int board_init (void ) {icache_enable (); +dcache_enable ();/* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params =CONFIG_SYS_SDRAM_BASE +0x100 ;
include/configs/socfpga_cyclone5.h +1 -1
@@ -18,7 +18,6 @@#undef CONFIG_SOCFPGA_VIRTUAL_TARGET#define CONFIG_ARMV7 -#define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ#define CONFIG_MISC_INIT_R
@@ -26,6 +25,7 @@#define CONFIG_SOCFPGA #define CONFIG_CLOCKS +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32/* base address for .text section */
Signature · 1 line
2.0.0
PATCH 40/51 arm: socfpga: cache: Enable PL310 L2 cache
In reply to Marek VasutEnable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- include/configs/socfpga_cyclone5.h | 2 ++ 1 file changed, 2 insertions(+)
include/configs/socfpga_cyclone5.h +2 -0
@@ -27,6 +27,8 @@#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS/* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
Signature · 1 line
2.0.0
PATCH 41/51 arm: socfpga: scu: Add SCU register file
In reply to Marek VasutAdd the Snoop Control Unit register definition file.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- arch/arm/include/asm/arch-socfpga/scu.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/scu.h
arch/arm/include/asm/arch-socfpga/scu.h new file +23 -0
@@ -0,0 +1,23 @@ +/* +* Copyright (C) 2014 Marek Vasut <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __SOCFPGA_SCU_H__ +#define __SOCFPGA_SCU_H__ + +struct scu_registers { +u32 ctrl;/* 0x00 */ +u32 cfg; +u32 cpsr; +u32 iassr; +u32 _pad_0x10_0x3c[12 ];/* 0x10 */ +u32 fsar;/* 0x40 */ +u32 fear; +u32 _pad_0x48_0x50[2 ]; +u32 acr;/* 0x54 */ +u32 sacr; +}; + +#endif /* __SOCFPGA_SCU_H__ */
Signature · 1 line
2.0.0
PATCH 42/51 arm: socfpga: nic301: Add NIC-301 GPV register file
In reply to Marek VasutAdd register definition for the NIC-301 used on SoCFPGA.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
Acked-by Pavel Machek <[email protected]>
--- arch/arm/include/asm/arch-socfpga/nic301.h | 195 +++++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/nic301.h
arch/arm/include/asm/arch-socfpga/nic301.h new file +195 -0
@@ -0,0 +1,195 @@ +/* +* Copyright (C) 2014 Marek Vasut <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _NIC301_REGISTERS_H_ +#define _NIC301_REGISTERS_H_ + +struct nic301_registers { +u32 remap;/* 0x0 */ +/* Security Register Group */ +u32 _pad_0x4_0x8[1 ]; +u32 l4main; +u32 l4sp; +u32 l4mp;/* 0x10 */ +u32 l4osc1; +u32 l4spim; +u32 stm; +u32 lwhps2fpgaregs;/* 0x20 */ +u32 _pad_0x24_0x28[1 ]; +u32 usb1; +u32 nanddata; +u32 _pad_0x30_0x80[20 ]; +u32 usb0;/* 0x80 */ +u32 nandregs; +u32 qspidata; +u32 fpgamgrdata; +u32 hps2fpgaregs;/* 0x90 */ +u32 acp; +u32 rom; +u32 ocram; +u32 sdrdata;/* 0xA0 */ +u32 _pad_0xa4_0x1fd0[1995 ]; +/* ID Register Group */ +u32 periph_id_4;/* 0x1FD0 */ +u32 _pad_0x1fd4_0x1fe0[3 ]; +u32 periph_id_0;/* 0x1FE0 */ +u32 periph_id_1; +u32 periph_id_2; +u32 periph_id_3; +u32 comp_id_0;/* 0x1FF0 */ +u32 comp_id_1; +u32 comp_id_2; +u32 comp_id_3; +u32 _pad_0x2000_0x2008[2 ]; +/* L4 MAIN */ +u32 l4main_fn_mod_bm_iss; +u32 _pad_0x200c_0x3008[1023 ]; +/* L4 SP */ +u32 l4sp_fn_mod_bm_iss; +u32 _pad_0x300c_0x4008[1023 ]; +/* L4 MP */ +u32 l4mp_fn_mod_bm_iss; +u32 _pad_0x400c_0x5008[1023 ]; +/* L4 OSC1 */ +u32 l4osc_fn_mod_bm_iss; +u32 _pad_0x500c_0x6008[1023 ]; +/* L4 SPIM */ +u32 l4spim_fn_mod_bm_iss; +u32 _pad_0x600c_0x7008[1023 ]; +/* STM */ +u32 stm_fn_mod_bm_iss; +u32 _pad_0x700c_0x7108[63 ]; +u32 stm_fn_mod; +u32 _pad_0x710c_0x8008[959 ]; +/* LWHPS2FPGA */ +u32 lwhps2fpga_fn_mod_bm_iss; +u32 _pad_0x800c_0x8108[63 ]; +u32 lwhps2fpga_fn_mod; +u32 _pad_0x810c_0xa008[1983 ]; +/* USB1 */ +u32 usb1_fn_mod_bm_iss; +u32 _pad_0xa00c_0xa044[14 ]; +u32 usb1_ahb_cntl; +u32 _pad_0xa048_0xb008[1008 ]; +/* NANDDATA */ +u32 nanddata_fn_mod_bm_iss; +u32 _pad_0xb00c_0xb108[63 ]; +u32 nanddata_fn_mod; +u32 _pad_0xb10c_0x20008[21439 ]; +/* USB0 */ +u32 usb0_fn_mod_bm_iss; +u32 _pad_0x2000c_0x20044[14 ]; +u32 usb0_ahb_cntl; +u32 _pad_0x20048_0x21008[1008 ]; +/* NANDREGS */ +u32 nandregs_fn_mod_bm_iss; +u32 _pad_0x2100c_0x21108[63 ]; +u32 nandregs_fn_mod; +u32 _pad_0x2110c_0x22008[959 ]; +/* QSPIDATA */ +u32 qspidata_fn_mod_bm_iss; +u32 _pad_0x2200c_0x22044[14 ]; +u32 qspidata_ahb_cntl; +u32 _pad_0x22048_0x23008[1008 ]; +/* FPGAMGRDATA */ +u32 fpgamgrdata_fn_mod_bm_iss; +u32 _pad_0x2300c_0x23040[13 ]; +u32 fpgamgrdata_wr_tidemark;/* 0x23040 */ +u32 _pad_0x23044_0x23108[49 ]; +u32 fn_mod; +u32 _pad_0x2310c_0x24008[959 ]; +/* HPS2FPGA */ +u32 hps2fpga_fn_mod_bm_iss; +u32 _pad_0x2400c_0x24040[13 ]; +u32 hps2fpga_wr_tidemark;/* 0x24040 */ +u32 _pad_0x24044_0x24108[49 ]; +u32 hps2fpga_fn_mod; +u32 _pad_0x2410c_0x25008[959 ]; +/* ACP */ +u32 acp_fn_mod_bm_iss; +u32 _pad_0x2500c_0x25108[63 ]; +u32 acp_fn_mod; +u32 _pad_0x2510c_0x26008[959 ]; +/* Boot ROM */ +u32 bootrom_fn_mod_bm_iss; +u32 _pad_0x2600c_0x26108[63 ]; +u32 bootrom_fn_mod; +u32 _pad_0x2610c_0x27008[959 ]; +/* On-chip RAM */ +u32 ocram_fn_mod_bm_iss; +u32 _pad_0x2700c_0x27040[13 ]; +u32 ocram_wr_tidemark;/* 0x27040 */ +u32 _pad_0x27044_0x27108[49 ]; +u32 ocram_fn_mod; +u32 _pad_0x2710c_0x42024[27590 ]; +/* DAP */ +u32 dap_fn_mod2; +u32 dap_fn_mod_ahb; +u32 _pad_0x4202c_0x42100[53 ]; +u32 dap_read_qos;/* 0x42100 */ +u32 dap_write_qos; +u32 dap_fn_mod; +u32 _pad_0x4210c_0x43100[1021 ]; +/* MPU */ +u32 mpu_read_qos;/* 0x43100 */ +u32 mpu_write_qos; +u32 mpu_fn_mod; +u32 _pad_0x4310c_0x44028[967 ]; +/* SDMMC */ +u32 sdmmc_fn_mod_ahb; +u32 _pad_0x4402c_0x44100[53 ]; +u32 sdmmc_read_qos;/* 0x44100 */ +u32 sdmmc_write_qos; +u32 sdmmc_fn_mod; +u32 _pad_0x4410c_0x45100[1021 ]; +/* DMA */ +u32 dma_read_qos;/* 0x45100 */ +u32 dma_write_qos; +u32 dma_fn_mod; +u32 _pad_0x4510c_0x46040[973 ]; +/* FPGA2HPS */ +u32 fpga2hps_wr_tidemark;/* 0x46040 */ +u32 _pad_0x46044_0x46100[47 ]; +u32 fpga2hps_read_qos;/* 0x46100 */ +u32 fpga2hps_write_qos; +u32 fpga2hps_fn_mod; +u32 _pad_0x4610c_0x47100[1021 ]; +/* ETR */ +u32 etr_read_qos;/* 0x47100 */ +u32 etr_write_qos; +u32 etr_fn_mod; +u32 _pad_0x4710c_0x48100[1021 ]; +/* EMAC0 */ +u32 emac0_read_qos;/* 0x48100 */ +u32 emac0_write_qos; +u32 emac0_fn_mod; +u32 _pad_0x4810c_0x49100[1021 ]; +/* EMAC1 */ +u32 emac1_read_qos;/* 0x49100 */ +u32 emac1_write_qos; +u32 emac1_fn_mod; +u32 _pad_0x4910c_0x4a028[967 ]; +/* USB0 */ +u32 usb0_fn_mod_ahb; +u32 _pad_0x4a02c_0x4a100[53 ]; +u32 usb0_read_qos;/* 0x4A100 */ +u32 usb0_write_qos; +u32 usb0_fn_mod; +u32 _pad_0x4a10c_0x4b100[1021 ]; +/* NAND */ +u32 nand_read_qos;/* 0x4B100 */ +u32 nand_write_qos; +u32 nand_fn_mod; +u32 _pad_0x4b10c_0x4c028[967 ]; +/* USB1 */ +u32 usb1_fn_mod_ahb; +u32 _pad_0x4c02c_0x4c100[53 ]; +u32 usb1_read_qos;/* 0x4C100 */ +u32 usb1_write_qos; +u32 usb1_fn_mod; +}; + +#endif /* _NIC301_REGISTERS_H_ */
Signature · 1 line
2.0.0
PATCH 43/51 arm: socfpga: pl310: Map SDRAM to 0x0
In reply to Marek VasutConfigure the PL310 address filter to make sure DRAM is mapped to 0x0. This code also configures the "remap" register of NIC-301 and sets the required 'mpuzero' bit.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/misc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/cpu/armv7/socfpga/misc.c +14 -0
@@ -12,11 +12,17 @@#include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> #include <asm/arch/dwmmc.h> +#include <asm/arch/nic301.h> +#include <asm/pl310.h> DECLARE_GLOBAL_DATA_PTR ; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE ;static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +static struct nic301_registers *nic301_regs = + (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS ;int dram_init (void ) {
@@ -129,6 +135,14 @@ static inline void socfpga_fpga_add(void) {}int misc_init_r (void ) { +/* Configure the L2 controller to make SDRAM start at 0 */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +writel (0x2 , &nic301_regs->remap); +#else +writel (0x1 , &nic301_regs->remap);/* remap.mpuzero */ +writel (0x1 , &pl310->pl310_addr_filter_start); +#endif +/* Add device descriptor to FPGA device table */ socfpga_fpga_add ();
Signature · 1 line
2.0.0
PATCH 44/51 arm: socfpga: nic301: Add NIC-301 configuration code
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA . The code sets the access permissions for the CPU to the AMBA slaves such that the CPU can access them in both secure and non-secure mode.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- arch/arm/cpu/armv7/socfpga/misc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
arch/arm/cpu/armv7/socfpga/misc.c +26 -0
@@ -13,6 +13,7 @@#include <asm/arch/system_manager.h> #include <asm/arch/dwmmc.h> #include <asm/arch/nic301.h> +#include <asm/arch/scu.h> #include <asm/pl310.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -23,6 +24,8 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ;static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS ; +static struct scu_registers *scu_regs = + (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS ;int dram_init (void ) {
@@ -133,8 +136,31 @@ static void socfpga_fpga_add(void)static inline void socfpga_fpga_add (void ) {}#endif +/* +* Convert all NIC-301 AMBA slaves from secure to non-secure +*/ +static void socfpga_nic301_slave_ns (void ) +{ +writel (0x1 , &nic301_regs->lwhps2fpgaregs); +writel (0x1 , &nic301_regs->hps2fpgaregs); +writel (0x1 , &nic301_regs->acp); +writel (0x1 , &nic301_regs->rom); +writel (0x1 , &nic301_regs->ocram); +writel (0x1 , &nic301_regs->sdrdata); +} +int misc_init_r (void ) { +socfpga_bridges_reset (1 ); +socfpga_nic301_slave_ns (); + +/* +* Private components security: +* U-Boot : configure private timer, global timer and cpu component +* access as non secure for kernel stage (as required by Linux) +*/ +setbits_le32 (&scu_regs->sacr,0xfff ); +/* Configure the L2 controller to make SDRAM start at 0 */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET writel (0x2 , &nic301_regs->remap);
Signature · 1 line
2.0.0
PATCH 45/51 arm: socfpga: Enable DWMMC for SOCFPGA
In reply to Marek VasutFrom: Chin Liang See <[email protected]>
Enable the DesignWare MMC controller driver support for SOCFPGA Cyclone5 dev kit
Signed-off-by Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Tom Rini <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Wolfgang Denk <[email protected]>
--- include/configs/socfpga_cyclone5.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
include/configs/socfpga_cyclone5.h +16 -0
@@ -251,6 +251,22 @@/* Clocks source frequency to watchdog timer */ #define CONFIG_DW_WDT_CLOCK_KHZ 25000 +/* +* MMC support +*/ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_SOCFPGA_DWMMC +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +/* using smaller max blk cnt to avoid flooding the limited stack we have */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif /* CONFIG_MMC */ /* * SPL "Second Program Loader" aka Initial Software
Signature · 1 line
2.0.0
PATCH 46/51 arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot
In reply to Marek VasutFrom: Chin Liang See <[email protected]>
Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit. Enable the bootz command as zImage is used instead uImage.
Signed-off-by Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Tom Rini <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Wolfgang Denk <[email protected]>
--- include/configs/socfpga_cyclone5.h | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-)
include/configs/socfpga_cyclone5.h +18 -4
@@ -93,6 +93,8 @@#include <config_cmd_default.h> /* FAT file system support */ #define CONFIG_CMD_FAT +/* bootz command support */ +#define CONFIG_CMD_BOOTZ /*
@@ -117,24 +119,36 @@#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "#define CONFIG_CMD_RUN +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif /* * arguments passed to the bootm command. The value of * CONFIG_BOOTARGS goes into the environment value "bootargs". * Do note the value will overide also the chosen node in FDT blob. */ -#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M at 0x0" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)#define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=uImage\0" \ + "bootimage=zImage\0" \ "fdt_addr=100\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "fatload mmc 0:1 ${loadaddr} ${bootimage};" \ + "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ "qspiroot=/dev/mtdblock0\0" \ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
Signature · 1 line
2.0.0
PATCH 47/51 arm: socfpga: Move cache_enable to CPU code
In reply to Marek VasutMove icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work.
Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Tom Rini <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Wolfgang Denk <[email protected]>
--- arch/arm/cpu/armv7/socfpga/misc.c | 10 ++++++++++ board/altera/socfpga/socfpga_cyclone5.c | 3 --- 2 files changed, 10 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/socfpga/misc.c +10 -0
@@ -33,6 +33,16 @@ int dram_init(void)return 0 ; } +void enable_caches (void ) +{ +#ifndef CONFIG_SYS_ICACHE_OFF +icache_enable (); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF +dcache_enable (); +#endif +} +/* * DesignWare Ethernet initialization */
board/altera/socfpga/socfpga_cyclone5.c +0 -3
@@ -34,9 +34,6 @@ int board_early_init_f(void)*/ int board_init (void ) { -icache_enable (); -dcache_enable (); -/* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params =CONFIG_SYS_SDRAM_BASE +0x100 ;
Signature · 1 line
2.0.0
PATCH 48/51 arm: socfpga: Add command to control HPS-FPGA bridges
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Add command to enable and disable the bridges between HPS and FPGA.
This patch does have a checkpatch issue with the assembler portion, checkpatch correctly complains that there should be no whitespace before quoted newline. I do not agree that fixing this specific checkpatch issue will improve the readability, thus this one is not addressed.
Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Tom Rini <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Wolfgang Denk <[email protected]>
--- arch/arm/cpu/armv7/socfpga/misc.c | 75 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+)
arch/arm/cpu/armv7/socfpga/misc.c +75 -0
@@ -22,6 +22,8 @@ static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE ;static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS ; +static struct socfpga_reset_manager *reset_manager_base = + (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS ;static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS ; static struct scu_registers *scu_regs =
@@ -159,8 +161,14 @@ static void socfpga_nic301_slave_ns(void)writel (0x1 , &nic301_regs->sdrdata); } +static uint32_t iswgrp_handoff[8 ]; +int misc_init_r (void ) { +int i; +for (i =0 ; i <8 ; i++)/* Cache initial SW setting regs */ + iswgrp_handoff[i] =readl (&sysmgr_regs->iswgrp_handoff[i]); +socfpga_bridges_reset (1 );socfpga_nic301_slave_ns ();
@@ -193,3 +201,70 @@ int misc_init_r(void)return 0 ; } + +static void socfpga_sdram_apply_static_cfg (void ) +{ +const uint32_t staticcfg =SOCFPGA_SDR_ADDRESS +0x505c ; +const uint32_t applymask =0x8 ; +uint32_t val =readl (staticcfg) | applymask; + +/* +* SDRAM staticcfg register specific: +* When applying the register setting, the CPU must not access +* SDRAM. Luckily for us, we can abuse i-cache here to help us +* circumvent the SDRAM access issue. The idea is to make sure +* that the code is in one full i-cache line by branching past +* it and back. Once it is in the i-cache, we execute the core +* of the code and apply the register settings. +* +* The code below uses 7 instructions, while the Cortex-A9 has +* 32-byte cachelines, thus the limit is 8 instructions total. +*/ + asmvolatile ( +".align 5 \n" +" b 2f \n" +"1: str %0, [%1] \n" +" dsb \n" +" isb \n" +" b 3f \n" +"2: b 1b \n" +"3: nop \n" + : :"r" (val),"r" (staticcfg) :"memory" ,"cc" ); +} + +int do_bridge (cmd_tbl_t *cmdtp,int flag,int argc,char *const argv[]) +{ +if (argc !=2 ) +return CMD_RET_USAGE ; + + argv++; + +switch (*argv[0 ]) { +case 'e' :/* Enable */ +writel (iswgrp_handoff[2 ], &sysmgr_regs->fpgaintfgrp_module); +socfpga_sdram_apply_static_cfg (); +writel (iswgrp_handoff[3 ],SOCFPGA_SDR_ADDRESS +0x5080 ); +writel (iswgrp_handoff[0 ], &reset_manager_base->brg_mod_reset); +writel (iswgrp_handoff[1 ], &nic301_regs->remap); +break ; +case 'd' :/* Disable */ +writel (0 , &sysmgr_regs->fpgaintfgrp_module); +writel (0 ,SOCFPGA_SDR_ADDRESS +0x5080 ); +socfpga_sdram_apply_static_cfg (); +writel (0 , &reset_manager_base->brg_mod_reset); +writel (1 , &nic301_regs->remap); +break ; +default : +return CMD_RET_USAGE ; + } + +return 0 ; +} + +U_BOOT_CMD ( + bridge,2 ,1 , do_bridge, +"SoCFPGA HPS FPGA bridge control" , +"enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" +"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" +"" +);
Signature · 1 line
2.0.0
PATCH 49/51 arm: socfpga: Clean up SoCFPGA configuration
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Reorganize and cleanup the configuration file for SoCFPGA. There is no functional change after this cleanup. This was necessary, since the file was a wild mess and it was impossible to make sense of it's content, let alone change something without breaking some other thing. This patch puts the contents on par with regular U-Boot standards.
Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER and CONFIG_USE_IRQ, which is undefined by default. Finally, do logical reordering of the defines in the file so it's much more readable. The reordering was also necessary for the splitting as the initial one was messy.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- include/configs/socfpga_cyclone5.h | 406 +++++++++++++++++-------------------- 1 file changed, 188 insertions(+), 218 deletions(-)
include/configs/socfpga_cyclone5.h +188 -218
@@ -1,319 +1,289 @@/* -* Copyright (C) 2012 Altera Corporation <www.altera.com> +* Copyright (C) 2012 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__#include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" #include "../../board/altera/socfpga/iocsr_config.h" #include "../../board/altera/socfpga/pll_config.h" -/* -* High level configuration -*/ +#define CONFIG_SYS_GENERIC_BOARD +/* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET#define CONFIG_ARMV7 -#undef CONFIG_USE_IRQ +#define CONFIG_SYS_THUMB_BUILD -#define CONFIG_MISC_INIT_R -#define CONFIG_SINGLE_BOOTLOADER #define CONFIG_SOCFPGA -#define CONFIG_CLOCKS -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG -/* base address for .text section */ -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TEXT_BASE 0x08000040 -#else -#define CONFIG_SYS_TEXT_BASE 0x01000040 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_USB -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_REGEX /* Enable regular expression support */ /* -* Display CPU and Board Info +* High level configuration */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO - -/* -* Enable early stage initialization at C environment -*/ #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CLOCKS -/* flat device tree */ +#define CONFIG_FIT #define CONFIG_OF_LIBFDT -/* skip updating the FDT blob */ -#define CONFIG_FDT_BLOB_SKIP_UPDATE -/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ -#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) +#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* -* Memory allocation (MALLOC) +* Memory configurations */ -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE 1024 -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define PHYS_SDRAM_1_SIZE 0x40000000/* 1GiB on SoCDK */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x0 +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE -/* SP location before relocation, must use scratch RAM */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -/* Reserving 0x100 space at back of scratch RAM for debug info */ #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) -/* Stack pointer prior relocation, must situated at on-chip RAM */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - - -/* -* Command line configuration. -*/ -#define CONFIG_SYS_NO_FLASH -#include <config_cmd_default.h> -/* FAT file system support */ -#define CONFIG_CMD_FAT -/* bootz command support */ -#define CONFIG_CMD_BOOTZ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) - -/* -* Misc -*/ -#define CONFIG_DOS_PARTITION 1 - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040#endif -/* -* Environment setup -*/ - -/* Delay before automatically booting the default image */ -#define CONFIG_BOOTDELAY 3 -/* Enable auto completion of commands using TAB */ -#define CONFIG_AUTO_COMPLETE -/* use "hush" command parser */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_CMD_RUN - +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTCOMMAND "run ramboot"#else -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"#endif +#define CONFIG_LOADADDR 0x8000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR/* -* arguments passed to the bootm command. The value of -* CONFIG_BOOTARGS goes into the environment value "bootargs". -* Do note the value will overide also the chosen node in FDT blob. +* U-Boot general configurations */ -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "fatload mmc 0:1 ${loadaddr} ${bootimage};" \ - "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - -/* using environment setting for stdin, stdout, stderr */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* Enable the call to overwrite_console() */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -/* Enable overwrite of previous console environment settings */ -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024/* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32/* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER /* -* Hardware drivers +* Cache */ +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS/* -* SDRAM Memory Map +* Ethernet on SoC (EMAC) */ -/* We have 1 bank of DRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -/* SDRAM Bank #1 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* SDRAM memory size */ -#define PHYS_SDRAM_1_SIZE 0x40000000 +#if defined(CONFIG_CMD_NET ) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET ) +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_NET_MULTI +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_MII +#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) +#define CONFIG_PHYLIB +#define CONFIG_PHY_GIGE -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE +#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII +#define CONFIG_EPHY0_PHY_ADDR 0 + +/* PHY */ +#define CONFIG_EPHY1_PHY_ADDR 4 +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 -/* -* NS16550 Configuration -*/ -#define UART0_BASE SOCFPGA_UART0_ADDRESS -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define V_NS16550_CLK 1000000 -#else -#define V_NS16550_CLK 100000000#endif -#define CONFIG_BAUDRATE 115200/* -* FLASH +* FPGA Driver */ -#define CONFIG_SYS_NO_FLASH +#ifdef CONFIG_CMD_FPGA +#define CONFIG_FPGA +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_SOCFPGA +#define CONFIG_FPGA_COUNT 1 +#endif /* * L4 OSC1 Timer 0 */ -/* This timer use eosc1 where the clock frequency is fixed -* throughout any condition */ +/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* Timer info */ +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TIMER_RATE 2400000#else #define CONFIG_SYS_TIMER_RATE 25000000#endif -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) - -#define CONFIG_ENV_IS_NOWHERE - -/* -* network support -*/ -#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_DESIGNWARE_ETH 1 -#endif - -#ifdef CONFIG_DESIGNWARE_ETH -#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS -#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS -/* console support for network */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -/* designware */ -#define CONFIG_NET_MULTI -#define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_MII -#define CONFIG_PHY_GIGE -#define CONFIG_DW_AUTONEG -#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_MICREL_KSZ9021 -/* EMAC controller and PHY used */ -#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE -#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR -#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII -#endif /* CONFIG_DESIGNWARE_ETH */ /* * L4 Watchdog */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 +#ifdef CONFIG_HW_WATCHDOG #define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS -/* Clocks source frequency to watchdog timer */ #define CONFIG_DW_WDT_CLOCK_KHZ 25000 +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 +#endif /* -* MMC support +* MMC Driver */ +#ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#ifdef CONFIG_MMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC #define CONFIG_DWMMC #define CONFIG_SOCFPGA_DWMMC #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +/* FIXME */ /* using smaller max blk cnt to avoid flooding the limited stack we have */ -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 -#endif /* CONFIG_MMC */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256/* FIXME -- SPL only? */ +#endif /* -* SPL "Second Program Loader" aka Initial Software +* Serial Driver */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_NS16550_CLK 1000000 +#else +#define CONFIG_SYS_NS16550_CLK 100000000 +#endif +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 -/* Enable building of SPL globally */ -#define CONFIG_SPL_FRAMEWORK - -/* TEXT_BASE for linking the SPL binary */ -#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 +/* +* USB +* Ungate USB: +* mw 0xffd05014 0x01bef032 +*/ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_OTG +/*#define CONFIG_USB_DWC2_REG_ADDR 0xffb00000*/ +#define CONFIG_USB_DWC2_REG_ADDR 0xffb40000 +#define CONFIG_USB_STORAGE +#endif -/* Stack size for SPL */ -#define CONFIG_SPL_STACK_SIZE (4 * 1024) +/* +* U-Boot environment +*/ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_HOSTNAME socfpga_cyclone5 -/* MALLOC size for SPL */ -#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "fatload mmc 0:1 ${loadaddr} ${bootimage};" \ + "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" -#define CONFIG_SPL_SERIAL_SUPPORT +/* +* SPL +*/ +#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_STACK_SIZE (4 * 1024) +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024)/* FIXME */ +#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) -#define CHUNKSZ_CRC32 (1 * 1024) - +#define CHUNKSZ_CRC32 (1 * 1024)/* FIXME: ewww */ #define CONFIG_CRC32_VERIFY /* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" -/* Support for common/libcommon.o in SPL binary */ #define CONFIG_SPL_LIBCOMMON_SUPPORT -/* Support for lib/libgeneric.o in SPL binary */ #define CONFIG_SPL_LIBGENERIC_SUPPORT - -/* Support for watchdog */ #define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif -#endif /* __CONFIG_H */ +#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
Signature · 1 line
2.0.0
PATCH 50/51 arm: socfpga: Split SoCFPGA configuration
In reply to Marek VasutFrom: Pavel Machek <[email protected]>
Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come.
This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- include/configs/socfpga_cyclone5.h | 211 ++---------------------------- include/configs/socfpga_cyclone5_common.h | 196 +++++++++++++++++++++++++++ 2 files changed, 207 insertions(+), 200 deletions(-) create mode 100644 include/configs/socfpga_cyclone5_common.h
include/configs/socfpga_cyclone5.h +11 -200
@@ -1,26 +1,16 @@/* -* Copyright (C) 2012 Altera Corporation <www.altera.com> +* Copyright (C) 2014 Marek Vasut <[email protected]> * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ -#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_H__#include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" #include "../../board/altera/socfpga/iocsr_config.h" #include "../../board/altera/socfpga/pll_config.h" -#define CONFIG_SYS_GENERIC_BOARD - -/* Virtual target or real hardware */ -#undef CONFIG_SOCFPGA_VIRTUAL_TARGET - -#define CONFIG_ARMV7 -#define CONFIG_SYS_THUMB_BUILD - -#define CONFIG_SOCFPGA -/* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH #include <config_cmd_default.h>
@@ -46,44 +36,8 @@#define CONFIG_REGEX /* Enable regular expression support */ -/* -* High level configuration -*/ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_NO_FLASH -#define CONFIG_CLOCKS - -#define CONFIG_FIT -#define CONFIG_OF_LIBFDT -#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* -* Memory configurations -*/ +/* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000/* 1GiB on SoCDK */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x0 -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TEXT_BASE 0x08000040 -#else -#define CONFIG_SYS_TEXT_BASE 0x01000040 -#endif /* Booting Linux */ #define CONFIG_BOOTDELAY 3
@@ -97,42 +51,8 @@#define CONFIG_LOADADDR 0x8000#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* -* U-Boot general configurations -*/ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 1024/* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -/* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32/* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER - -/* -* Cache -*/ -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS - -/* -* Ethernet on SoC (EMAC) -*/ -#if defined(CONFIG_CMD_NET ) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET ) -#define CONFIG_DESIGNWARE_ETH -#define CONFIG_NET_MULTI -#define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_MII -#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB -#define CONFIG_PHY_GIGE - +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET )#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII#define CONFIG_EPHY0_PHY_ADDR 0
@@ -148,92 +68,8 @@#endif -/* -* FPGA Driver -*/ -#ifdef CONFIG_CMD_FPGA -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_SOCFPGA -#define CONFIG_FPGA_COUNT 1 -#endif - -/* -* L4 OSC1 Timer 0 -*/ -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TIMER_RATE 2400000 -#else -#define CONFIG_SYS_TIMER_RATE 25000000 -#endif - -/* -* L4 Watchdog -*/ -#ifdef CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS -#define CONFIG_DW_WDT_CLOCK_KHZ 25000 -#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 -#endif - -/* -* MMC Driver -*/ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_GENERIC_MMC -#define CONFIG_DWMMC -#define CONFIG_SOCFPGA_DWMMC -#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 -/* FIXME */ -/* using smaller max blk cnt to avoid flooding the limited stack we have */ -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256/* FIXME -- SPL only? */ -#endif - -/* -* Serial Driver -*/ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_NS16550_CLK 1000000 -#else -#define CONFIG_SYS_NS16550_CLK 100000000 -#endif -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* -* USB -* Ungate USB: -* mw 0xffd05014 0x01bef032 -*/ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_OTG -/*#define CONFIG_USB_DWC2_REG_ADDR 0xffb00000*/ -#define CONFIG_USB_DWC2_REG_ADDR 0xffb40000 -#define CONFIG_USB_STORAGE -#endif - -/* -* U-Boot environment -*/ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_HOSTNAME socfpga_cyclone5 +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_cyclone5#define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \
@@ -258,32 +94,7 @@" root=${qspiroot} rw rootfstype=${qspirootfstype};" \"bootm ${loadaddr} - ${fdt_addr}\0" -/* -* SPL - */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_STACK_SIZE (4 * 1024) -#define CONFIG_SPL_MALLOC_SIZE (5 * 1024)/* FIXME */ -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) - -#define CHUNKSZ_CRC32 (1 * 1024)/* FIXME: ewww */ -#define CONFIG_CRC32_VERIFY - -/* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_WATCHDOG_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS -#endif +/* The rest of the configuration is shared */ +#include <configs/socfpga_cyclone5_common.h> -#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ +#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */
include/configs/socfpga_cyclone5_common.h new file +196 -0
196 lines not on this page · raw message
Signature · 1 line
2.0.0
PATCH 50/51 arm: socfpga: Split SoCFPGA configuration
Quoted 18 lines · Marek Vasut
From: Pavel Machek <[email protected]>
Split the SoCFPGA configuration into SoC-specific part which is common for all boards (
socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come.This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>
Quoted 5 lines
--- include/configs/socfpga_cyclone5.h | 211 ++---------------------------- include/configs/socfpga_cyclone5_common.h | 196 +++++++++++++++++++++++++++ 2 files changed, 207 insertions(+), 200 deletions(-) create mode 100644 include/configs/socfpga_cyclone5_common.h
Thanks for taking a stab at this, but I think it makes more sense to have socfpga_commoh.h and socfpga_cyclone5.h. The _common file can have most of the common settings for u-boot, while _cyclone5 will have the base addresses for all the various IP blocks. Then once everything is done for Cyclone5, we can add support for the Arria5 SOC by just adding socfpga_arria5.h.
BR,
Dinh
PATCH 50/51 arm: socfpga: Split SoCFPGA configuration
Hi!
Quoted 24 lines
Quoted 18 lines
From: Pavel Machek <[email protected]>
Split the SoCFPGA configuration into SoC-specific part which is common for all boards (
socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come.This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Quoted 5 lines
--- include/configs/socfpga_cyclone5.h | 211 ++---------------------------- include/configs/socfpga_cyclone5_common.h | 196 +++++++++++++++++++++++++++ 2 files changed, 207 insertions(+), 200 deletions(-) create mode 100644 include/configs/socfpga_cyclone5_common.h
Quoted 5 lines
Thanks for taking a stab at this, but I think it makes more sense to have
socfpga_commoh.handsocfpga_cyclone5.h. The_commonfile can have most of the common settings for u-boot, while_cyclone5will have the base addresses for all the various IP blocks. Then once everything is done for Cyclone5, we can add support for the Arria5 SOC by just addingsocfpga_arria5.h.
socfpga_common.h sounds like a good name.
But I wonder if socfpga_cyclone5.h should be named socfpga_cyclone5_socdk.h ?
Best regards,
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH 50/51 arm: socfpga: Split SoCFPGA configuration
Quoted 36 lines · Pavel Machek
Hi!
Quoted 27 lines
Quoted 18 lines
From: Pavel Machek <[email protected]>
Split the SoCFPGA configuration into SoC-specific part which is common for all boards (
socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come.This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Quoted 8 lines
---
include/configs/socfpga_cyclone5.h | 211 ++---------------------------- include/configs/socfpga_cyclone5_common.h | 196 +++++++++++++++++++++++++++ 2 files changed, 207 insertions(+), 200 deletions(-) create mode 100644 include/configs/socfpga_cyclone5_common.hQuoted 6 lines
Thanks for taking a stab at this, but I think it makes more sense to have
socfpga_commoh.handsocfpga_cyclone5.h. The_commonfile can have most of the common settings for u-boot, while_cyclone5will have the base addresses for all the various IP blocks. Then once everything is done for Cyclone5, we can add support for the Arria5 SOC by just addingsocfpga_arria5.h.
Quoted 4 lines
socfpga_common.hsounds like a good name.But I wonder if
socfpga_cyclone5.hshould be namedsocfpga_cyclone5_socdk.h?
To be consistent with Linux DTB name even ? Might be a good idea, but not for this patch . This patch doesn't introduce any "functional" change either for the build or for the result.
Best regards,
Marek Vasut
PATCH 50/51 arm: socfpga: Split SoCFPGA configuration
In reply to Dinh NguyenQuoted 28 lines · Dinh Nguyen
Quoted 18 lines · Marek Vasut
From: Pavel Machek <[email protected]>
Split the SoCFPGA configuration into SoC-specific part which is common for all boards (
socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come.This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>Quoted 8 lines
---
include/configs/socfpga_cyclone5.h | 211 ++---------------------------- include/configs/socfpga_cyclone5_common.h | 196 +++++++++++++++++++++++++++ 2 files changed, 207 insertions(+), 200 deletions(-) create mode 100644 include/configs/socfpga_cyclone5_common.h
Quoted 6 lines
Thanks for taking a stab at this, but I think it makes more sense to have
socfpga_commoh.handsocfpga_cyclone5.h. The_commonfile can have most of the common settings for u-boot, while_cyclone5will have the base addresses for all the various IP blocks. Then once everything is done for Cyclone5, we can add support for the Arria5 SOC by just addingsocfpga_arria5.h.
Yes, I agree, done.
Best regards,
Marek Vasut
PATCH 51/51 arm: socfpga: Use CMD_FS_GENERIC
In reply to Marek VasutEnable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the filesystem type into the environment.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Pavel Machek <[email protected]>
--- include/configs/socfpga_cyclone5.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
include/configs/socfpga_cyclone5.h +3 -2
@@ -26,6 +26,7 @@#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GREPENV #define CONFIG_CMD_MII #define CONFIG_CMD_MMC
@@ -86,8 +87,8 @@" root=${mmcroot} rw rootwait;" \"bootz ${loadaddr} - ${fdt_addr}\0" \"mmcload=mmc rescan;" \ -"fatload mmc 0:1 ${loadaddr} ${bootimage};" \ -"fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ +"load mmc 0:1 ${loadaddr} ${bootimage};" \ +"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \"qspiroot=/dev/mtdblock0\0" \"qspirootfstype=jffs2\0" \"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
Signature · 1 line
2.0.0
PATCH 51/51 arm: socfpga: Use CMD_FS_GENERIC
Quoted 28 lines · Marek Vasut
Enable and use the
CONFIG_CMD_FS_GENERICto avoid hard-coding the filesystem type into the environment.Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Pavel Machek <[email protected]>--- include/configs/socfpga_cyclone5.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)include/configs/socfpga_cyclone5.h +1
-0@@ -26,6 +26,7 @@#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GREPENV #define CONFIG_CMD_MII #define CONFIG_CMD_MMC
include/configs/socfpga_cyclone5.h line 94
Quoted 10 lines
include/configs/socfpga_cyclone5.h +2
-2@@ -86,8 +87,8 @@" root=${mmcroot} rw rootwait;" \"bootz ${loadaddr} - ${fdt_addr}\0" \"mmcload=mmc rescan;" \ -"fatload mmc 0:1 ${loadaddr} ${bootimage};" \ -"fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ +"load mmc 0:1 ${loadaddr} ${bootimage};" \ +"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \"qspiroot=/dev/mtdblock0\0" \"qspirootfstype=jffs2\0" \"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
Acked-by Michal Simek <[email protected]>
Thanks,
Michal
PATCH 28/51 fpga: altera: Clean up altera_validate function
In reply to Marek VasutQuoted 9 lines · Marek Vasut
Boldly go, where no programmer has gone before and just clean up the indentation mayhem. No functional change.
Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>
Nice!
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
cover arm: socfpga: Usability fixes
In reply to Marek VasutQuoted 5 lines · Marek Vasut
This entire series is the second stab at making SoCFPGA usable with mainline U-Boot again. There are much fewer bits missing than in the last series, more cleanup happened and bugs were fixed. This allows me to use mainline U-Boot on my SoCFPGA systems.
Quoted 7 lines
The big missing part is the SPL generation, which still needs a lot of additional work. We also miss the Cadence QSPI controller driver.
This set contains patches for a few subsystems, which are utilized by the SoCFPGA, but the most part is the SoCFPGA chip support. This series now contains cleanup for the mayhem in
drivers/fpga/altera.ccode, which was terrible, but is now much better.
Thanks Marek!
I have tested your latest patchset on the EBV SoCrates board. And it works really good. Once this is all available in mainline I'll send a patch to add the SoCrates and a new custom SoCFPGA board support to the list.
For now, please add my tested-by to the patchset:
Tested-by Stefan Roese <[email protected]>
Thanks,
Stefan
cover arm: socfpga: Usability fixes
In reply to Marek VasutHi!
Quoted 4 lines
This entire series is the second stab at making SoCFPGA usable with mainline U-Boot again. There are much fewer bits missing than in the last series, more cleanup happened and bugs were fixed. This allows me to use mainline U-Boot on my SoCFPGA systems.
You can add my
Acked-by Pavel Machek <[email protected]>
to patches 3,6,7,11,12,13,16,17,18,27,29,30,31,32,33,36,43,47,51.
You need to add your signoff to patches 45,46,50. Then you have my ack.
For patches 48,49, I'm marked as an author, but I think that you should take the credit. You have my ack.
Thanks for the hard work, and looking forward to u-boot-socfpga repository,
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
cover arm: socfpga: Usability fixes
Quoted 7 lines · Pavel Machek
Hi!
Quoted 4 lines
This entire series is the second stab at making SoCFPGA usable with mainline U-Boot again. There are much fewer bits missing than in the last series, more cleanup happened and bugs were fixed. This allows me to use mainline U-Boot on my SoCFPGA systems.
Quoted 7 lines
You can add my
Acked-by Pavel Machek <[email protected]>to patches 3,6,7,11,12,13,16,17,18,27,29,30,31,32,33,36,43,47,51.
You need to add your signoff to patches 45,46,50. Then you have my ack.
50 has my SoB tho.
Quoted 4 lines
For patches 48,49, I'm marked as an author, but I think that you should take the credit. You have my ack.
Thanks for the hard work, and looking forward to u-boot-socfpga repository,
Thanks.
Best regards,
Marek Vasut
cover arm: socfpga: Usability fixes
In reply to Marek VasutQuoted 5 lines · marex at denx.de
This entire series is the second stab at making SoCFPGA usable with mainline U-Boot again. There are much fewer bits missing than in the last series, more cleanup happened and bugs were fixed. This allows me to use mainline U-Boot on my SoCFPGA systems.
Quoted 8 lines
The big missing part is the SPL generation, which still needs a lot of additional work. We also miss the Cadence QSPI controller driver.
This set contains patches for a few subsystems, which are utilized by the SoCFPGA, but the most part is the SoCFPGA chip support. This series now contains cleanup for the mayhem in
drivers/fpga/altera.ccode, which was terrible, but is now much better.
Thanks Marek, I tested this series of patches and here are the outcome I have.
SDMMC - Working as I can read and write to SDMMC
Boot - Working as I can boot till Linux
Ethernet - Seems not working for me.
FPGA programming - Seems not working for me too.
I will help to look into those features which are not working for me. But this series of patches serves as a good start.
Tested-by Chin Liang See <[email protected]>
Thanks
Chin Liang
cover arm: socfpga: Usability fixes
Quoted 14 lines · Chin Liang See
Quoted 5 lines · marex at denx.de
This entire series is the second stab at making SoCFPGA usable with mainline U-Boot again. There are much fewer bits missing than in the last series, more cleanup happened and bugs were fixed. This allows me to use mainline U-Boot on my SoCFPGA systems.
Quoted 7 lines
The big missing part is the SPL generation, which still needs a lot of additional work. We also miss the Cadence QSPI controller driver.
This set contains patches for a few subsystems, which are utilized by the SoCFPGA, but the most part is the SoCFPGA chip support. This series now contains cleanup for the mayhem in
drivers/fpga/altera.ccode, which was terrible, but is now much better.
Quoted 6 lines
Thanks Marek, I tested this series of patches and here are the outcome I have.
SDMMC - Working as I can read and write to SDMMC
Boot - Working as I can boot till Linux
Ethernet - Seems not working for me.
I suspect that's because the ethernet support in the originally upstreamed SoCFPGA code never worked on the SoCDK in the first place. I think the SoCDK uses EMAC1, but the mainline code uses EMAC0 for whatever reason.
Edit include/configs/socfpga_cyclone5.h and change:
-#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
Does this work ?
Quoted 1 line
FPGA programming - Seems not working for me too.
I zap'd the "run bridge_enable_handoff" thing and replaced it with "bridge enable" command. Could that be the case ?
Quoted 2 lines
I will help to look into those features which are not working for me. But this series of patches serves as a good start.
Please let me know if some of the above help first. The network part should and if it does, then I will add a patch. The FPGA part should as well
Also, I separated the patches into smaller groups, which I will resubmit one more time, but you can find a merge of all of them at [1], so you don't have to apply them by hand. Please be advised, that those branches will be replaced with a never ones, that's why there's the timestamp at the end of the name (so check the repository if there is no new topic/arm/socfpga-yyyymmdd). Also, I will likely garbage collect the old ones at some point.
[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/topic/arm/socfpga-20140930
Best regards,
Marek Vasut