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ARM: imx: Add Freescale LS1021A SoC and board support

PATCH Superseded Jingchang Lu 4 participants 18 messages Oct 13, 2014 – Oct 21, 2014

Subsystems (5)
Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape +1 more subsystems

v5 of 7 Superseded Latest is v7 →

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Jingchang Lu

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#0 lore raw

v5 cover ARM: imx: Add Freescale LS1021A SoC and board support

This series contain the support for Freescale LS1021A CPU and LS1021A-QDS and LS1021A-TWR board.

The LS1021A SoC combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3W embedded communications processors and with a comprehensive enablement model focused on ease of programmability.

The LS1021A SoC shares IPs with i.MX family, Vybrid family and Freescale PowerPC platform.

For the detail information about LS1021A SoC, please refer to the RM doc.

---
changes in v5:
remove unideal dts nodes for later add.
add X11 license to dts files.

changes in v4:
add "syscon" compatible to scfg and dcfg dts node. remove mxc_restart in the platform machine desc. remove dma_zone_size defination.

changes in v3:
rewrite scfg and dcfg binding doc description. remove sai related node leaving to the driver support.

changes in v2:
remove unused nodes.
wakeup the secondary core by IPI call to u-boot standby procedure. add dt-bindings for LS1021A SoC and platform gerenal configuration nodes.

----------------------------------------------------------------
Jingchang Lu (6):
ARM: dts: Add SoC level device tree support for LS1021A
ARM: dts: Add initial LS1021A QDS board dts support
ARM: dts: Add initial LS1021A TWR board dts support
dt-bindings: arm: add Freescale LS1021A SoC device tree binding
ARM: imx: Add initial support for Freescale LS1021A
ARM: imx: Add Freescale LS1021A SMP support

 Documentation/devicetree/bindings/arm/fsl.txt |  38 +++++
 arch/arm/boot/dts/Makefile                    |   2 +
 arch/arm/boot/dts/ls1021a-qds.dts             | 240 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts             | 127 ++++++++++++++++
 arch/arm/boot/dts/ls1021a.dtsi                | 405 ++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                     |  14 ++
 arch/arm/mach-imx/Makefile                    |   4 +-
 arch/arm/mach-imx/common.h                    |   1 +
 arch/arm/mach-imx/mach-ls1021a.c              |  22 +++
 arch/arm/mach-imx/platsmp.c                   |  32 ++++
 10 files changed, 884 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
 create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts
 create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
 create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
author
#1 lore raw

PATCH v5 1/6 ARM: dts: Add SoC level device tree support for LS1021A

From: Jingchang Lu <[email protected]>

Add Freescale LS1021A SoC device tree support

Signed-off-by Nikhil Badola <[email protected]>
Signed-off-by Chenhui Zhao <[email protected]>
Signed-off-by Suresh Gupta <[email protected]>
Signed-off-by Shaveta Leekha <[email protected]>
Signed-off-by Ruchika Gupta <[email protected]>
Signed-off-by Bhupesh Sharma <[email protected]>
Signed-off-by Chao Fu <[email protected]>
Signed-off-by Xiubo Li <[email protected]>
Signed-off-by Jingchang Lu <[email protected]>
---
 arch/arm/boot/dts/ls1021a.dtsi | 405 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 405 insertions(+)
 create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
arch/arm/boot/dts/ls1021a.dtsi new file +405 -0
new file mode 100644
index 0000000..5075c18
@@ -0,0 +1,405 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "fsl,ls1021a";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
+		serial4 = &lpuart4;
+		serial5 = &lpuart5;
+		sysclk = &sysclk;
+		};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at f00 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0xf00>;
+		};
+
+		cpu at f01 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0xf01>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		interrupt-parent = <&gic>;
+		ranges;
+
+		gic: interrupt-controller at 1400000 {
+			compatible = "arm,cortex-a7-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x0 0x1401000 0x0 0x1000>,
+				<0x0 0x1402000 0x0 0x1000>,
+				<0x0 0x1404000 0x0 0x2000>,
+				<0x0 0x1406000 0x0 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+
+		};
+
+		ifc: ifc at 1530000 {
+			compatible = "fsl,ifc", "simple-bus";
+			reg = <0x0 0x1530000 0x0 0x10000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		dcfg: dcfg at 1ee0000 {
+			compatible = "fsl,ls1021a-dcfg", "syscon";
+			reg = <0x0 0x1ee0000 0x0 0x10000>;
+			big-endian;
+		};
+
+		esdhc: esdhc at 1560000 {
+			compatible = "fsl,esdhc";
+			reg = <0x0 0x1560000 0x0 0x10000>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			voltage-ranges = <1800 1800 3300 3300>;
+			sdhci,auto-cmd12;
+			big-endian;
+			bus-width = <4>;
+			status = "disabled";
+		};
+
+		scfg: scfg at 1570000 {
+			compatible = "fsl,ls1021a-scfg", "syscon";
+			reg = <0x0 0x1570000 0x0 0x10000>;
+		};
+
+		clockgen: clocking at 1ee1000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x1ee1000 0x10000>;
+
+			sysclk: sysclk {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-output-names = "sysclk";
+			};
+
+			cga_pll1: pll at 800 {
+				compatible = "fsl,qoriq-core-pll-2.0";
+				#clock-cells = <1>;
+				reg = <0x800 0x10>;
+				clocks = <&sysclk>;
+				clock-output-names = "cga-pll1", "cga-pll1-div2",
+						"cga-pll1-div3", "cga-pll1-div4";
+			};
+
+			platform_clk: pll at c00 {
+				compatible = "fsl,qoriq-core-pll-2.0";
+				#clock-cells = <1>;
+				reg = <0xc00 0x10>;
+				clocks = <&sysclk>;
+				clock-output-names = "platform-clk", "platform-clk-div2";
+			};
+
+			cluster1_clk: clk0c0 at 0 {
+				compatible = "fsl,qoriq-core-mux-2.0";
+				#clock-cells = <0>;
+				reg = <0x0 0x10>;
+				clock-names = "pll1cga", "pll1cga-div2";
+				clocks = <&cga_pll1 0>, <&cga_pll1 2>;
+				clock-output-names = "cluster1-clk";
+			};
+		};
+
+		dspi0: dspi at 2100000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2100000 0x0 0x10000>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&platform_clk 1>;
+			spi-num-chipselects = <5>;
+			big-endian;
+			status = "disabled";
+		};
+
+		dspi1: dspi at 2110000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2110000 0x0 0x10000>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&platform_clk 1>;
+			spi-num-chipselects = <5>;
+			big-endian;
+			status = "disabled";
+		};
+
+		i2c0: i2c at 2180000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2180000 0x0 0x10000>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&platform_clk 1>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 2190000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2190000 0x0 0x10000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&platform_clk 1>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 21a0000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x21a0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&platform_clk 1>;
+			status = "disabled";
+		};
+
+		uart0: serial at 21c0500 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x0 0x21c0500 0x0 0x100>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		uart1: serial at 21c0600 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x0 0x21c0600 0x0 0x100>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		uart2: serial at 21d0500 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x0 0x21d0500 0x0 0x100>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		uart3: serial at 21d0600 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x0 0x21d0600 0x0 0x100>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		lpuart0: serial at 2950000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2950000 0x0 0x1000>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart1: serial at 2960000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2960000 0x0 0x1000>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart2: serial at 2970000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2970000 0x0 0x1000>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart3: serial at 2980000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2980000 0x0 0x1000>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart4: serial at 2990000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2990000 0x0 0x1000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart5: serial at 29a0000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x29a0000 0x0 0x1000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		wdog0: watchdog at 2ad0000 {
+			compatible = "fsl,imx21-wdt";
+			reg = <0x0 0x2ad0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "wdog-en";
+			big-endian;
+		};
+
+		sai1: sai at 2b50000 {
+			compatible = "fsl,vf610-sai";
+			reg = <0x0 0x2b50000 0x0 0x10000>;
+			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "sai";
+			dma-names = "tx", "rx";
+			dmas = <&edma0 1 47>,
+				<&edma0 1 46>;
+			big-endian;
+			status = "disabled";
+		};
+
+		sai2: sai at 2b60000 {
+			compatible = "fsl,vf610-sai";
+			reg = <0x0 0x2b60000 0x0 0x10000>;
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "sai";
+			dma-names = "tx", "rx";
+			dmas = <&edma0 1 45>,
+				<&edma0 1 44>;
+			big-endian;
+			status = "disabled";
+		};
+
+		edma0: edma at 2c00000 {
+			#dma-cells = <2>;
+			compatible = "fsl,vf610-edma";
+			reg = <0x0 0x2c00000 0x0 0x10000>,
+				<0x0 0x2c10000 0x0 0x10000>,
+				<0x0 0x2c20000 0x0 0x10000>;
+			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma-tx", "edma-err";
+			dma-channels = <32>;
+			big-endian;
+			clock-names = "dmamux0", "dmamux1";
+			clocks = <&platform_clk 1>,
+				<&platform_clk 1>;
+		};
+
+		mdio0: mdio at 2d24000 {
+			compatible = "gianfar";
+			device_type = "mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2d24000 0x0 0x4000>;
+		};
+
+		usb at 8600000 {
+			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+			reg = <0x0 0x8600000 0x0 0x1000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			phy_type = "ulpi";
+		};
+
+		usb3 at 3100000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+		};
+	};
+};
Signature · 1 line
1.8.0
#2 lore raw

PATCH v5 1/6 ARM: dts: Add SoC level device tree support for LS1021A

Quoted 60 lines · Jingchang Lu

From: Jingchang Lu <[email protected]>

Add Freescale LS1021A SoC device tree support

Signed-off-by Nikhil Badola <[email protected]>
Signed-off-by Chenhui Zhao <[email protected]>
Signed-off-by Suresh Gupta <[email protected]>
Signed-off-by Shaveta Leekha <[email protected]>
Signed-off-by Ruchika Gupta <[email protected]>
Signed-off-by Bhupesh Sharma <[email protected]>
Signed-off-by Chao Fu <[email protected]>
Signed-off-by Xiubo Li <[email protected]>
Signed-off-by Jingchang Lu <[email protected]>
---
 arch/arm/boot/dts/ls1021a.dtsi | 405 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 405 insertions(+)
 create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
arch/arm/boot/dts/ls1021a.dtsi new file +36 -0
new file mode 100644
index 0000000..5075c18
@@ -0,0 +1,405 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.

arch/arm/boot/dts/ls1021a.dtsi line 46

Quoted 10 lines
arch/arm/boot/dts/ls1021a.dtsi new file +10 -0
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */

DT maintainers,

I would like to confirm this is a appropriate copyright for device tree sources, as it sets the example how we should migrate from the existing GPL. If we merge it, I assume that a lot of future files will likely follow the example.

Shawn

maintainer
#3 lore raw

PATCH v5 1/6 ARM: dts: Add SoC level device tree support for LS1021A

Quoted 55 lines · On Sunday 19 October 2014 09:17:46 Shawn Guo wrote:
Quoted 42 lines
arch/arm/boot/dts/ls1021a.dtsi new file +36 -0
new file mode 100644
index 0000000..5075c18
@@ -0,0 +1,405 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.

arch/arm/boot/dts/ls1021a.dtsi line 46

Quoted 10 lines
arch/arm/boot/dts/ls1021a.dtsi new file +10 -0
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */

DT maintainers,

Quoted 4 lines

I would like to confirm this is a appropriate copyright for device tree sources, as it sets the example how we should migrate from the existing GPL. If we merge it, I assume that a lot of future files will likely follow the example.

The license is fine as far as I can tell, but the first half mentions 'library' three times, and that should probably be changed to 'file'.

The Allwinner dts files had the same text and are now changing it to say 'file'.

Arnd

#4 lore raw

PATCH v5 1/6 ARM: dts: Add SoC level device tree support for LS1021A

In reply to Jingchang Lu

arch/arm/boot/dts/ls1021a.dtsi line 62

Quoted 12 lines · Jingchang Lu
arch/arm/boot/dts/ls1021a.dtsi new file +12 -0
+/ {
+	compatible = "fsl,ls1021a";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
+		serial4 = &lpuart4;
+		serial5 = &lpuart5;
+		sysclk = &sysclk;

What is this sysclk aliase used for?

Review

Quoted 1 line
(quoted diff) +1 -0
+		};

Bad indent.

Quoted 14 lines
arch/arm/boot/dts/ls1021a.dtsi new file +14 -0
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at f00 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0xf00>;
+		};
+
+		cpu at f01 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";

arch/arm/boot/dts/ls1021a.dtsi line 87

Quoted 10 lines
arch/arm/boot/dts/ls1021a.dtsi new file +10 -0
+			reg = <0xf01>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

I like this indent style ...

arch/arm/boot/dts/ls1021a.dtsi line 93

Quoted 6 lines
arch/arm/boot/dts/ls1021a.dtsi new file +6 -0
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;

... not this style. Please fix such indents through the file.

Review

Quoted 1 line
(quoted diff) +1 -0
+	};

Shawn

author
#5 lore raw

PATCH v5 1/6 ARM: dts: Add SoC level device tree support for LS1021A

Quoted 13 lines

-----Original Message-----
From: Shawn Guo [mailto:shawn.guo at linaro.org]
Sent: Sunday, October 19, 2014 9:37 AM
To: Lu Jingchang-B35083
Cc: arnd at arndb.de; mark.rutland at arm.com; linux-arm- kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Jingchang- B35083; Badola Nikhil-B46172; Zhao Chenhui-B35336; Gupta Suresh-B42813; Leekha Shaveta-B20052; Gupta Ruchika-R66431; Sharma Bhupesh-B45370; Fu Chao-B44548; Xiubo Li-B47053
Subject: Re: [PATCHv5 1/6] ARM: dts: Add SoC level device tree support for LS1021A

On Mon, Oct 13, 2014 at 05:35:58PM +0800, Jingchang Lu wrote:

Quoted 14 lines

arch/arm/boot/dts/ls1021a.dtsi line 62

Quoted 12 lines
arch/arm/boot/dts/ls1021a.dtsi new file +12 -0
+/ {
+	compatible = "fsl,ls1021a";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
+		serial4 = &lpuart4;
+		serial5 = &lpuart5;
+		sysclk = &sysclk;

What is this sysclk aliase used for?

The sysclk alias is used by dtb fixup stage in u-boot to set the proper clk frequency for its configurable. The sysclk is compatible to "fixed-clock" but there may be more than one "fixed-clock" source and only the sysclk is desired, so an alias is add to located it exclusively. Thanks.

Quoted 36 lines

Review

Quoted 2 lines
(quoted diff) +1 -0
+		};

Bad indent.

Quoted 11 lines
arch/arm/boot/dts/ls1021a.dtsi new file +11 -0
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at f00 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0xf00>;
+		};
+

arch/arm/boot/dts/ls1021a.dtsi

Quoted 10 lines
arch/arm/boot/dts/ls1021a.dtsi new file +10 -0
+		cpu at f01 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0xf01>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |

IRQ_TYPE_LEVEL_LOW)>,

Review

Quoted 1 line
(quoted diff) +1 -0
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |

IRQ_TYPE_LEVEL_LOW)>,

Review

Quoted 1 line
(quoted diff) +1 -0
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |

IRQ_TYPE_LEVEL_LOW)>,

Review

Quoted 1 line
(quoted diff) +1 -0
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |

IRQ_TYPE_LEVEL_LOW)>;

I like this indent style ...

Quoted 8 lines

arch/arm/boot/dts/ls1021a.dtsi line 93

Quoted 6 lines
arch/arm/boot/dts/ls1021a.dtsi new file +6 -0
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;

... not this style. Please fix such indents through the file.

I will, thanks.

Best Regards,
Jingchang

Quoted 4 lines

Review

Quoted 2 lines
(quoted diff) +1 -0
+	};

Shawn

author
#6 lore raw

PATCH v5 2/6 ARM: dts: Add initial LS1021A QDS board dts support

In reply to Jingchang Lu

From: Jingchang Lu <[email protected]>

Signed-off-by Alison Wang <[email protected]>
Signed-off-by Chao Fu <[email protected]>
Signed-off-by Jason Jin <[email protected]>
Signed-off-by Xiubo Li <[email protected]>
Signed-off-by Bhupesh Sharma <[email protected]>
Signed-off-by Jaiprakash Singh <[email protected]>
Signed-off-by Jingchang Lu <[email protected]>
---
 arch/arm/boot/dts/Makefile        |   1 +
 arch/arm/boot/dts/ls1021a-qds.dts | 240 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 241 insertions(+)
 create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
arch/arm/boot/dts/Makefile +1 -0
index 8f12390..f89e5da 100644
@@ -251,6 +251,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6q-tx6q-1110.dtb \
 	imx6sl-evk.dtb \
 	imx6sx-sdb.dtb \
+	ls1021a-qds.dtb \
 	vf610-colibri-eval-v3.dtb \
 	vf610-cosmic.dtb \
 	vf610-twr.dtb
arch/arm/boot/dts/ls1021a-qds.dts new file +240 -0

240 lines not on this page · raw message

Signature · 1 line
1.8.0
#7 lore raw

PATCH v5 2/6 ARM: dts: Add initial LS1021A QDS board dts support

Quoted 2 lines · Jingchang Lu

From: Jingchang Lu <[email protected]>

Generally, blank commit log is not good. In this case, it should be helpful to put a brief introduction to LS1021A QDS board here.

Also please add a reference to the documents (user manual, schematics, etc.) of the board if they are publicly available somewhere.

Shawn

Quoted 7 lines
Signed-off-by Alison Wang <[email protected]>
Signed-off-by Chao Fu <[email protected]>
Signed-off-by Jason Jin <[email protected]>
Signed-off-by Xiubo Li <[email protected]>
Signed-off-by Bhupesh Sharma <[email protected]>
Signed-off-by Jaiprakash Singh <[email protected]>
Signed-off-by Jingchang Lu <[email protected]>
author
#8 lore raw

PATCH v5 3/6 ARM: dts: Add initial LS1021A TWR board dts support

In reply to Jingchang Lu
Signed-off-by Chen Lu <[email protected]>
Signed-off-by Chao Fu <[email protected]>
Signed-off-by Jingchang Lu <[email protected]>
---
 arch/arm/boot/dts/Makefile        |   1 +
 arch/arm/boot/dts/ls1021a-twr.dts | 127 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)
 create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts
arch/arm/boot/dts/Makefile +1 -0
index f89e5da..dfc7deb 100644
@@ -252,6 +252,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6sl-evk.dtb \
 	imx6sx-sdb.dtb \
 	ls1021a-qds.dtb \
+	ls1021a-twr.dtb \
 	vf610-colibri-eval-v3.dtb \
 	vf610-cosmic.dtb \
 	vf610-twr.dtb
arch/arm/boot/dts/ls1021a-twr.dts new file +127 -0

127 lines not on this page · raw message

Signature · 1 line
1.8.0
#9 lore raw

PATCH v5 3/6 ARM: dts: Add initial LS1021A TWR board dts support

Quoted 3 lines · Jingchang Lu
Signed-off-by Chen Lu <[email protected]>
Signed-off-by Chao Fu <[email protected]>
Signed-off-by Jingchang Lu <[email protected]>

Have something in the commit log, please.

Quoted 82 lines
---
 arch/arm/boot/dts/Makefile        |   1 +
 arch/arm/boot/dts/ls1021a-twr.dts | 127 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)
 create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts
arch/arm/boot/dts/Makefile +1 -0
index f89e5da..dfc7deb 100644
@@ -252,6 +252,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6sl-evk.dtb \
 	imx6sx-sdb.dtb \
 	ls1021a-qds.dtb \
+	ls1021a-twr.dtb \
 	vf610-colibri-eval-v3.dtb \
 	vf610-cosmic.dtb \
 	vf610-twr.dtb
arch/arm/boot/dts/ls1021a-twr.dts new file +58 -0
new file mode 100755
index 0000000..1e463fe
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+	model = "LS1021A TWR Board";
+
+	aliases {
+		enet2_rgmii_phy = &rgmii_phy1;
+		enet0_sgmii_phy = &sgmii_phy2;
+		enet1_sgmii_phy = &sgmii_phy0;
+	};

arch/arm/boot/dts/ls1021a-twr.dts line 68

Quoted 10 lines
arch/arm/boot/dts/ls1021a-twr.dts new file +10 -0
+};
+
+&dspi1 {
+	bus-num = <0>;
+	status = "okay";
+
+	dspiflash: s25fl064k at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25fl064k";

Is this a documented compatible?

Quoted 30 lines
arch/arm/boot/dts/ls1021a-twr.dts new file +30 -0
+		spi-max-frequency = <16000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	/* NOR, and CPLD on board */
+	ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
+	status = "okay";
+
+	nor at 0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x8000000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};

arch/arm/boot/dts/ls1021a-twr.dts line 108

Quoted 10 lines
arch/arm/boot/dts/ls1021a-twr.dts new file +10 -0
+};
+
+&lpuart0 {
+	status = "okay";
+};
+
+&mdio0 {
+	sgmii_phy0: ethernet-phy at 0 {
+		reg = <0x0>;
+	};

Please have new line between nodes.

arch/arm/boot/dts/ls1021a-twr.dts line 117

Quoted 9 lines
arch/arm/boot/dts/ls1021a-twr.dts new file +9 -0
+	rgmii_phy1: ethernet-phy at 1 {
+		reg = <0x1>;
+	};
+	sgmii_phy2: ethernet-phy at 2 {
+		reg = <0x2>;
+	};
+	tbi1: tbi-phy at 1f {
+		reg = <0x1f>;
+		device_type = "tbi-phy";

I cannot find this "tbi-phy" documented anywhere in the bindings folder.

Shawn

Quoted 13 lines
arch/arm/boot/dts/ls1021a-twr.dts new file +10 -0
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
Signature · 1 line
1.8.0
author
#10 lore raw

PATCH v5 4/6 dt-bindings: arm: add Freescale LS1021A SoC device tree binding

In reply to Jingchang Lu
Signed-off-by Jingchang Lu <[email protected]>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 38 +++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
Documentation/devicetree/bindings/arm/fsl.txt +38 -0
index e935d7d..4e8b7df 100644
@@ -74,3 +74,41 @@ Required root node properties:
 i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
+
+
+Freescale LS1021A Platform Device Tree Bindings
+------------------------------------------------
+
+Required root node compatible properties:
+  - compatible = "fsl,ls1021a";
+
+Freescale LS1021A SoC-specific Device Tree Bindings
+-------------------------------------------
+
+Freescale SCFG
+  SCFG is the supplemental configuration unit, that provides SoC specific
+configuration and status registers for the chip. Such as getting PEX port
+status.
+  Required properties:
+  - compatible: should be "fsl,ls1021a-scfg"
+  - reg: should contain base address and length of SCFG memory-mapped registers
+
+Example:
+	scfg: scfg at 1570000 {
+		compatible = "fsl,ls1021a-scfg";
+		reg = <0x0 0x1570000 0x0 0x10000>;
+	};
+
+Freescale DCFG
+  DCFG is the device configuration unit, that provides general purpose
+configuration and status for the device. Such as setting the secondary
+core start address and release the secondary core from holdoff and startup.
+  Required properties:
+  - compatible: should be "fsl,ls1021a-dcfg"
+  - reg : should contain base address and length of DCFG memory-mapped registers
+
+Example:
+	dcfg: dcfg at 1ee0000 {
+		compatible = "fsl,ls1021a-dcfg";
+		reg = <0x0 0x1ee0000 0x0 0x10000>;
+	};
Signature · 1 line
1.8.0
author
#11 lore raw

PATCH v5 5/6 ARM: imx: Add initial support for Freescale LS1021A

In reply to Jingchang Lu

From: Jingchang Lu <[email protected]>

The LS1021A SoC is a dual-core Cortex-A7 based processor, this add the initial support for it.

Signed-off-by Jingchang Lu <[email protected]>
---
 arch/arm/mach-imx/Kconfig        | 14 ++++++++++++++
 arch/arm/mach-imx/Makefile       |  2 ++
 arch/arm/mach-imx/mach-ls1021a.c | 21 +++++++++++++++++++++
 3 files changed, 37 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
arch/arm/mach-imx/Kconfig +14 -0
index 11b2957..49a0096 100644
@@ -639,6 +639,20 @@ config SOC_VF610
 	help
 	  This enable support for Freescale Vybrid VF610 processor.
 
+config FSL_SOC
+	bool
+
+config SOC_LS1021A
+	bool "Freescale LS1021A support"
+	select ARM_GIC
+	select HAVE_ARM_ARCH_TIMER
+	select FSL_SOC
+	select PCI_DOMAINS if PCI
+	select ZONE_DMA if ARM_LPAE
+
+	help
+	  This enable support for Freescale LS1021A processor.
+
 endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
arch/arm/mach-imx/Makefile +2 -0
index 6e4fcd8..ce137bc 100644
@@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
 obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
 
+obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
+
 obj-y += devices/
arch/arm/mach-imx/mach-ls1021a.c new file +21 -0
new file mode 100644
index 0000000..9d2034b
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const char * const ls1021a_dt_compat[] __initconst = {
+	"fsl,ls1021a",
+	NULL,
+};
+
+DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+	.dt_compat	= ls1021a_dt_compat,
+MACHINE_END
Signature · 1 line
1.8.0
author
#12 lore raw

PATCH v5 6/6 ARM: imx: Add Freescale LS1021A SMP support

In reply to Jingchang Lu

From: Jingchang Lu <[email protected]>

Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core.

Signed-off-by Jingchang Lu <[email protected]>
---
 arch/arm/mach-imx/Makefile       |  2 +-
 arch/arm/mach-imx/common.h       |  1 +
 arch/arm/mach-imx/mach-ls1021a.c |  1 +
 arch/arm/mach-imx/platsmp.c      | 32 ++++++++++++++++++++++++++++++++
 4 files changed, 35 insertions(+), 1 deletion(-)
arch/arm/mach-imx/Makefile +1 -1
index ce137bc..38d75e2 100644
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-ifdef CONFIG_SOC_IMX6
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
 AFLAGS_headsmp.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
arch/arm/mach-imx/common.h +1 -0
index 1dabf43..c473ca5 100644
@@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {}
 #endif
 
 extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
 
 #endif
arch/arm/mach-imx/mach-ls1021a.c +1 -0
index 9d2034b..b89c858 100644
@@ -17,5 +17,6 @@ static const char * const ls1021a_dt_compat[] __initconst = {
 };
 
 DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+	.smp		= smp_ops(ls1021a_smp_ops),
 	.dt_compat	= ls1021a_dt_compat,
 MACHINE_END
arch/arm/mach-imx/platsmp.c +32 -0
index 771bd25..69b87ca 100644
@@ -16,6 +16,8 @@
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 
 #include "common.h"
 #include "hardware.h"

@@ -94,3 +96,33 @@ struct smp_operations  imx_smp_ops __initdata = {
 	.cpu_kill		= imx_cpu_kill,
 #endif
 };
+
+#define DCFG_CCSR_SCRATCHRW1	0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+	return 0;
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
+{
+	struct device_node *np;
+	void __iomem *dcfg_base;
+	unsigned long paddr;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+	dcfg_base = of_iomap(np, 0);
+	BUG_ON(!dcfg_base);
+
+	paddr = virt_to_phys(secondary_startup);
+	writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
+
+	iounmap(dcfg_base);
+}
+
+struct smp_operations  ls1021a_smp_ops __initdata = {
+	.smp_prepare_cpus	= ls1021a_smp_prepare_cpus,
+	.smp_boot_secondary	= ls1021a_boot_secondary,
+};
Signature · 1 line
1.8.0
#13 lore raw

PATCH v5 6/6 ARM: imx: Add Freescale LS1021A SMP support

Quoted 78 lines · Jingchang Lu

From: Jingchang Lu <[email protected]>

Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core.

Signed-off-by Jingchang Lu <[email protected]>

---

arch/arm/mach-imx/Makefile       |  2 +-
arch/arm/mach-imx/common.h       |  1 +
arch/arm/mach-imx/mach-ls1021a.c |  1 +
arch/arm/mach-imx/platsmp.c      | 32 ++++++++++++++++++++++++++++++++
4 files changed, 35 insertions(+), 1 deletion(-)
arch/arm/mach-imx/Makefile +0 -0
index ce137bc..38d75e2 100644
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o

obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o

arch/arm/mach-imx/Makefile +1 -1
-ifdef CONFIG_SOC_IMX6
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)

AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o

arch/arm/mach-imx/common.h +1 -0
index 1dabf43..c473ca5 100644
@@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {}
 #endif
 
 extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
 
 #endif
arch/arm/mach-imx/mach-ls1021a.c +1 -0
index 9d2034b..b89c858 100644
@@ -17,5 +17,6 @@ static const char * const ls1021a_dt_compat[] __initconst = {
 };
 
 DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+	.smp		= smp_ops(ls1021a_smp_ops),
 	.dt_compat	= ls1021a_dt_compat,

MACHINE_END

arch/arm/mach-imx/platsmp.c +15 -0
index 771bd25..69b87ca 100644
@@ -16,6 +16,8 @@
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 
 #include "common.h"
 #include "hardware.h"

@@ -94,3 +96,33 @@ struct smp_operations  imx_smp_ops __initdata = {
 	.cpu_kill		= imx_cpu_kill,
 #endif
 };
+
+#define DCFG_CCSR_SCRATCHRW1	0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+	return 0;
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
+{
+	struct device_node *np;

arch/arm/mach-imx/platsmp.c struct smp_operations imx_smp_ops __initdata = { · line 121

Quoted 10 lines
arch/arm/mach-imx/platsmp.c +10 -0
+	void __iomem *dcfg_base;
+	unsigned long paddr;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+	dcfg_base = of_iomap(np, 0);
+	BUG_ON(!dcfg_base);
+
+	paddr = virt_to_phys(secondary_startup);
+	writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
+

This seems odd, why are we writing the startup address to DCFG_CCSR_SCRATCHRW1?

Quoted 10 lines
arch/arm/mach-imx/platsmp.c +7 -0
+	iounmap(dcfg_base);
+}
+
+struct smp_operations  ls1021a_smp_ops __initdata = {
+	.smp_prepare_cpus	= ls1021a_smp_prepare_cpus,
+	.smp_boot_secondary	= ls1021a_boot_secondary,
+};
Signature · 1 line
1.8.0

- k

Signature · 3 lines
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#14 lore raw

PATCH v5 6/6 ARM: imx: Add Freescale LS1021A SMP support

Quoted 98 lines

-----Original Message-----
From: Kumar Gala [mailto:galak at codeaurora.org]
Sent: Thursday, October 16, 2014 10:31 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; mark.rutland at arm.com; devicetree at vger.kernel.org; Lu Jingchang-B35083; linux-arm-kernel at lists.infradead.org; arnd at arndb.de
Subject: Re: [PATCHv5 6/6] ARM: imx: Add Freescale LS1021A SMP support

Quoted 84 lines · Jingchang Lu

From: Jingchang Lu <[email protected]>

Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core.

Signed-off-by Jingchang Lu <[email protected]>

---

arch/arm/mach-imx/Makefile       |  2 +-
arch/arm/mach-imx/common.h       |  1 +
arch/arm/mach-imx/mach-ls1021a.c |  1 +
arch/arm/mach-imx/platsmp.c      | 32 ++++++++++++++++++++++++++++++++
4 files changed, 35 insertions(+), 1 deletion(-)
arch/arm/mach-imx/Makefile +0 -0
index ce137bc..38d75e2 100644
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o

obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o

arch/arm/mach-imx/Makefile +1 -1
-ifdef CONFIG_SOC_IMX6
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)

AFLAGS_headsmp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 1dabf43..c473ca5 100644

arch/arm/mach-imx/common.h +1 -0
@@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {}
 #endif
 
 extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
 
 #endif
arch/arm/mach-imx/mach-ls1021a.c +1 -0
index 9d2034b..b89c858 100644
@@ -17,5 +17,6 @@ static const char * const ls1021a_dt_compat[]
 __initconst = { };
 
 DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+	.smp		= smp_ops(ls1021a_smp_ops),
 	.dt_compat	= ls1021a_dt_compat,

MACHINE_END

arch/arm/mach-imx/platsmp.c +20 -0
index 771bd25..69b87ca 100644
@@ -16,6 +16,8 @@
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 
 #include "common.h"
 #include "hardware.h"

@@ -94,3 +96,33 @@ struct smp_operations  imx_smp_ops __initdata = {
 	.cpu_kill		= imx_cpu_kill,
 #endif
 };
+
+#define DCFG_CCSR_SCRATCHRW1	0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct
+task_struct *idle) {
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+	return 0;
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus) {
+	struct device_node *np;
+	void __iomem *dcfg_base;
+	unsigned long paddr;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+	dcfg_base = of_iomap(np, 0);
+	BUG_ON(!dcfg_base);
Quoted 8 lines

arch/arm/mach-imx/platsmp.c struct smp_operations imx_smp_ops __initdata = { · line 121

Quoted 5 lines
arch/arm/mach-imx/platsmp.c +5 -0
+
+	paddr = virt_to_phys(secondary_startup);
+	writel_relaxed(cpu_to_be32(paddr), dcfg_base +
+DCFG_CCSR_SCRATCHRW1);
+

This seems odd, why are we writing the startup address to DCFG_CCSR_SCRATCHRW1?

It is the secondary cpu's executing address for smp kernel image, the secondary cpu will jump to this address after wakeup during the smp initialization. Thanks.

Best Regards,
Jingchang

#15 lore raw

PATCH v5 6/6 ARM: imx: Add Freescale LS1021A SMP support

Quoted 106 lines · Jingchang Lu
Quoted 98 lines

-----Original Message-----
From: Kumar Gala [mailto:galak at codeaurora.org]
Sent: Thursday, October 16, 2014 10:31 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; mark.rutland at arm.com; devicetree at vger.kernel.org; Lu Jingchang-B35083; linux-arm-kernel at lists.infradead.org; arnd at arndb.de
Subject: Re: [PATCHv5 6/6] ARM: imx: Add Freescale LS1021A SMP support

Quoted 84 lines · Jingchang Lu

From: Jingchang Lu <[email protected]>

Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core.

Signed-off-by Jingchang Lu <[email protected]>

---

arch/arm/mach-imx/Makefile       |  2 +-
arch/arm/mach-imx/common.h       |  1 +
arch/arm/mach-imx/mach-ls1021a.c |  1 +
arch/arm/mach-imx/platsmp.c      | 32 ++++++++++++++++++++++++++++++++
4 files changed, 35 insertions(+), 1 deletion(-)
arch/arm/mach-imx/Makefile +0 -0
index ce137bc..38d75e2 100644
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o

obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o

arch/arm/mach-imx/Makefile +1 -1
-ifdef CONFIG_SOC_IMX6
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)

AFLAGS_headsmp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 1dabf43..c473ca5 100644

arch/arm/mach-imx/common.h +1 -0
@@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {}
 #endif
 
 extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
 
 #endif
arch/arm/mach-imx/mach-ls1021a.c +1 -0
index 9d2034b..b89c858 100644
@@ -17,5 +17,6 @@ static const char * const ls1021a_dt_compat[]
 __initconst = { };
 
 DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+	.smp		= smp_ops(ls1021a_smp_ops),
 	.dt_compat	= ls1021a_dt_compat,

MACHINE_END

arch/arm/mach-imx/platsmp.c +20 -0
index 771bd25..69b87ca 100644
@@ -16,6 +16,8 @@
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 
 #include "common.h"
 #include "hardware.h"

@@ -94,3 +96,33 @@ struct smp_operations  imx_smp_ops __initdata = {
 	.cpu_kill		= imx_cpu_kill,
 #endif
 };
+
+#define DCFG_CCSR_SCRATCHRW1	0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct
+task_struct *idle) {
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+	return 0;
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus) {
+	struct device_node *np;
+	void __iomem *dcfg_base;
+	unsigned long paddr;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+	dcfg_base = of_iomap(np, 0);
+	BUG_ON(!dcfg_base);
Quoted 8 lines

arch/arm/mach-imx/platsmp.c struct smp_operations imx_smp_ops __initdata = { · line 121

Quoted 5 lines
arch/arm/mach-imx/platsmp.c +5 -0
+
+	paddr = virt_to_phys(secondary_startup);
+	writel_relaxed(cpu_to_be32(paddr), dcfg_base +
+DCFG_CCSR_SCRATCHRW1);
+

This seems odd, why are we writing the startup address to DCFG_CCSR_SCRATCHRW1?

Quoted 3 lines

It is the secondary cpu's executing address for smp kernel image, the secondary cpu will jump to this address after wakeup during the smp initialization. Thanks.

Is that a convention spec?d by HW or SW?

- k

Signature · 3 lines
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#16 lore raw

PATCH v5 6/6 ARM: imx: Add Freescale LS1021A SMP support

Quoted 123 lines

-----Original Message-----
From: Kumar Gala [mailto:galak at codeaurora.org]
Sent: Friday, October 17, 2014 8:27 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; mark.rutland at arm.com; devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; arnd at arndb.de
Subject: Re: [PATCHv5 6/6] ARM: imx: Add Freescale LS1021A SMP support

Quoted 109 lines · Jingchang Lu
Quoted 109 lines

-----Original Message-----
From: Kumar Gala [mailto:galak at codeaurora.org]
Sent: Thursday, October 16, 2014 10:31 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; mark.rutland at arm.com; devicetree at vger.kernel.org; Lu Jingchang-B35083; linux-arm-kernel at lists.infradead.org; arnd at arndb.de
Subject: Re: [PATCHv5 6/6] ARM: imx: Add Freescale LS1021A SMP support

Quoted 79 lines · Jingchang Lu

From: Jingchang Lu <[email protected]>

Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core.

Signed-off-by Jingchang Lu <[email protected]>

---

arch/arm/mach-imx/Makefile       |  2 +-
arch/arm/mach-imx/common.h       |  1 +
arch/arm/mach-imx/mach-ls1021a.c |  1 +
arch/arm/mach-imx/platsmp.c      | 32 ++++++++++++++++++++++++++++++++
4 files changed, 35 insertions(+), 1 deletion(-)
arch/arm/mach-imx/Makefile +0 -0
index ce137bc..38d75e2 100644
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o

obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o

arch/arm/mach-imx/Makefile +1 -1
-ifdef CONFIG_SOC_IMX6
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)

AFLAGS_headsmp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 1dabf43..c473ca5 100644

arch/arm/mach-imx/common.h +1 -0
@@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {}
 #endif
 
 extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
 
 #endif
arch/arm/mach-imx/mach-ls1021a.c +1 -0
index 9d2034b..b89c858 100644
@@ -17,5 +17,6 @@ static const char * const ls1021a_dt_compat[]
 __initconst = { };
 
 DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+	.smp		= smp_ops(ls1021a_smp_ops),
 	.dt_compat	= ls1021a_dt_compat,

MACHINE_END

(quoted diff) +0 -0

b/arch/arm/mach-imx/platsmp.c index 771bd25..69b87ca 100644

arch/arm/mach-imx/platsmp.c +15 -0
@@ -16,6 +16,8 @@
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 
 #include "common.h"
 #include "hardware.h"

@@ -94,3 +96,33 @@ struct smp_operations  imx_smp_ops __initdata = {
 	.cpu_kill		= imx_cpu_kill,
 #endif
 };
+
+#define DCFG_CCSR_SCRATCHRW1	0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct
+task_struct *idle) {
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+	return 0;
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus) {
+	struct device_node *np;
+	void __iomem *dcfg_base;

arch/arm/mach-imx/platsmp.c struct smp_operations imx_smp_ops __initdata = { · line 121

Quoted 10 lines
arch/arm/mach-imx/platsmp.c +10 -0
+	unsigned long paddr;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+	dcfg_base = of_iomap(np, 0);
+	BUG_ON(!dcfg_base);
+
+	paddr = virt_to_phys(secondary_startup);
+	writel_relaxed(cpu_to_be32(paddr), dcfg_base +
+DCFG_CCSR_SCRATCHRW1);
+

This seems odd, why are we writing the startup address to DCFG_CCSR_SCRATCHRW1?

Quoted 5 lines
Quoted 3 lines

It is the secondary cpu's executing address for smp kernel image, the secondary cpu will jump to this address after wakeup during the smp initialization. Thanks.

Is that a convention spec?d by HW or SW?

One is bootrom's convention, thanks.

Best Regards
Jinghcang

Quoted 6 lines

- k
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

#17 lore raw

PATCH v5 6/6 ARM: imx: Add Freescale LS1021A SMP support

In reply to Jingchang Lu

arch/arm/mach-imx/platsmp.c line 20

Quoted 10 lines · Jingchang Lu
arch/arm/mach-imx/platsmp.c +2 -0
index 771bd25..69b87ca 100644
@@ -16,6 +16,8 @@
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
+#include <linux/of_address.h>
+#include <linux/of.h>

Please group the headers into <linux/*> and sort them alphabetically.

Shawn

Quoted 3 lines
arch/arm/mach-imx/platsmp.c +0 -0
 #include "common.h"
 #include "hardware.h"