usb: dwc2: Add driver for Synopsis DWC2 USB IP block
PATCH 1/1 usb: dwc2: Add driver for Synopsis DWC2 USB IP block
From: Oleksandr Tymoshenko <[email protected]>
This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi.
This code has three checkpatch warnings, but to make sure it stays at least readable and clear, these are not fixed. These bugs are in the USB request handling combinatorial logic, so any abstracting of those is out of question.
Tested on DENX MCV (Altera SoCFPGA 5CSFXC6C6U23C8N) and RPi B+ (BCM2835).
--- README | 3 + drivers/usb/host/Makefile | 3 + drivers/usb/host/dwc2.c | 1055 +++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/dwc2.h | 782 +++++++++++++++++++++++++++++++++ include/usb.h | 3 +- 5 files changed, 1845 insertions(+), 1 deletion(-) create mode 100644 drivers/usb/host/dwc2.c create mode 100644 drivers/usb/host/dwc2.h
NOTE: Unless there are no objections, I would like to apply this.
README +3 -0
@@ -1459,6 +1459,9 @@ The following options need to be configured: CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset. + CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2 + HW module registers + - USB Device: Define the below if you wish to use the USB console. Once firmware is rebuilt from a serial console issue the
drivers/usb/host/Makefile +3 -0
@@ -45,3 +45,6 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o + +# designware +obj-$(CONFIG_USB_DWC2) += dwc2.o
drivers/usb/host/dwc2.c new file +1055 -0
1,055 lines not on this page · raw message
drivers/usb/host/dwc2.h new file +782 -0
782 lines not on this page · raw message
include/usb.h +2 -1
@@ -150,7 +150,8 @@ enum usb_init_type {defined (CONFIG_USB_OMAP3 ) ||defined (CONFIG_USB_DA8XX ) || \defined (CONFIG_USB_BLACKFIN ) ||defined (CONFIG_USB_AM35X ) || \defined (CONFIG_USB_MUSB_DSPS ) ||defined (CONFIG_USB_MUSB_AM35X ) || \ - defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI) +defined (CONFIG_USB_MUSB_OMAP2PLUS ) ||defined (CONFIG_USB_XHCI ) || \ + defined(CONFIG_USB_DWC2)int usb_lowlevel_init (int index,enum usb_init_type init,void **controller);int usb_lowlevel_stop (int index);
Signature · 1 line
2.1.1
PATCH 1/1 usb: dwc2: Add driver for Synopsis DWC2 USB IP block
Hi!
Quoted 8 lines
This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi.
This code has three checkpatch warnings, but to make sure it stays at least readable and clear, these are not fixed. These bugs are in the USB request handling combinatorial logic, so any abstracting of those is out of question.
Tested on DENX MCV (Altera SoCFPGA 5CSFXC6C6U23C8N) and RPi B+ (BCM2835).
The code also has ton of unused defines. You said you want them to document hardware, but do we really need
DWC2_HAINTMSK_CH7 _and_ DWC2_HAINTMSK_CH7_OFFSET, both unused? They both contain same information...
Quoted 1 line
NOTE: Unless there are no objections, I would like to apply this.
Parse error :-).
README The following options need to be configured: · line 1463
Quoted 10 lines
README +2
-0@@ -1459,6 +1459,9 @@ The following options need to be configured: CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset. + CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2 + HW module registers
Missing . at end of sentence.
drivers/usb/host/dwc2.c line 6
Quoted 10 lines
index 0000000..cff36f8
drivers/usb/host/dwc2.c new file +6
-0@@ -0,0 +1,1055 @@ +/* +* Copyright (C) 2012 Oleksandr Tymoshenko <[email protected]> +* Copyright (C) 2014 Marek Vasut <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0 +*/
Is this supposed to be "GPL-2.0+"?
Quoted 7 lines
drivers/usb/host/dwc2.c new file +7
-0+switch (cmd->requesttype & ~USB_DIR_IN ) { +case 0 : + *(uint16_t *)buffer =cpu_to_le16 (1 ); + len =2 ; +break ; +case USB_RECIP_INTERFACE : + *(uint16_t *)buffer =cpu_to_le16 (0 );
drivers/usb/host/dwc2.c line 452
Quoted 10 lines
drivers/usb/host/dwc2.c new file +10
-0+ len =2 ; +break ; +case USB_RECIP_ENDPOINT : + *(uint16_t *)buffer =cpu_to_le16 (0 ); + len =2 ; +break ; +case USB_TYPE_CLASS : + *(uint32_t *)buffer =cpu_to_le32 (0 ); + len =4 ; +break ;
You can get rid of endianness conversion for zeros.
And can use same code for USB_RECIP_INTERFACE and USB_RECIP_ENDPOINT.
Quoted 15 lines
drivers/usb/host/dwc2.c new file +15
-0+switch (cmd->requesttype & ~USB_DIR_IN ) { +case 0 : +switch (wValue &0xff00 ) { +case 0x0100 :/* device descriptor */ + len =min3 (txlen,sizeof (root_hub_dev_des), wLength); +memcpy (buffer, root_hub_dev_des, len); +break ; +case 0x0200 :/* configuration descriptor */ + len =min3 (txlen,sizeof (root_hub_config_des), wLength); +memcpy (buffer, root_hub_config_des, len); +break ; +case 0x0300 :/* string descriptors */ +switch (wValue &0xff ) { +case 0x00 : + len = min3(txlen, sizeof(root_hub_str_index0),
drivers/usb/host/dwc2.c line 528
Quoted 10 lines
drivers/usb/host/dwc2.c new file +10
-0+ wLength); +memcpy (buffer, root_hub_str_index0, len); +break ; +case 0x01 : + len =min3 (txlen,sizeof (root_hub_str_index1), + wLength); +memcpy (buffer, root_hub_str_index1, len); +break ; + } +break ;
Helper function that takes root_hub_str_index0 or similar, then does len and memcpy?
Otherwise looks good to me,
Quoted 32 lines
drivers/usb/host/dwc2.c new file +32
-0+#define DWC2_HAINT_CH0 (1 << 0) +#define DWC2_HAINT_CH0_OFFSET 0 +#define DWC2_HAINT_CH1 (1 << 1) +#define DWC2_HAINT_CH1_OFFSET 1 +#define DWC2_HAINT_CH2 (1 << 2) +#define DWC2_HAINT_CH2_OFFSET 2 +#define DWC2_HAINT_CH3 (1 << 3) +#define DWC2_HAINT_CH3_OFFSET 3 +#define DWC2_HAINT_CH4 (1 << 4) +#define DWC2_HAINT_CH4_OFFSET 4 +#define DWC2_HAINT_CH5 (1 << 5) +#define DWC2_HAINT_CH5_OFFSET 5 +#define DWC2_HAINT_CH6 (1 << 6) +#define DWC2_HAINT_CH6_OFFSET 6 +#define DWC2_HAINT_CH7 (1 << 7) +#define DWC2_HAINT_CH7_OFFSET 7 +#define DWC2_HAINT_CH8 (1 << 8) +#define DWC2_HAINT_CH8_OFFSET 8 +#define DWC2_HAINT_CH9 (1 << 9) +#define DWC2_HAINT_CH9_OFFSET 9 +#define DWC2_HAINT_CH10 (1 << 10) +#define DWC2_HAINT_CH10_OFFSET 10 +#define DWC2_HAINT_CH11 (1 << 11) +#define DWC2_HAINT_CH11_OFFSET 11 +#define DWC2_HAINT_CH12 (1 << 12) +#define DWC2_HAINT_CH12_OFFSET 12 +#define DWC2_HAINT_CH13 (1 << 13) +#define DWC2_HAINT_CH13_OFFSET 13 +#define DWC2_HAINT_CH14 (1 << 14) +#define DWC2_HAINT_CH14_OFFSET 14 +#define DWC2_HAINT_CH15 (1 << 15) +#define DWC2_HAINT_CH15_OFFSET 15
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH 1/1 usb: dwc2: Add driver for Synopsis DWC2 USB IP block
Quoted 10 lines · Pavel Machek
Hi!
Quoted 8 lines
This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi.
This code has three checkpatch warnings, but to make sure it stays at least readable and clear, these are not fixed. These bugs are in the USB request handling combinatorial logic, so any abstracting of those is out of question.
Quoted 8 lines
Quoted 2 lines
Tested on DENX MCV (Altera SoCFPGA 5CSFXC6C6U23C8N) and RPi B+ (BCM2835).
The code also has ton of unused defines. You said you want them to document hardware, but do we really need
DWC2_HAINTMSK_CH7_and_DWC2_HAINTMSK_CH7_OFFSET, both unused? They both contain same information...
They're mask and offset, two different things in fact.
Quoted 3 lines
Quoted 1 line
NOTE: Unless there are no objections, I would like to apply this.
Parse error :-).
Excuse me ?
[...]
Quoted 11 lines
Quoted 11 lines
drivers/usb/host/dwc2.c new file +11
-0+switch (cmd->requesttype & ~USB_DIR_IN ) { +case 0 : + *(uint16_t *)buffer =cpu_to_le16 (1 ); + len =2 ; +break ; +case USB_RECIP_INTERFACE : + *(uint16_t *)buffer =cpu_to_le16 (0 ); + len =2 ; +break ; +case USB_RECIP_ENDPOINT : + *(uint16_t *)buffer =cpu_to_le16 (0 );
Quoted 8 lines
drivers/usb/host/dwc2.c line 452
Quoted 6 lines
drivers/usb/host/dwc2.c new file +6
-0+ len =2 ; +break ; +case USB_TYPE_CLASS : + *(uint32_t *)buffer =cpu_to_le32 (0 ); + len =4 ; +break ;You can get rid of endianness conversion for zeros.
Yes, but being inconsistent about the buffer endianness conversion would only lead to bugs in case someone started hacking on this code. So I would really like to keep this in place for consistency's sake.
Quoted 1 line
And can use same code for
USB_RECIP_INTERFACEandUSB_RECIP_ENDPOINT.
Done.
Quoted 20 lines
Quoted 20 lines
drivers/usb/host/dwc2.c new file +20
-0+switch (cmd->requesttype & ~USB_DIR_IN ) { +case 0 : +switch (wValue &0xff00 ) { +case 0x0100 :/* device descriptor */ + len =min3 (txlen,sizeof (root_hub_dev_des), wLength); +memcpy (buffer, root_hub_dev_des, len); +break ; +case 0x0200 :/* configuration descriptor */ + len =min3 (txlen,sizeof (root_hub_config_des), wLength); +memcpy (buffer, root_hub_config_des, len); +break ; +case 0x0300 :/* string descriptors */ +switch (wValue &0xff ) { +case 0x00 : + len =min3 (txlen,sizeof (root_hub_str_index0), + wLength); +memcpy (buffer, root_hub_str_index0, len); +break ; +case 0x01 : + len = min3(txlen, sizeof(root_hub_str_index1),
Quoted 8 lines
drivers/usb/host/dwc2.c line 528
Quoted 5 lines
drivers/usb/host/dwc2.c new file +5
-0+ wLength); +memcpy (buffer, root_hub_str_index1, len); +break ; + } +break ;Helper function that takes
root_hub_str_index0or similar, then does len and memcpy?
A helper function which would basically take parameters of the min3() and memcpy() as parameters? Do you consider this worth it ?
Quoted 1 line
Acked-by Pavel Machek <[email protected]>
[...]
PATCH v2 1/1 usb: dwc2: Add driver for Synopsis DWC2 USB IP block
In reply to Marek VasutFrom: Oleksandr Tymoshenko <[email protected]>
This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi.
This code has three checkpatch warnings, but to make sure it stays at least readable and clear, these are not fixed. These bugs are in the USB request handling combinatorial logic, so any abstracting of those is out of question.
Tested on DENX MCV (Altera SoCFPGA 5CSFXC6C6U23C8N) and RPi B+ (BCM2835).
--- README | 3 + drivers/usb/host/Makefile | 3 + drivers/usb/host/dwc2.c | 1053 +++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/dwc2.h | 782 +++++++++++++++++++++++++++++++++ include/usb.h | 3 +- 5 files changed, 1843 insertions(+), 1 deletion(-) create mode 100644 drivers/usb/host/dwc2.c create mode 100644 drivers/usb/host/dwc2.h
V2: Fix missing fullstop in README
Fix license to be GPL 2.0+
Re-use the code for USB_RECIP_INTERFACE/USB_RECIP_ENDPOINT
README +3 -0
@@ -1465,6 +1465,9 @@ The following options need to be configured: CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset. + CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2 + HW module registers. + - USB Device: Define the below if you wish to use the USB console. Once firmware is rebuilt from a serial console issue the
drivers/usb/host/Makefile +3 -0
@@ -45,3 +45,6 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o + +# designware +obj-$(CONFIG_USB_DWC2) += dwc2.o
drivers/usb/host/dwc2.c new file +1053 -0
1,053 lines not on this page · raw message
drivers/usb/host/dwc2.h new file +782 -0
782 lines not on this page · raw message
include/usb.h +2 -1
@@ -150,7 +150,8 @@ enum usb_init_type {defined (CONFIG_USB_OMAP3 ) ||defined (CONFIG_USB_DA8XX ) || \defined (CONFIG_USB_BLACKFIN ) ||defined (CONFIG_USB_AM35X ) || \defined (CONFIG_USB_MUSB_DSPS ) ||defined (CONFIG_USB_MUSB_AM35X ) || \ - defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI) +defined (CONFIG_USB_MUSB_OMAP2PLUS ) ||defined (CONFIG_USB_XHCI ) || \ + defined(CONFIG_USB_DWC2)int usb_lowlevel_init (int index,enum usb_init_type init,void **controller);int usb_lowlevel_stop (int index);
Signature · 1 line
2.0.0
PATCH v2 1/1 usb: dwc2: Add driver for Synopsis DWC2 USB IP block
Quoted 8 lines · Marek Vasut
From: Oleksandr Tymoshenko <[email protected]>
This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi.
This code has three checkpatch warnings, but to make sure it stays at least readable and clear, these are not fixed. These bugs are in the USB request handling combinatorial logic, so any abstracting of those is out of question.
Quoted 7 lines
Tested on DENX MCV (Altera SoCFPGA 5CSFXC6C6U23C8N) and RPi B+ (BCM2835).
Signed-off-by Oleksandr Tymoshenko <[email protected]>Signed-off-by Stephen Warren <[email protected]>Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
Marek Vasut
AppliedPATCH v2 1/1 usb: dwc2: Add driver for Synopsis DWC2 USB IP block
Quoted 13 lines · Pavel Machek
Quoted 12 lines · Marek Vasut
From: Oleksandr Tymoshenko <[email protected]>
This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi.
This code has three checkpatch warnings, but to make sure it stays at least readable and clear, these are not fixed. These bugs are in the USB request handling combinatorial logic, so any abstracting of those is out of question.
Tested on DENX MCV (Altera SoCFPGA 5CSFXC6C6U23C8N) and RPi B+ (BCM2835).
Quoted 7 lines
Quoted 5 lines
Signed-off-by Oleksandr Tymoshenko <[email protected]>Signed-off-by Stephen Warren <[email protected]>Signed-off-by Marek Vasut <[email protected]>Cc Chin Liang See <[email protected]>Cc Dinh Nguyen <[email protected]>Acked-by Pavel Machek <[email protected]>
Applied, thanks!
Best regards,
Marek Vasut