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keystone2: generalize keystone_net driver usage

PATCH New Ivan Khoronzhuk 2 participants 11 messages Sep 29, 2014 – Oct 23, 2014

Subsystems (2)
Network drivers Arm (32-bit)
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Ivan Khoronzhuk

author
#0 lore raw

v2 cover keystone2: generalize keystone_net driver usage

This series generalize keystone_net driver usage in order to add keystone2 K2E/K2L SoCs support.

Based on
"[U-boot] [Patch v2] keystone: usb: add support of usb xhci"
https://patchwork.ozlabs.org/patch/386506/

v2..v1:
net: keystone_net: remove redundant code from keystone_net.c
- remove spurious function rename

Hao Zhang (1):
net: keystone_net: remove SoC specific emac_regs structure

Ivan Khoronzhuk (3):
net: keystone_net: add support for NETCP v1.5
net: keystone_net: move header file from arch to ti-common
net: keystone_net: remove redundant code from keystone_net.c

Vitaly Andrianov (1):
net: keystone_net: increase MDIO clock frequency

 arch/arm/include/asm/arch-keystone/emac_defs.h     | 237 --------------------
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h |   3 +
 arch/arm/include/asm/arch-keystone/hardware.h      |   2 +
 arch/arm/include/asm/ti-common/keystone_net.h      | 248 +++++++++++++++++++++
 board/ti/ks2_evm/board.c                           |  11 +-
 board/ti/ks2_evm/board.h                           |   2 +-
 board/ti/ks2_evm/board_k2hk.c                      |   2 +-
 drivers/net/keystone_net.c                         |  27 +--
 include/configs/k2hk_evm.h                         |   2 +
 include/configs/ks2_evm.h                          |   4 +
 10 files changed, 275 insertions(+), 263 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-keystone/emac_defs.h
 create mode 100644 arch/arm/include/asm/ti-common/keystone_net.h
Signature · 1 line
1.8.3.2
author
#1 lore raw

PATCH v2 1/5 net: keystone_net: remove SoC specific emac_regs structure

From: Hao Zhang <[email protected]>

This patch removes K2HK SOC specifc emac_regs structure, it uses soc specific register offset to keep the network driver common across all the Keystone II EVMs.

Acked-by Murali Karicheri <[email protected]>
Signed-off-by Hao Zhang <[email protected]>
Signed-off-by Ivan Khoronzhuk <[email protected]>
---
 arch/arm/include/asm/arch-keystone/emac_defs.h | 15 ---------------
 drivers/net/keystone_net.c                     |  8 +++-----
 2 files changed, 3 insertions(+), 20 deletions(-)
arch/arm/include/asm/arch-keystone/emac_defs.h +0 -15
index 9cd8925..47e0ada 100644
@@ -202,21 +202,6 @@ struct mdio_regs {
 	dv_reg		userphysel1;
 };
 
-/* Ethernet MAC Registers Structure */
-struct emac_regs {
-	dv_reg		idver;
-	dv_reg		maccontrol;
-	dv_reg		macstatus;
-	dv_reg		soft_reset;
-	dv_reg		rx_maxlen;
-	u32		rsvd0;
-	dv_reg		rx_pause;
-	dv_reg		tx_pause;
-	dv_reg		emcontrol;
-	dv_reg		pri_map;
-	u32		rsvd1[6];
-};
-
 #define SGMII_ACCESS(port, reg) \
 	*((volatile unsigned int *)(sgmiis[port] + reg))
drivers/net/keystone_net.c +3 -5
index 66532ee..4abde57 100644
@@ -45,8 +45,6 @@ static void keystone2_eth_mdio_enable(void);
 static int gen_get_link_speed(int phy_addr);
 
 /* EMAC Addresses */
-static volatile struct emac_regs	*adap_emac =
-	(struct emac_regs *)EMAC_EMACSL_BASE_ADDR;
 static volatile struct mdio_regs	*adap_mdio =
 	(struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
 

@@ -169,10 +167,10 @@ static void  __attribute__((unused))
 	 * Check if link detected is giga-bit
 	 * If Gigabit mode detected, enable gigbit in MAC
 	 */
-	writel(readl(&(adap_emac[eth_priv->slave_port - 1].maccontrol)) |
+	writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
+		     CPGMACSL_REG_CTL) |
 	       EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
-	       &(adap_emac[eth_priv->slave_port - 1].maccontrol))
-		;
+	       DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
 }
 
 int keystone_sgmii_link_status(int port)
Signature · 1 line
1.8.3.2
#2 lore raw

PATCH v2 1/5 net: keystone_net: remove SoC specific emac_regs structure

Quoted 9 lines · Ivan

From: Hao Zhang <[email protected]>

This patch removes K2HK SOC specifc emac_regs structure, it uses soc specific register offset to keep the network driver common across all the Keystone II EVMs.

Acked-by Murali Karicheri <[email protected]>
Signed-off-by Hao Zhang <[email protected]>
Signed-off-by Ivan Khoronzhuk <[email protected]>

Applied to u-boot-ti/master, thanks!

Signature · 8 lines
Tom
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author
#3 lore raw

PATCH v2 2/5 net: keystone_net: add support for NETCP v1.5

In reply to Ivan Khoronzhuk

Currently the network driver is used only by k2hk evm board. The k2hk SoC contains NETCP v1.0, but Keystone2 SoCs, like k2e contain NETCP v1.5. So driver should be able to work with such kind of NETCP. This commit adds this opportunity. The main difference in masks and some registers, the logic is the same, so only definitions should be changed. To differentiate between versions add KS2_NETCP_V1_0 and KS2_NETCP_V1_5. Also remove unused and no more needed defines.

The port number is specific for each board so move this parameter to configuration.

Acked-by Murali Karicheri <[email protected]>
Signed-off-by Hao Zhang <[email protected]>
Signed-off-by Ivan Khoronzhuk <[email protected]>
---
 arch/arm/include/asm/arch-keystone/emac_defs.h     | 156 +++++++++++++--------
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h |   3 +
 include/configs/k2hk_evm.h                         |   1 +
 3 files changed, 98 insertions(+), 62 deletions(-)
arch/arm/include/asm/arch-keystone/emac_defs.h +94 -62
index 47e0ada..3450246 100644
@@ -13,20 +13,44 @@
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 
+/* EMAC */
+#ifdef KS2_NETCP_V1_0
+
 #define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00090900)
 #define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00090300)
 #define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00090100)
+#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x)*0x040)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL		0x04
+#define CPGMACSL_REG_STATUS		0x08
+#define CPGMACSL_REG_RESET		0x0c
+#define CPGMACSL_REG_MAXLEN		0x10
+
+#elif defined KS2_NETCP_V1_5
+
+#define CPGMACSL_REG_RX_PRI_MAP		0x020
+#define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00222000)
+#define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00200f00)
+#define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00200100)
+#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL		0x330
+#define CPGMACSL_REG_STATUS		0x334
+#define CPGMACSL_REG_RESET		0x338
+#define CPGMACSL_REG_MAXLEN		0x024
+
+#endif
 
 #define KEYSTONE2_EMAC_GIG_ENABLE
 
 #define MAC_ID_BASE_ADDR                (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
 
-#ifdef CONFIG_SOC_K2HK
 /* MDIO module input frequency */
 #define EMAC_MDIO_BUS_FREQ              (clk_get_rate(pass_pll_clk))
 /* MDIO clock output frequency */
 #define EMAC_MDIO_CLOCK_FREQ            1000000		/* 1.0 MHz */
-#endif
 
 /* MII Status Register */
 #define MII_STATUS_REG                  1

@@ -86,17 +110,8 @@ struct mac_sl_cfg {
 #define GMACSL_RET_WARN_MAXLEN_TOO_BIG      -3
 #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
 
-/* Register offsets */
-#define CPGMACSL_REG_ID         0x00
-#define CPGMACSL_REG_CTL        0x04
-#define CPGMACSL_REG_STATUS     0x08
-#define CPGMACSL_REG_RESET      0x0c
-#define CPGMACSL_REG_MAXLEN     0x10
-#define CPGMACSL_REG_BOFF       0x14
-#define CPGMACSL_REG_RX_PAUSE   0x18
-#define CPGMACSL_REG_TX_PAURSE  0x1c
-#define CPGMACSL_REG_EM_CTL     0x20
-#define CPGMACSL_REG_PRI        0x24
+/* EMAC SL register definitions */
+#define DEVICE_EMACSL_RESET_POLL_COUNT		  100
 
 /* Soft reset register values */
 #define CPGMAC_REG_RESET_VAL_RESET_MASK      (1 << 0)

@@ -105,6 +120,7 @@ struct mac_sl_cfg {
 /* Maxlen register values */
 #define CPGMAC_REG_MAXLEN_LEN                0x3fff
 
+/* CPSW */
 /* Control bitfields */
 #define CPSW_CTL_P2_PASS_PRI_TAGGED     (1 << 5)
 #define CPSW_CTL_P1_PASS_PRI_TAGGED     (1 << 4)

@@ -113,24 +129,39 @@ struct mac_sl_cfg {
 #define CPSW_CTL_VLAN_AWARE             (1 << 1)
 #define CPSW_CTL_FIFO_LOOPBACK          (1 << 0)
 
-#define DEVICE_CPSW_NUM_PORTS       5                    /* 5 switch ports */
-#define DEVICE_CPSW_BASE            (0x02090800)
-#define target_get_switch_ctl()     CPSW_CTL_P0_ENABLE   /* Enable port 0 */
-#define SWITCH_MAX_PKT_SIZE         9000
+#define DEVICE_CPSW_NUM_PORTS		CONFIG_KSNET_CPSW_NUM_PORTS
+#define DEVICE_N_GMACSL_PORTS		(DEVICE_CPSW_NUM_PORTS - 1)
+
+#ifdef KS2_NETCP_V1_0
+
+#define DEVICE_CPSW_BASE		(KS2_PASS_BASE + 0x00090800)
+#define CPSW_REG_CTL			0x004
+#define CPSW_REG_STAT_PORT_EN		0x00c
+#define CPSW_REG_MAXLEN			0x040
+#define CPSW_REG_ALE_CONTROL		0x608
+#define CPSW_REG_ALE_PORTCTL(x)		(0x640 + (x)*4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL     0xf
+
+#elif defined KS2_NETCP_V1_5
+
+#define DEVICE_CPSW_BASE		 (KS2_PASS_BASE + 0x00220000)
+#define CPSW_REG_CTL		         0x00004
+#define CPSW_REG_STAT_PORT_EN	         0x00014
+#define CPSW_REG_MAXLEN		         0x01024
+#define CPSW_REG_ALE_CONTROL	         0x1e008
+#define CPSW_REG_ALE_PORTCTL(x)		 (0x1e040 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL     0x1ff
+
+#endif
 
-/* Register offsets */
-#define CPSW_REG_CTL                0x004
-#define CPSW_REG_STAT_PORT_EN       0x00c
-#define CPSW_REG_MAXLEN             0x040
-#define CPSW_REG_ALE_CONTROL        0x608
-#define CPSW_REG_ALE_PORTCTL(x)     (0x640 + (x)*4)
-
-/* Register values */
-#define CPSW_REG_VAL_STAT_ENABLE_ALL             0xf
 #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE    ((u_int32_t)0xc0000000)
 #define CPSW_REG_VAL_ALE_CTL_BYPASS              ((u_int32_t)0x00000010)
 #define CPSW_REG_VAL_PORTCTL_FORWARD_MODE        0x3
 
+#define target_get_switch_ctl()     CPSW_CTL_P0_ENABLE   /* Enable port 0 */
+#define SWITCH_MAX_PKT_SIZE         9000
+
+/* SGMII */
 #define SGMII_REG_STATUS_LOCK           BIT(4)
 #define SGMII_REG_STATUS_LINK           BIT(0)
 #define SGMII_REG_STATUS_AUTONEG        BIT(2)

@@ -147,40 +178,46 @@ struct mac_sl_cfg {
 #define SGMII_LINK_MAC_FIBER            3
 #define SGMII_LINK_MAC_PHY_FORCED       4
 
-#define TARGET_SGMII_BASE              KS2_PASS_BASE + 0x00090100
-#define TARGET_SGMII_BASE_ADDRESSES    {KS2_PASS_BASE + 0x00090100, \
-					KS2_PASS_BASE + 0x00090200, \
-					KS2_PASS_BASE + 0x00090400, \
-					KS2_PASS_BASE + 0x00090500}
-
+#ifdef KS2_NETCP_V1_0
 #define SGMII_OFFSET(x)	((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
-
-/*
- * SGMII registers
- */
-#define SGMII_IDVER_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
-#define SGMII_SRESET_REG(x)   (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
-#define SGMII_CTL_REG(x)      (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
-#define SGMII_STATUS_REG(x)   (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
-#define SGMII_MRADV_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
-#define SGMII_LPADV_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
-#define SGMII_TXCFG_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
-#define SGMII_RXCFG_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
-#define SGMII_AUXCFG_REG(x)   (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
-
-#define DEVICE_EMACSL_BASE(x)      (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
-#define DEVICE_N_GMACSL_PORTS           4
-#define DEVICE_EMACSL_RESET_POLL_COUNT  100
-
-#define DEVICE_PSTREAM_CFG_REG_ADDR                 (KS2_PASS_BASE + 0x604)
-
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI      0x06060606
+#elif defined KS2_NETCP_V1_5
+#define SGMII_OFFSET(x)			((x) * 0x100)
 #endif
 
-#define hw_config_streaming_switch() \
-	writel(DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR);
+#define SGMII_IDVER_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
+
+/* PSS */
+#ifdef KS2_NETCP_V1_0
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR		(KS2_PASS_BASE + 0x604)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x06060606
+#define hw_config_streaming_switch()\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
+
+#elif defined KS2_NETCP_V1_5
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR		(KS2_PASS_BASE + 0x500)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x0
+
+#define hw_config_streaming_switch()\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+4);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+8);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+12);
+
+#endif
 
 /* EMAC MDIO Registers Structure */
 struct mdio_regs {

@@ -202,9 +239,6 @@ struct mdio_regs {
 	dv_reg		userphysel1;
 };
 
-#define SGMII_ACCESS(port, reg) \
-	*((volatile unsigned int *)(sgmiis[port] + reg))
-
 struct eth_priv_t {
 	char	int_name[32];
 	int	rx_flow;

@@ -213,8 +247,6 @@ struct eth_priv_t {
 	int	sgmii_link_type;
 };
 
-extern struct eth_priv_t eth_priv_cfg[];
-
 int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
 void sgmii_serdes_setup_156p25mhz(void);
 void sgmii_serdes_shutdown(void);
arch/arm/include/asm/arch-keystone/hardware-k2hk.h +3 -0
index 2db806c..6cfed3a 100644
@@ -95,4 +95,7 @@
 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
 #define KS2_NETCP_PDMA_TX_SND_QUEUE	648
 
+/* NETCP version */
+#define KS2_NETCP_V1_0
+
 #endif /* __ASM_ARCH_HARDWARE_H */
include/configs/k2hk_evm.h +1 -0
index d0c5ff1..15cebb9 100644
@@ -38,5 +38,6 @@
 #define CONFIG_DRIVER_TI_KEYSTONE_NET
 #define CONFIG_TI_KSNAV
 #define CONFIG_KSNAV_PKTDMA_NETCP
+#define CONFIG_KSNET_CPSW_NUM_PORTS	5
 
 #endif /* __CONFIG_K2HK_EVM_H */
Signature · 1 line
1.8.3.2
#4 lore raw

PATCH v2 2/5 net: keystone_net: add support for NETCP v1.5

Quoted 8 lines · Ivan

Currently the network driver is used only by k2hk evm board. The k2hk SoC contains NETCP v1.0, but Keystone2 SoCs, like k2e contain NETCP v1.5. So driver should be able to work with such kind of NETCP. This commit adds this opportunity. The main difference in masks and some registers, the logic is the same, so only definitions should be changed. To differentiate between versions add KS2_NETCP_V1_0 and KS2_NETCP_V1_5. Also remove unused and no more needed defines.

Quoted 6 lines

The port number is specific for each board so move this parameter to configuration.

Acked-by Murali Karicheri <[email protected]>
Signed-off-by Hao Zhang <[email protected]>
Signed-off-by Ivan Khoronzhuk <[email protected]>

Applied to u-boot-ti/master, thanks!

Signature · 8 lines
Tom
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author
#5 lore raw

PATCH v2 3/5 net: keystone_net: move header file from arch to ti-common

In reply to Ivan Khoronzhuk

The header file for the driver should be in correct place. So move it to "arch/arm/include/asm/ti-common/keystone_net.h" and correct driver's external dependencies. At the same time align and correct some definitions.

Acked-by Murali Karicheri <[email protected]>
Signed-off-by Ivan Khoronzhuk <[email protected]>
---
 arch/arm/include/asm/arch-keystone/emac_defs.h     | 254 ---------------------
 arch/arm/include/asm/arch-keystone/hardware-k2hk.h |   4 +-
 arch/arm/include/asm/arch-keystone/hardware.h      |   2 +
 arch/arm/include/asm/ti-common/keystone_net.h      | 248 ++++++++++++++++++++
 board/ti/ks2_evm/board.c                           |   2 +-
 board/ti/ks2_evm/board.h                           |   2 +-
 board/ti/ks2_evm/board_k2hk.c                      |   2 +-
 drivers/net/keystone_net.c                         |   2 +-
 include/configs/k2hk_evm.h                         |   1 +
 include/configs/ks2_evm.h                          |   4 +
 10 files changed, 261 insertions(+), 260 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-keystone/emac_defs.h
 create mode 100644 arch/arm/include/asm/ti-common/keystone_net.h
arch/arm/include/asm/arch-keystone/emac_defs.h deleted +0 -254
deleted file mode 100644
index 3450246..0000000
@@ -1,254 +0,0 @@
-/*
- * emac definitions for keystone2 devices
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _EMAC_DEFS_H_
-#define _EMAC_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/* EMAC */
-#ifdef KS2_NETCP_V1_0
-
-#define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00090900)
-#define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00090300)
-#define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00090100)
-#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x)*0x040)
-
-/* Register offsets */
-#define CPGMACSL_REG_CTL		0x04
-#define CPGMACSL_REG_STATUS		0x08
-#define CPGMACSL_REG_RESET		0x0c
-#define CPGMACSL_REG_MAXLEN		0x10
-
-#elif defined KS2_NETCP_V1_5
-
-#define CPGMACSL_REG_RX_PRI_MAP		0x020
-#define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00222000)
-#define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00200f00)
-#define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00200100)
-#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
-
-/* Register offsets */
-#define CPGMACSL_REG_CTL		0x330
-#define CPGMACSL_REG_STATUS		0x334
-#define CPGMACSL_REG_RESET		0x338
-#define CPGMACSL_REG_MAXLEN		0x024
-
-#endif
-
-#define KEYSTONE2_EMAC_GIG_ENABLE
-
-#define MAC_ID_BASE_ADDR                (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
-
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ              (clk_get_rate(pass_pll_clk))
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ            1000000		/* 1.0 MHz */
-
-/* MII Status Register */
-#define MII_STATUS_REG                  1
-#define MII_STATUS_LINK_MASK            (0x4)
-
-/* Marvell 88E1111 PHY ID */
-#define PHY_MARVELL_88E1111             (0x01410cc0)
-
-#define MDIO_CONTROL_IDLE               (0x80000000)
-#define MDIO_CONTROL_ENABLE             (0x40000000)
-#define MDIO_CONTROL_FAULT_ENABLE       (0x40000)
-#define MDIO_CONTROL_FAULT              (0x80000)
-#define MDIO_USERACCESS0_GO             (0x80000000)
-#define MDIO_USERACCESS0_WRITE_READ     (0x0)
-#define MDIO_USERACCESS0_WRITE_WRITE    (0x40000000)
-#define MDIO_USERACCESS0_ACK            (0x20000000)
-
-#define EMAC_MACCONTROL_MIIEN_ENABLE       (0x20)
-#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE  (0x1)
-#define EMAC_MACCONTROL_GIGABIT_ENABLE     (1 << 7)
-#define EMAC_MACCONTROL_GIGFORCE           (1 << 17)
-#define EMAC_MACCONTROL_RMIISPEED_100      (1 << 15)
-
-#define EMAC_MIN_ETHERNET_PKT_SIZE         60
-
-struct mac_sl_cfg {
-	u_int32_t max_rx_len;	/* Maximum receive packet length. */
-	u_int32_t ctl;		/* Control bitfield */
-};
-
-/*
- * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
- */
-#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES       (1 << 24)
-#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES         (1 << 23)
-#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES         (1 << 22)
-#define GMACSL_RX_ENABLE_EXT_CTL                  (1 << 18)
-#define GMACSL_RX_ENABLE_GIG_FORCE                (1 << 17)
-#define GMACSL_RX_ENABLE_IFCTL_B                  (1 << 16)
-#define GMACSL_RX_ENABLE_IFCTL_A                  (1 << 15)
-#define GMACSL_RX_ENABLE_CMD_IDLE                 (1 << 11)
-#define GMACSL_TX_ENABLE_SHORT_GAP                (1 << 10)
-#define GMACSL_ENABLE_GIG_MODE                    (1 <<  7)
-#define GMACSL_TX_ENABLE_PACE                     (1 <<  6)
-#define GMACSL_ENABLE                             (1 <<  5)
-#define GMACSL_TX_ENABLE_FLOW_CTL                 (1 <<  4)
-#define GMACSL_RX_ENABLE_FLOW_CTL                 (1 <<  3)
-#define GMACSL_ENABLE_LOOPBACK                    (1 <<  1)
-#define GMACSL_ENABLE_FULL_DUPLEX                 (1 <<  0)
-
-/*
- * DEFINTITION: function return values
- */
-#define GMACSL_RET_OK                        0
-#define GMACSL_RET_INVALID_PORT             -1
-#define GMACSL_RET_WARN_RESET_INCOMPLETE    -2
-#define GMACSL_RET_WARN_MAXLEN_TOO_BIG      -3
-#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
-
-/* EMAC SL register definitions */
-#define DEVICE_EMACSL_RESET_POLL_COUNT		  100
-
-/* Soft reset register values */
-#define CPGMAC_REG_RESET_VAL_RESET_MASK      (1 << 0)
-#define CPGMAC_REG_RESET_VAL_RESET           (1 << 0)
-
-/* Maxlen register values */
-#define CPGMAC_REG_MAXLEN_LEN                0x3fff
-
-/* CPSW */
-/* Control bitfields */
-#define CPSW_CTL_P2_PASS_PRI_TAGGED     (1 << 5)
-#define CPSW_CTL_P1_PASS_PRI_TAGGED     (1 << 4)
-#define CPSW_CTL_P0_PASS_PRI_TAGGED     (1 << 3)
-#define CPSW_CTL_P0_ENABLE              (1 << 2)
-#define CPSW_CTL_VLAN_AWARE             (1 << 1)
-#define CPSW_CTL_FIFO_LOOPBACK          (1 << 0)
-
-#define DEVICE_CPSW_NUM_PORTS		CONFIG_KSNET_CPSW_NUM_PORTS
-#define DEVICE_N_GMACSL_PORTS		(DEVICE_CPSW_NUM_PORTS - 1)
-
-#ifdef KS2_NETCP_V1_0
-
-#define DEVICE_CPSW_BASE		(KS2_PASS_BASE + 0x00090800)
-#define CPSW_REG_CTL			0x004
-#define CPSW_REG_STAT_PORT_EN		0x00c
-#define CPSW_REG_MAXLEN			0x040
-#define CPSW_REG_ALE_CONTROL		0x608
-#define CPSW_REG_ALE_PORTCTL(x)		(0x640 + (x)*4)
-#define CPSW_REG_VAL_STAT_ENABLE_ALL     0xf
-
-#elif defined KS2_NETCP_V1_5
-
-#define DEVICE_CPSW_BASE		 (KS2_PASS_BASE + 0x00220000)
-#define CPSW_REG_CTL		         0x00004
-#define CPSW_REG_STAT_PORT_EN	         0x00014
-#define CPSW_REG_MAXLEN		         0x01024
-#define CPSW_REG_ALE_CONTROL	         0x1e008
-#define CPSW_REG_ALE_PORTCTL(x)		 (0x1e040 + (x) * 4)
-#define CPSW_REG_VAL_STAT_ENABLE_ALL     0x1ff
-
-#endif
-
-#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE    ((u_int32_t)0xc0000000)
-#define CPSW_REG_VAL_ALE_CTL_BYPASS              ((u_int32_t)0x00000010)
-#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE        0x3
-
-#define target_get_switch_ctl()     CPSW_CTL_P0_ENABLE   /* Enable port 0 */
-#define SWITCH_MAX_PKT_SIZE         9000
-
-/* SGMII */
-#define SGMII_REG_STATUS_LOCK           BIT(4)
-#define SGMII_REG_STATUS_LINK           BIT(0)
-#define SGMII_REG_STATUS_AUTONEG        BIT(2)
-#define SGMII_REG_CONTROL_AUTONEG       BIT(0)
-#define SGMII_REG_CONTROL_MASTER        BIT(5)
-#define	SGMII_REG_MR_ADV_ENABLE         BIT(0)
-#define	SGMII_REG_MR_ADV_LINK           BIT(15)
-#define	SGMII_REG_MR_ADV_FULL_DUPLEX    BIT(12)
-#define SGMII_REG_MR_ADV_GIG_MODE       BIT(11)
-
-#define SGMII_LINK_MAC_MAC_AUTONEG      0
-#define SGMII_LINK_MAC_PHY              1
-#define SGMII_LINK_MAC_MAC_FORCED       2
-#define SGMII_LINK_MAC_FIBER            3
-#define SGMII_LINK_MAC_PHY_FORCED       4
-
-#ifdef KS2_NETCP_V1_0
-#define SGMII_OFFSET(x)	((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
-#elif defined KS2_NETCP_V1_5
-#define SGMII_OFFSET(x)			((x) * 0x100)
-#endif
-
-#define SGMII_IDVER_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
-#define SGMII_SRESET_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
-#define SGMII_CTL_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
-#define SGMII_STATUS_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
-#define SGMII_MRADV_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
-#define SGMII_LPADV_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
-#define SGMII_TXCFG_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
-#define SGMII_RXCFG_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
-#define SGMII_AUXCFG_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
-
-/* PSS */
-#ifdef KS2_NETCP_V1_0
-
-#define DEVICE_PSTREAM_CFG_REG_ADDR		(KS2_PASS_BASE + 0x604)
-#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x06060606
-#define hw_config_streaming_switch()\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
-
-#elif defined KS2_NETCP_V1_5
-
-#define DEVICE_PSTREAM_CFG_REG_ADDR		(KS2_PASS_BASE + 0x500)
-#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x0
-
-#define hw_config_streaming_switch()\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR);\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR+4);\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR+8);\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR+12);
-
-#endif
-
-/* EMAC MDIO Registers Structure */
-struct mdio_regs {
-	dv_reg		version;
-	dv_reg		control;
-	dv_reg		alive;
-	dv_reg		link;
-	dv_reg		linkintraw;
-	dv_reg		linkintmasked;
-	u_int8_t	rsvd0[8];
-	dv_reg		userintraw;
-	dv_reg		userintmasked;
-	dv_reg		userintmaskset;
-	dv_reg		userintmaskclear;
-	u_int8_t	rsvd1[80];
-	dv_reg		useraccess0;
-	dv_reg		userphysel0;
-	dv_reg		useraccess1;
-	dv_reg		userphysel1;
-};
-
-struct eth_priv_t {
-	char	int_name[32];
-	int	rx_flow;
-	int	phy_addr;
-	int	slave_port;
-	int	sgmii_link_type;
-};
-
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
-void sgmii_serdes_setup_156p25mhz(void);
-void sgmii_serdes_shutdown(void);
-
-#endif  /* _EMAC_DEFS_H_ */
arch/arm/include/asm/arch-keystone/hardware-k2hk.h +2 -2
index 6cfed3a..706b21d 100644
@@ -95,7 +95,7 @@
 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
 #define KS2_NETCP_PDMA_TX_SND_QUEUE	648
 
-/* NETCP version */
-#define KS2_NETCP_V1_0
+/* NETCP */
+#define KS2_NETCP_BASE			0x02000000
 
 #endif /* __ASM_ARCH_HARDWARE_H */
arch/arm/include/asm/arch-keystone/hardware.h +2 -0
index 29f7bf1..b297671 100644
@@ -171,6 +171,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DEV_USB_PHY_BASE		0x02620738
 #define KS2_USB_PHY_CFG_BASE		0x02630000
 
+#define KS2_MAC_ID_BASE_ADDR		(KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif
arch/arm/include/asm/ti-common/keystone_net.h new file +248 -0

248 lines not on this page · raw message

board/ti/ks2_evm/board.c +1 -1
index dfe7be6..f9d5f90 100644
@@ -12,8 +12,8 @@
 #include <exports.h>
 #include <fdt_support.h>
 #include <asm/arch/ddr3.h>
-#include <asm/arch/emac_defs.h>
 #include <asm/ti-common/ti-aemif.h>
+#include <asm/ti-common/keystone_net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
board/ti/ks2_evm/board.h +1 -1
index d91ef73..e476c06 100644
@@ -10,7 +10,7 @@
 #ifndef _KS2_BOARD
 #define _KS2_BOARD
 
-#include <asm/arch/emac_defs.h>
+#include <asm/ti-common/keystone_net.h>
 
 extern struct eth_priv_t eth_priv_cfg[];
board/ti/ks2_evm/board_k2hk.c +1 -1
index 6fb3d21..d82654f 100644
@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/emac_defs.h>
+#include <asm/ti-common/keystone_net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
drivers/net/keystone_net.c +1 -1
index 4abde57..edd2bb0 100644
@@ -12,9 +12,9 @@
 #include <net.h>
 #include <miiphy.h>
 #include <malloc.h>
-#include <asm/arch/emac_defs.h>
 #include <asm/arch/psc_defs.h>
 #include <asm/ti-common/keystone_nav.h>
+#include <asm/ti-common/keystone_net.h>
 
 unsigned int emac_dbg;
include/configs/k2hk_evm.h +1 -0
index 15cebb9..45bd72d 100644
@@ -38,6 +38,7 @@
 #define CONFIG_DRIVER_TI_KEYSTONE_NET
 #define CONFIG_TI_KSNAV
 #define CONFIG_KSNAV_PKTDMA_NETCP
+#define CONFIG_KSNET_NETCP_V1_0
 #define CONFIG_KSNET_CPSW_NUM_PORTS	5
 
 #endif /* __CONFIG_K2HK_EVM_H */
include/configs/ks2_evm.h +4 -0
index 639f119..a7d7937 100644
@@ -135,6 +135,10 @@
 #define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE	KS2_NETCP_PDMA_RX_RCV_QUEUE
 #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE
 
+/* Keystone net */
+#define CONFIG_KSNET_MAC_ID_BASE	KS2_MAC_ID_BASE_ADDR
+#define CONFIG_KSNET_NETCP_BASE		KS2_NETCP_BASE
+
 /* AEMIF */
 #define CONFIG_TI_AEMIF
 #define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE
Signature · 1 line
1.8.3.2
#6 lore raw

PATCH v2 3/5 net: keystone_net: move header file from arch to ti-common

Quoted 7 lines · Ivan

The header file for the driver should be in correct place. So move it to "arch/arm/include/asm/ti-common/keystone_net.h" and correct driver's external dependencies. At the same time align and correct some definitions.

Acked-by Murali Karicheri <[email protected]>
Signed-off-by Ivan Khoronzhuk <[email protected]>

Applied to u-boot-ti/master, thanks!

Signature · 8 lines
Tom
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#7 lore raw

PATCH v2 4/5 net: keystone_net: increase MDIO clock frequency

In reply to Ivan Khoronzhuk

From: Vitaly Andrianov <[email protected]>

With MAC_PHY sgmii configuration, u-boot checks PHY link status before sending each packet. Increasing MDIO frequency increases overall tftp speed. We set it to maximum 2.5MHz.

Acked-by Murali Karicheri <[email protected]>
Signed-off-by Vitaly Andrianov <[email protected]>
Signed-off-by Ivan Khoronzhuk <[email protected]>
---
 arch/arm/include/asm/ti-common/keystone_net.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/include/asm/ti-common/keystone_net.h +1 -1
index 7769d7b..e56759d 100644
@@ -51,7 +51,7 @@
 /* MDIO module input frequency */
 #define EMAC_MDIO_BUS_FREQ		(clk_get_rate(pass_pll_clk))
 /* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		1000000                /* 1.0 MHz */
+#define EMAC_MDIO_CLOCK_FREQ		2500000	/* 2.5 MHz */
 
 /* MII Status Register */
 #define MII_STATUS_REG			1
Signature · 1 line
1.8.3.2
#8 lore raw

PATCH v2 4/5 net: keystone_net: increase MDIO clock frequency

Quoted 9 lines · Ivan

From: Vitaly Andrianov <[email protected]>

With MAC_PHY sgmii configuration, u-boot checks PHY link status before sending each packet. Increasing MDIO frequency increases overall tftp speed. We set it to maximum 2.5MHz.

Acked-by Murali Karicheri <[email protected]>
Signed-off-by Vitaly Andrianov <[email protected]>
Signed-off-by Ivan Khoronzhuk <[email protected]>

Applied to u-boot-ti/master, thanks!

Signature · 8 lines
Tom
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author
#9 lore raw

PATCH v2 5/5 net: keystone_net: remove redundant code from keystone_net.c

In reply to Ivan Khoronzhuk

Remove unused tx_send_loop variable.

Removes duplicated get_link_status() call from the keystone2_eth_send_packet().

The emac_gigabit_enable() is called at opening Ethernet and there is no need to enable it on sending each packet. So remove that call from keystone2_eth_send_packet() as well.

The calling of power/clock up functions are mostly the responsibility of SoC/board code, so move these functions to appropriate place.

Signed-off-by Ivan Khoronzhuk <[email protected]>
---
 board/ti/ks2_evm/board.c   |  9 +++++++++
 drivers/net/keystone_net.c | 17 -----------------
 2 files changed, 9 insertions(+), 17 deletions(-)
board/ti/ks2_evm/board.c +9 -0
index f9d5f90..cdfca23 100644
@@ -12,6 +12,7 @@
 #include <exports.h>
 #include <fdt_support.h>
 #include <asm/arch/ddr3.h>
+#include <asm/arch/psc_defs.h>
 #include <asm/ti-common/ti-aemif.h>
 #include <asm/ti-common/keystone_net.h>
 

@@ -68,6 +69,14 @@ int board_eth_init(bd_t *bis)
 	int port_num;
 	char link_type_name[32];
 
+	/* By default, select PA PLL clock as PA clock source */
+	if (psc_enable_module(KS2_LPSC_PA))
+		return -1;
+	if (psc_enable_module(KS2_LPSC_CPGMAC))
+		return -1;
+	if (psc_enable_module(KS2_LPSC_CRYPTO))
+		return -1;
+
 	port_num = get_num_eth_ports();
 
 	for (j = 0; j < port_num; j++) {
drivers/net/keystone_net.c +0 -17
index edd2bb0..33197f9 100644
@@ -12,12 +12,9 @@
 #include <net.h>
 #include <miiphy.h>
 #include <malloc.h>
-#include <asm/arch/psc_defs.h>
 #include <asm/ti-common/keystone_nav.h>
 #include <asm/ti-common/keystone_net.h>
 
-unsigned int emac_dbg;
-
 unsigned int emac_open;
 static unsigned int sys_has_mdio = 1;
 

@@ -409,9 +406,6 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 	sys_has_mdio =
 		(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
 
-	psc_enable_module(KS2_LPSC_PA);
-	psc_enable_module(KS2_LPSC_CPGMAC);
-
 	sgmii_serdes_setup_156p25mhz();
 
 	if (sys_has_mdio)

@@ -490,8 +484,6 @@ void keystone2_eth_close(struct eth_device *dev)
 	debug("- emac_close\n");
 }
 
-static int tx_send_loop;
-
 /*
  * This function sends a single packet on the network and returns
  * positive number (number of bytes transmitted) or negative for error

@@ -502,21 +494,12 @@ static int keystone2_eth_send_packet(struct eth_device *dev,
 	int ret_status = -1;
 	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 
-	tx_send_loop = 0;
-
 	if (keystone_get_link_status(dev) == 0)
 		return -1;
 
-	emac_gigabit_enable(dev);
-
 	if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
 		return ret_status;
 
-	if (keystone_get_link_status(dev) == 0)
-		return -1;
-
-	emac_gigabit_enable(dev);
-
 	return length;
 }
Signature · 1 line
1.8.3.2
#10 lore raw

PATCH v2 5/5 net: keystone_net: remove redundant code from keystone_net.c

Quoted 5 lines · Ivan

Remove unused tx_send_loop variable.

Removes duplicated get_link_status() call from the keystone2_eth_send_packet().

Quoted 8 lines

The emac_gigabit_enable() is called at opening Ethernet and there is no need to enable it on sending each packet. So remove that call from keystone2_eth_send_packet() as well.

The calling of power/clock up functions are mostly the responsibility of SoC/board code, so move these functions to appropriate place.

Signed-off-by Ivan Khoronzhuk <[email protected]>

Applied to u-boot-ti/master, thanks!

Signature · 8 lines
Tom
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