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arm: socfpga: Add example config entry for EPCS/EPCQ SPI

PATCH New Marek Vasut 4 participants 10 messages Oct 30, 2014 – Oct 31, 2014

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Marek Vasut

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#0 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
---
 include/configs/socfpga_common.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
include/configs/socfpga_common.h +19 -0
index 83a1bcd..1df886b 100644
@@ -79,6 +79,25 @@
 #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 
 /*
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
+ * The base address is configurable in QSys, each board must specify the
+ * base address based on it's particular FPGA configuration. Please note
+ * that the address here is incremented by  0x400  from the Base address
+ * selected in QSys, since the SPI registers are at offset +0x400.
+ * #define CONFIG_SYS_SPI_BASE		0xff240400
+ */
+#endif
+
+/*
  * Ethernet on SoC (EMAC)
  */
 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
Signature · 1 line
2.0.0
#1 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

Quoted 8 lines · Marek Vasut

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Acked-by Pavel Machek <[email protected]>
Quoted 9 lines
include/configs/socfpga_common.h +3 -0
@@ -79,6 +79,25 @@
 #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 
 /*
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI

include/configs/socfpga_common.h line 94

Quoted 10 lines
include/configs/socfpga_common.h +10 -0
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
+ * The base address is configurable in QSys, each board must specify the
+ * base address based on it's particular FPGA configuration. Please note
+ * that the address here is incremented by  0x400  from the Base address

Are the double spaces around 0x400 intentional?

Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#2 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

Quoted 20 lines · Pavel Machek
Quoted 8 lines · Marek Vasut

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Acked-by Pavel Machek <[email protected]>
Quoted 8 lines
include/configs/socfpga_common.h +0 -0
@@ -79,6 +79,25 @@
 
 #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 
 /*
Quoted 15 lines

include/configs/socfpga_common.h line 94

Quoted 13 lines
include/configs/socfpga_common.h +13 -0
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
+ * The base address is configurable in QSys, each board must specify the
+ * base address based on it's particular FPGA configuration. Please note
+ * that the address here is incremented by  0x400  from the Base address

Are the double spaces around 0x400 intentional?

Yes, to stress it out and align the text to a nice block ;-)

Best regards,
Marek Vasut

#3 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

In reply to Marek Vasut
Quoted 10 lines · Marek Vasut

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

#4 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

In reply to Marek Vasut
Quoted 27 lines · Marek Vasut

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>
---
 include/configs/socfpga_common.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
include/configs/socfpga_common.h +5 -0
index 83a1bcd..1df886b 100644
@@ -79,6 +79,25 @@
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
 /*
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF

include/configs/socfpga_common.h line 96

Quoted 10 lines
include/configs/socfpga_common.h +10 -0
+#define CONFIG_SF_DEFAULT_SPEED                30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
+ * The base address is configurable in QSys, each board must specify the
+ * base address based on it's particular FPGA configuration. Please note
+ * that the address here is incremented by  0x400  from the Base address
+ * selected in QSys, since the SPI registers are at offset +0x400.
+ * #define CONFIG_SYS_SPI_BASE         0xff240400

So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI

Quoted 9 lines
include/configs/socfpga_common.h +4 -1
+ */
+#endif
+
+/*
  * Ethernet on SoC (EMAC)
  */
 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
--

2.0.0

thanks!

Signature · 1 line
Jagan.
author
#5 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

Quoted 36 lines · Jagan Teki
Quoted 35 lines · Marek Vasut

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>

---

 include/configs/socfpga_common.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
(quoted diff) +0 -0

b/include/configs/socfpga_common.h index 83a1bcd..1df886b 100644

include/configs/socfpga_common.h +10 -0
@@ -79,6 +79,25 @@
 
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
 /*
 
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED                30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
Quoted 8 lines

include/configs/socfpga_common.h line 96

Quoted 5 lines
include/configs/socfpga_common.h +5 -0
+ * The base address is configurable in QSys, each board must specify the
+ * base address based on it's particular FPGA configuration. Please note
+ * that the address here is incremented by  0x400  from the Base address
+ * selected in QSys, since the SPI registers are at offset +0x400.
+ * #define CONFIG_SYS_SPI_BASE         0xff240400

So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI

Yes, the address is not fixed, since this is FPGA IP.

Best regards,
Marek Vasut

#6 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

Quoted 46 lines · Marek Vasut
Quoted 36 lines · Jagan Teki
Quoted 35 lines · Marek Vasut

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>

---

 include/configs/socfpga_common.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
(quoted diff) +0 -0

b/include/configs/socfpga_common.h index 83a1bcd..1df886b 100644

include/configs/socfpga_common.h +10 -0
@@ -79,6 +79,25 @@
 
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
 /*
 
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED                30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
Quoted 8 lines

include/configs/socfpga_common.h line 96

Quoted 5 lines
include/configs/socfpga_common.h +5 -0
+ * The base address is configurable in QSys, each board must specify the
+ * base address based on it's particular FPGA configuration. Please note
+ * that the address here is incremented by  0x400  from the Base address
+ * selected in QSys, since the SPI registers are at offset +0x400.
+ * #define CONFIG_SYS_SPI_BASE         0xff240400

So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI

Quoted 1 line

Yes, the address is not fixed, since this is FPGA IP.

May be use conditional ifdef with CONFIG_SYS_SPI_BASE instead of CONFIG_ALTERA_SPI
so who ever use SPI on their board will define CONFIG_SYS_SPI_BASE config.

thanks!

Signature · 1 line
Jagan.
author
#7 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

Quoted 47 lines · Jagan Teki
Quoted 46 lines · Marek Vasut
Quoted 44 lines · Jagan Teki
Quoted 36 lines · Marek Vasut

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>

---

 include/configs/socfpga_common.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
(quoted diff) +0 -0

b/include/configs/socfpga_common.h index 83a1bcd..1df886b 100644

include/configs/socfpga_common.h +11 -0
@@ -79,6 +79,25 @@
 
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
 /*
 
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED                30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
+ * The base address is configurable in QSys, each board must specify
Quoted 4 lines

the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at
offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400

So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI

Quoted 5 lines
Quoted 1 line

Yes, the address is not fixed, since this is FPGA IP.

May be use conditional ifdef with CONFIG_SYS_SPI_BASE instead of CONFIG_ALTERA_SPI
so who ever use SPI on their board will define CONFIG_SYS_SPI_BASE config.

You can have different SPI controllers enabled on the SoCFPGA, so enabling CONFIG_ALTERA_SPI explicitly in case CONFIG_SYS_SPI_BASE is defined is a very bad idea.

Best regards,
Marek Vasut

#8 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

Quoted 50 lines · Marek Vasut
Quoted 49 lines · Jagan Teki
Quoted 47 lines · Marek Vasut
Quoted 36 lines · Jagan Teki
Quoted 35 lines · Marek Vasut

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>

---

 include/configs/socfpga_common.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
(quoted diff) +0 -0

b/include/configs/socfpga_common.h index 83a1bcd..1df886b 100644

include/configs/socfpga_common.h +10 -0
@@ -79,6 +79,25 @@
 
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
 /*
 
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED                30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
Quoted 8 lines
Quoted 5 lines
include/configs/socfpga_common.h +1 -0
+ * The base address is configurable in QSys, each board must specify

the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at
offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400

So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI

Yes, the address is not fixed, since this is FPGA IP.

Quoted 7 lines
Quoted 3 lines

May be use conditional ifdef with CONFIG_SYS_SPI_BASE instead of CONFIG_ALTERA_SPI
so who ever use SPI on their board will define CONFIG_SYS_SPI_BASE config.

You can have different SPI controllers enabled on the SoCFPGA, so enabling CONFIG_ALTERA_SPI explicitly in case CONFIG_SYS_SPI_BASE is defined is a very bad idea.

In that case - It's true.

Reviewed-by Jagannadha Sutradharudu Teki <[email protected]>

thanks!

Signature · 1 line
Jagan.
author
#9 lore raw

PATCH 1/1 arm: socfpga: Add example config entry for EPCS/EPCQ SPI

Quoted 57 lines · Jagan Teki
Quoted 56 lines · Marek Vasut
Quoted 54 lines · Jagan Teki
Quoted 47 lines · Marek Vasut
Quoted 37 lines · Jagan Teki
Quoted 36 lines · Marek Vasut

Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Stefan Roese <[email protected]>

---

 include/configs/socfpga_common.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
(quoted diff) +0 -0

b/include/configs/socfpga_common.h index 83a1bcd..1df886b 100644

include/configs/socfpga_common.h +11 -0
@@ -79,6 +79,25 @@
 
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
 /*
 
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED                30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
+ * The base address is configurable in QSys, each board must
Quoted 8 lines
Quoted 5 lines

specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define
CONFIG_SYS_SPI_BASE 0xff240400

So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI

Quoted 1 line

Yes, the address is not fixed, since this is FPGA IP.

May be use conditional ifdef with CONFIG_SYS_SPI_BASE instead of CONFIG_ALTERA_SPI
so who ever use SPI on their board will define CONFIG_SYS_SPI_BASE config.

Quoted 7 lines
Quoted 3 lines

You can have different SPI controllers enabled on the SoCFPGA, so enabling CONFIG_ALTERA_SPI explicitly in case CONFIG_SYS_SPI_BASE is defined is a very bad idea.

In that case - It's true.

Reviewed-by Jagannadha Sutradharudu Teki <[email protected]>

Applied to u-boot-socfpga, thanks.

Best regards,
Marek Vasut