Add support for CompuLab cm-t3517 SoM

index 2ce682f..c297fd8 100644
@@ -18,6 +18,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <power/tps65910.h>
+#include <linux/compiler.h>
 
 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
 

@@ -53,7 +54,7 @@ u32 get_cpu_type(void)
  * get_board_rev() - setup to pass kernel board revision information
  * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
  */
-u32 get_board_rev(void)
+u32 __weak get_board_rev(void)
 {
 	return BOARD_REV_ID;
 }

index 2ce682f..781d83f 100644
@@ -18,6 +18,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <power/tps65910.h>
+#include <linux/compiler.h>
 
 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
 

@@ -51,11 +52,11 @@ u32 get_cpu_type(void)
 
 /**
  * get_board_rev() - setup to pass kernel board revision information
- * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ * returns: 0 for the ATAG REVISION tag value.
  */
-u32 get_board_rev(void)
+u32 __weak get_board_rev(void)
 {
-	return BOARD_REV_ID;
+	return 0;
 }
 
 /**

index 33a82fc..7eacf27 100644
@@ -14,8 +14,6 @@
 #include <asm/ti-common/sys_proto.h>
 #include <asm/arch/cpu.h>
 
-#define BOARD_REV_ID	0x0
-
 u32 get_cpu_rev(void);
 u32 get_sysboot_value(void);
 

index d0b0930..5453942 100644
@@ -33,6 +33,7 @@
 #include <asm/ehci-omap.h>
 #include <asm/gpio.h>
 
+#include "../common/common.h"
 #include "../common/eeprom.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -154,34 +155,18 @@ int board_init(void)
 	return 0;
 }
 
-static u32 cm_t3x_rev;
-
 /*
  * Routine: get_board_rev
  * Description: read system revision
  */
 u32 get_board_rev(void)
 {
-	if (!cm_t3x_rev)
-		cm_t3x_rev = cl_eeprom_get_board_rev();
-
-	return cm_t3x_rev;
+	return cl_eeprom_get_board_rev();
 };
 
-/*
- * Routine: misc_init_r
- * Description: display die ID
- */
 int misc_init_r(void)
 {
-	u32 board_rev = get_board_rev();
-	u32 rev_major = board_rev / 100;
-	u32 rev_minor = board_rev - (rev_major * 100);
-
-	if ((rev_minor / 10) * 10 == rev_minor)
-		rev_minor = rev_minor / 10;
-
-	printf("PCB:   %u.%u\n", rev_major, rev_minor);
+	cl_print_pcb_info();
 	dieid_num_r();
 
 	return 0;

new file mode 100644
index 0000000..6d2d7b0
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bootm.h>
+
+#include "common.h"
+#include "eeprom.h"
+
+void cl_print_pcb_info(void)
+{
+	u32 board_rev = get_board_rev();
+	u32 rev_major = board_rev / 100;
+	u32 rev_minor = board_rev - (rev_major * 100);
+
+	if ((rev_minor / 10) * 10 == rev_minor)
+		rev_minor = rev_minor / 10;
+
+	printf("PCB:   %u.%u\n", rev_major, rev_minor);
+}

new file mode 100644
index 0000000..316ee4c
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CL_COMMON_
+#define _CL_COMMON_
+
+void cl_print_pcb_info(void);
+
+#endif /* _CL_COMMON_ */

index 2df3ada..a45e7be 100644
@@ -109,23 +109,27 @@ int cl_eeprom_read_mac_addr(uchar *buf)
 	return cl_eeprom_read(offset, buf, 6);
 }
 
+static u32 board_rev;
+
 /*
  * Routine: cl_eeprom_get_board_rev
  * Description: read system revision from eeprom
  */
 u32 cl_eeprom_get_board_rev(void)
 {
-	u32 rev = 0;
 	char str[5]; /* Legacy representation can contain at most 4 digits */
 	uint offset = BOARD_REV_OFFSET_LEGACY;
 
+	if (board_rev)
+		return board_rev;
+
 	if (cl_eeprom_setup_layout())
 		return 0;
 
 	if (cl_eeprom_layout != LAYOUT_LEGACY)
 		offset = BOARD_REV_OFFSET;
 
-	if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
+	if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE))
 		return 0;
 
 	/*

@@ -133,9 +137,9 @@ u32 cl_eeprom_get_board_rev(void)
 	 * representation. i.e. for rev 1.00: 0x100 --> 0x64
 	 */
 	if (cl_eeprom_layout == LAYOUT_LEGACY) {
-		sprintf(str, "%x", rev);
-		rev = simple_strtoul(str, NULL, 10);
+		sprintf(str, "%x", board_rev);
+		board_rev = simple_strtoul(str, NULL, 10);
 	}
 
-	return rev;
+	return board_rev;
 };

index 5453942..aca41c8 100644
@@ -568,21 +568,12 @@ struct omap_usbhs_board_data usbhs_bdata = {
 
 #define SB_T35_USB_HUB_RESET_GPIO	167
 int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+		  struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	u8 val;
 	int offset;
 
-	if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
-		printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
-				SB_T35_USB_HUB_RESET_GPIO);
-		return -1;
-	}
-
-	gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
-	udelay(10);
-	gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
-	udelay(1000);
+	cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
 
 	offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
 	twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);

@@ -599,6 +590,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 int ehci_hcd_stop(void)
 {
+	cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
 	return omap_ehci_hcd_stop();
 }
 #endif /* CONFIG_USB_EHCI_OMAP */

index 6d2d7b0..f2ce522 100644
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <asm/bootm.h>
+#include <asm/gpio.h>
 
 #include "common.h"
 #include "eeprom.h"

@@ -23,3 +24,24 @@ void cl_print_pcb_info(void)
 
 	printf("PCB:   %u.%u\n", rev_major, rev_minor);
 }
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label)
+{
+	if (gpio_request(gpio, label)) {
+		printf("Error: can't obtain GPIO%d for %s", gpio, label);
+		return -1;
+	}
+
+	gpio_direction_output(gpio, 0);
+	udelay(10);
+	gpio_set_value(gpio, 1);
+	udelay(1000);
+	return 0;
+}
+
+void cl_usb_hub_deinit(int gpio)
+{
+	gpio_free(gpio);
+}
+#endif

index 316ee4c..ffe1ef8 100644
@@ -9,6 +9,19 @@
 #ifndef _CL_COMMON_
 #define _CL_COMMON_
 
+#include <asm/errno.h>
+
 void cl_print_pcb_info(void);
 
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label);
+void cl_usb_hub_deinit(int gpio);
+#else /* !CONFIG_CMD_USB */
+static inline int cl_usb_hub_init(int gpio, const char *label)
+{
+	return -ENOSYS;
+}
+static inline void cl_usb_hub_deinit(int gpio) {}
+#endif /* CONFIG_CMD_USB */
+
 #endif /* _CL_COMMON_ */

index aca41c8..a3b38ae 100644
@@ -19,9 +19,7 @@
 #include <i2c.h>
 #include <usb.h>
 #include <mmc.h>
-#include <nand.h>
 #include <twl4030.h>
-#include <bmp_layout.h>
 #include <linux/compiler.h>
 
 #include <asm/io.h>

@@ -54,48 +52,6 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
 	0
 };
 
-#ifdef CONFIG_LCD
-#ifdef CONFIG_CMD_NAND
-static int splash_load_from_nand(u32 bmp_load_addr)
-{
-	struct bmp_header *bmp_hdr;
-	int res, splash_screen_nand_offset = 0x100000;
-	size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
-
-	if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
-		goto splash_address_too_high;
-
-	res = nand_read_skip_bad(&nand_info[nand_curr_device],
-			splash_screen_nand_offset, &bmp_header_size,
-			NULL, nand_info[nand_curr_device].size,
-			(u_char *)bmp_load_addr);
-	if (res < 0)
-		return res;
-
-	bmp_hdr = (struct bmp_header *)bmp_load_addr;
-	bmp_size = le32_to_cpu(bmp_hdr->file_size);
-
-	if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
-		goto splash_address_too_high;
-
-	return nand_read_skip_bad(&nand_info[nand_curr_device],
-			splash_screen_nand_offset, &bmp_size,
-			NULL, nand_info[nand_curr_device].size,
-			(u_char *)bmp_load_addr);
-
-splash_address_too_high:
-	printf("Error: splashimage address too high. Data overwrites U-Boot "
-		"and/or placed beyond DRAM boundaries.\n");
-
-	return -1;
-}
-#else
-static inline int splash_load_from_nand(void)
-{
-	return -1;
-}
-#endif /* CONFIG_CMD_NAND */
-
 #ifdef CONFIG_SPL_BUILD
 /*
  * Routine: get_board_mem_timings

@@ -112,24 +68,12 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 }
 #endif
 
+#define CM_T35_SPLASH_NAND_OFFSET 0x100000
+
 int splash_screen_prepare(void)
 {
-	char *env_splashimage_value;
-	u32 bmp_load_addr;
-
-	env_splashimage_value = getenv("splashimage");
-	if (env_splashimage_value == NULL)
-		return -1;
-
-	bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
-	if (bmp_load_addr == 0) {
-		printf("Error: bad splashimage address specified\n");
-		return -1;
-	}
-
-	return splash_load_from_nand(bmp_load_addr);
+	return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET);
 }
-#endif /* CONFIG_LCD */
 
 /*
  * Routine: board_init

index ffe1ef8..7a106d6 100644
@@ -24,4 +24,13 @@ static inline int cl_usb_hub_init(int gpio, const char *label)
 static inline void cl_usb_hub_deinit(int gpio) {}
 #endif /* CONFIG_CMD_USB */
 
+#ifdef CONFIG_SPLASH_SCREEN
+int cl_splash_screen_prepare(int nand_offset);
+#else /* !CONFIG_SPLASH_SCREEN */
+static inline int cl_splash_screen_prepare(int nand_offset)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_SPLASH_SCREEN */
+
 #endif /* _CL_COMMON_ */

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index a3b38ae..3b96318 100644
@@ -23,6 +23,7 @@
 #include <linux/compiler.h>
 
 #include <asm/io.h>
+#include <asm/errno.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/mmc_host_def.h>

@@ -42,16 +43,6 @@ const omap3_sysinfo sysinfo = {
 	"NAND",
 };
 
-static u32 gpmc_net_config[GPMC_MAX_REG] = {
-	NET_GPMC_CONFIG1,
-	NET_GPMC_CONFIG2,
-	NET_GPMC_CONFIG3,
-	NET_GPMC_CONFIG4,
-	NET_GPMC_CONFIG5,
-	NET_GPMC_CONFIG6,
-	0
-};
-
 #ifdef CONFIG_SPL_BUILD
 /*
  * Routine: get_board_mem_timings

@@ -391,37 +382,12 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-/*
- * Routine: setup_net_chip_gmpc
- * Description: Setting up the configuration GPMC registers specific to the
- *		Ethernet hardware.
- */
-static void setup_net_chip_gmpc(void)
-{
-	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
-	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
-			      CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
-	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
-			      SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
-
-	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
-	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
-
-	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
-
-	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
-		&ctrl_base->gpmc_nadv_ale);
-}
-
 #ifdef CONFIG_SYS_I2C_OMAP34XX
 /*
  * Routine: reset_net_chip
  * Description: reset the Ethernet controller via TPS65930 GPIO
  */
-static void reset_net_chip(void)
+static int cm_t3x_reset_net_chip(int gpio)
 {
 	/* Set GPIO1 of TPS65930 as output */
 	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,

@@ -436,9 +402,10 @@ static void reset_net_chip(void)
 	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
 			     0x02);
 	mdelay(1);
+	return 0;
 }
 #else
-static inline void reset_net_chip(void) {}
+static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
 #endif
 
 #ifdef CONFIG_SMC911X

@@ -465,7 +432,6 @@ static int handle_mac_address(void)
 	return eth_setenv_enetaddr("ethaddr", enetaddr);
 }
 
-
 /*
  * Routine: board_eth_init
  * Description: initialize module and base-board Ethernet chips

@@ -474,18 +440,16 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0, rc1 = 0;
 
-	setup_net_chip_gmpc();
-	reset_net_chip();
-
 	rc1 = handle_mac_address();
 	if (rc1)
 		printf("No MAC address found! ");
 
-	rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
+	rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE,
+				    cm_t3x_reset_net_chip, -EINVAL);
 	if (rc1 > 0)
 		rc++;
 
-	rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
+	rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
 	if (rc1 > 0)
 		rc++;
 

index 7a106d6..68ffb11 100644
@@ -33,4 +33,15 @@ static inline int cl_splash_screen_prepare(int nand_offset)
 }
 #endif /* CONFIG_SPLASH_SCREEN */
 
+#ifdef CONFIG_SMC911X
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+			  int (*reset)(int), int rst_gpio);
+#else /* !CONFIG_SMC911X */
+static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+					int (*reset)(int), int rst_gpio)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_SMC911X */
+
 #endif /* _CL_COMMON_ */

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index 3b96318..886c723 100644
@@ -457,16 +457,6 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
-void __weak get_board_serial(struct tag_serialnr *serialnr)
-{
-	/*
-	 * This corresponds to what happens when we can communicate with the
-	 * eeprom but don't get a valid board serial value.
-	 */
-	serialnr->low = 0;
-	serialnr->high = 0;
-};
-
 #ifdef CONFIG_USB_EHCI_OMAP
 struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,

index f2ce522..b25d9a2 100644
@@ -25,6 +25,18 @@ void cl_print_pcb_info(void)
 	printf("PCB:   %u.%u\n", rev_major, rev_minor);
 }
 
+#ifdef CONFIG_SERIAL_TAG
+void __weak get_board_serial(struct tag_serialnr *serialnr)
+{
+	/*
+	 * This corresponds to what happens when we can communicate with the
+	 * eeprom but don't get a valid board serial value.
+	 */
+	serialnr->low = 0;
+	serialnr->high = 0;
+};
+#endif
+
 #ifdef CONFIG_CMD_USB
 int cl_usb_hub_init(int gpio, const char *label)
 {

index 944b723..b1a067d 100644
@@ -100,16 +100,11 @@ uint mmc_get_env_part(struct mmc *mmc)
 #define SB_T54_CD_GPIO 228
 #define SB_T54_WP_GPIO 229
 
-int board_mmc_getcd(struct mmc *mmc)
-{
-	return !gpio_get_value(SB_T54_CD_GPIO);
-}
-
 int board_mmc_init(bd_t *bis)
 {
 	int ret0, ret1;
 
-	ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO);
+	ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO);
 	if (ret0)
 		printf("cm_t54: failed to initialize mmc0\n");
 

index ef2cbf9..ffb5284 100644
@@ -611,7 +611,8 @@ static int omap_hsmmc_getcd(struct mmc *mmc)
 	if (cd_gpio < 0)
 		return 1;
 
-	return gpio_get_value(cd_gpio);
+	/* NOTE: assumes card detect signal is active-low */
+	return !gpio_get_value(cd_gpio);
 }
 
 static int omap_hsmmc_getwp(struct mmc *mmc)

@@ -624,6 +625,7 @@ static int omap_hsmmc_getwp(struct mmc *mmc)
 	if (wp_gpio < 0)
 		return 0;
 
+	/* NOTE: assumes write protect signal is active-high */
 	return gpio_get_value(wp_gpio);
 }
 #endif

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index 056fc15..6abecc2 100644
@@ -8,14 +8,19 @@
 
 #include <common.h>
 #include <status_led.h>
+#include <usb.h>
 #include <mmc.h>
 #include <linux/compiler.h>
+#include <linux/usb/musb.h>
 
 #include <asm/io.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/am35x_def.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/ehci-omap.h>
 
 #include "../common/common.h"
 

@@ -27,6 +32,53 @@ const omap3_sysinfo sysinfo = {
 	"NAND 128/512M",
 };
 
+#ifdef CONFIG_USB_MUSB_AM35X
+static struct musb_hdrc_config cm_t3517_musb_config = {
+	.multipoint     = 1,
+	.dyn_fifo       = 1,
+	.num_eps        = 16,
+	.ram_bits       = 12,
+};
+
+static struct omap_musb_board_data cm_t3517_musb_board_data = {
+	.set_phy_power		= am35x_musb_phy_power,
+	.clear_irq		= am35x_musb_clear_irq,
+	.reset			= am35x_musb_reset,
+};
+
+static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
+#if defined(CONFIG_MUSB_HOST)
+	.mode           = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+	.mode		= MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+	.config         = &cm_t3517_musb_config,
+	.power          = 250,
+	.platform_ops	= &am35x_ops,
+	.board_data	= &cm_t3517_musb_board_data,
+};
+
+static void cm_t3517_musb_init(void)
+{
+	/*
+	 * Set up USB clock/mode in the DEVCONF2 register.
+	 * USB2.0 PHY reference clock is 13 MHz
+	 */
+	clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+			CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
+			CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
+			CONF2_VBDTCTEN | CONF2_DATPOL);
+
+	if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
+			  (void *)AM35XX_IPSS_USBOTGSS_BASE))
+		printf("Failed initializing AM35x MUSB!\n");
+}
+#else
+static inline void am3517_evm_musb_init(void) {}
+#endif
+
 int board_init(void)
 {
 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */

@@ -38,6 +90,8 @@ int board_init(void)
 	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
 #endif
 
+	cm_t3517_musb_init();
+
 	return 0;
 }
 

@@ -58,3 +112,31 @@ int board_mmc_init(bd_t *bis)
 	return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
 }
 #endif
+
+#ifdef CONFIG_USB_EHCI_OMAP
+static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
+	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+#define CM_T3517_USB_HUB_RESET_GPIO	152
+#define SB_T35_USB_HUB_RESET_GPIO	98
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+			struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
+	cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
+
+	return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+	cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
+	cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
+
+	return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI_OMAP */

index f799d21..e1575a6 100644
@@ -104,6 +104,10 @@ void set_muxconf_regs(void)
 	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M4)); /*GPIO_144*/
 	/* WIFI nRESET GPIO145 */
 	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | EN  | M4)); /*GPIO_145*/
+	/* USB1 PHY Reset GPIO 146 */
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | EN  | M4)); /*GPIO_146*/
+	/* USB2 PHY Reset GPIO 147 */
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | EN  | M4)); /*GPIO_147*/
 
 	/* MMC1 */
 	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0));

@@ -119,12 +123,46 @@ void set_muxconf_regs(void)
 	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0));
 	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0));
 
+	/* SB-T35 USB HUB Reset GPIO98 */
+	MUX_VAL(CP(CCDC_WEN),		(IDIS | PTU | EN  | M4)); /*GPIO_98*/
+	/* CM-T3517 USB HUB Reset GPIO152 */
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)); /*GPIO_152*/
+
 	/* Green LED GPIO186 */
 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4)); /*GPIO_186*/
 
 	/* RTC V3020 CS Enable GPIO160 */
 	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTD | EN  | M4)); /*GPIO_160*/
 
+	/* USB0 - mUSB */
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0));
+	/* USB1 EHCI */
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT0*/
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT1*/
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT2*/
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT3*/
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT4*/
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT5*/
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT6*/
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT7*/
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DIR*/
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_NXT*/
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
+	/* USB2 EHCI */
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DT0*/
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DT1*/
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M3)); /*HSUSB2_DT2*/
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M3)); /*HSUSB2_DT3*/
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DT4*/
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DT5*/
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M3)); /*HSUSB2_DT6*/
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | EN  | M3)); /*HSUSB2_DT7*/
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DIR*/
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | EN  | M3)); /*HSUSB2_NXT*/
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+
 	/* SYS_BOOT */
 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTU | DIS | M4)); /*GPIO_2*/
 	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTU | DIS | M4)); /*GPIO_3*/

index 02ec932..1c2d1f4 100644
@@ -98,6 +98,23 @@
 #define CONFIG_OMAP_HSMMC
 #define CONFIG_DOS_PARTITION
 
+/* USB */
+#define CONFIG_USB_MUSB_AM35X
+
+#ifndef CONFIG_USB_MUSB_AM35X
+#define CONFIG_USB_OMAP3
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
+#else /* !CONFIG_USB_MUSB_AM35X */
+#define CONFIG_MUSB_HOST
+#define CONFIG_MUSB_PIO_ONLY
+#endif /* CONFIG_USB_MUSB_AM35X */
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
 /* commands to include */
 #include <config_cmd_default.h>
 

index 6abecc2..cac1ad9 100644
@@ -8,6 +8,8 @@
 
 #include <common.h>
 #include <status_led.h>
+#include <net.h>
+#include <netdev.h>
 #include <usb.h>
 #include <mmc.h>
 #include <linux/compiler.h>

@@ -23,6 +25,7 @@
 #include <asm/ehci-omap.h>
 
 #include "../common/common.h"
+#include "../common/eeprom.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -113,6 +116,92 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONTROL_EFUSE_EMAC_LSB  0x48002380
+#define CONTROL_EFUSE_EMAC_MSB  0x48002384
+
+static int am3517_get_efuse_enetaddr(u8 *enetaddr)
+{
+	u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
+	u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
+
+	enetaddr[0] = (u8)((msb >> 16) & 0xff);
+	enetaddr[1] = (u8)((msb >> 8)  & 0xff);
+	enetaddr[2] = (u8)(msb & 0xff);
+	enetaddr[3] = (u8)((lsb >> 16) & 0xff);
+	enetaddr[4] = (u8)((lsb >> 8)  & 0xff);
+	enetaddr[5] = (u8)(lsb & 0xff);
+
+	return is_valid_ether_addr(enetaddr);
+}
+
+static inline int cm_t3517_init_emac(bd_t *bis)
+{
+	int ret = cpu_eth_init(bis);
+
+	if (ret > 0)
+		return ret;
+
+	printf("Failed initializing EMAC! ");
+	return 0;
+}
+#else /* !CONFIG_DRIVER_TI_EMAC */
+static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
+static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int cm_t3517_handle_mac_address(void)
+{
+	unsigned char enetaddr[6];
+	int ret;
+
+	ret = eth_getenv_enetaddr("ethaddr", enetaddr);
+	if (ret)
+		return 0;
+
+	ret = cl_eeprom_read_mac_addr(enetaddr);
+	if (ret) {
+		ret = am3517_get_efuse_enetaddr(enetaddr);
+		if (ret)
+			return ret;
+	}
+
+	if (!is_valid_ether_addr(enetaddr))
+		return -1;
+
+	return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define SB_T35_ETH_RST_GPIO 164
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0, rc1 = 0;
+
+	rc1 = cm_t3517_handle_mac_address();
+	if (rc1)
+		printf("No MAC address found! ");
+
+	rc1 = cm_t3517_init_emac(bis);
+	if (rc1 > 0)
+		rc++;
+
+	rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
+				    NULL, SB_T35_ETH_RST_GPIO);
+	if (rc1 > 0)
+		rc++;
+
+	return rc;
+}
+
 #ifdef CONFIG_USB_EHCI_OMAP
 static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,

index e1575a6..cb54c2c 100644
@@ -83,6 +83,9 @@ void set_muxconf_regs(void)
 	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
 	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
 
+	/* SB-T35 Ethernet */
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0));
+
 	/* SB-T35 SD/MMC WP GPIO59 */
 	MUX_VAL(CP(GPMC_CLK),		(IEN  | PTU | EN  | M4)); /*GPIO_59*/
 	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));

@@ -93,12 +96,16 @@ void set_muxconf_regs(void)
 	MUX_VAL(CP(GPMC_NBE1),		(IDIS | PTU | EN  | M4)); /*GPIO_61*/
 	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
 	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0));
+	/* SB-T35 Ethernet IRQ GPIO65 */
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M4)); /*GPIO_65*/
 
 	/* UART3 Console */
 	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0));
 	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
 	/* RTC V3020 nCS GPIO163 */
 	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | EN  | M4)); /*GPIO_163*/
+	/* SB-T35 Ethernet nRESET GPIO164 */
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTU | EN  | M4)); /*GPIO_164*/
 
 	/* SB-T35 SD/MMC CD GPIO144 */
 	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M4)); /*GPIO_144*/

@@ -128,6 +135,18 @@ void set_muxconf_regs(void)
 	/* CM-T3517 USB HUB Reset GPIO152 */
 	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)); /*GPIO_152*/
 
+	/* RMII */
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0));
+	MUX_VAL(CP(RMII_RXD0),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(RMII_RXER),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(RMII_TXD0),		(IDIS | M0));
+	MUX_VAL(CP(RMII_TXD1),		(IDIS | M0));
+	MUX_VAL(CP(RMII_TXEN),		(IDIS | M0));
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTU | DIS | M0));
+
 	/* Green LED GPIO186 */
 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4)); /*GPIO_186*/
 

index 1c2d1f4..1d35df9 100644
@@ -132,6 +132,8 @@
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
 #define CONFIG_CMD_GPIO
 
 #undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/

@@ -272,6 +274,15 @@
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
 
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE	(0x2C000000 + (16 << 20))
+#endif /* CONFIG_CMD_NET */
+
 /* additions for new relocation code, must be added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800

index cb54c2c..88ce2cc 100644
@@ -85,6 +85,10 @@ void set_muxconf_regs(void)
 
 	/* SB-T35 Ethernet */
 	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0));
+	/* DVI enable */
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | DIS  | M4));/*GPIO_54*/
+	/* DataImage backlight */
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | DIS  | M4));/*GPIO_58*/
 
 	/* SB-T35 SD/MMC WP GPIO59 */
 	MUX_VAL(CP(GPMC_CLK),		(IEN  | PTU | EN  | M4)); /*GPIO_59*/

@@ -124,6 +128,36 @@ void set_muxconf_regs(void)
 	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0));
 	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0));
 
+	/* DSS */
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0));
+
 	/* I2C */
 	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0));
 	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0));

@@ -150,8 +184,18 @@ void set_muxconf_regs(void)
 	/* Green LED GPIO186 */
 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4)); /*GPIO_186*/
 
+	/* SPI */
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+	MUX_VAL(CP(MCBSP1_DX),		(IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+	MUX_VAL(CP(MCBSP1_DR),		(IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN | PTU | EN  | M1)); /*MCSPI4_CS0*/
+	/* LCD reset GPIO157 */
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | DIS | M4)); /*GPIO_157*/
+
 	/* RTC V3020 CS Enable GPIO160 */
 	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTD | EN  | M4)); /*GPIO_160*/
+	/* SB-T35 LVDS Transmitter SHDN GPIO162 */
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTU | DIS | M4)); /*GPIO_162*/
 
 	/* USB0 - mUSB */
 	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0));

index 1d35df9..d202779 100644
@@ -307,4 +307,19 @@
 #define CONFIG_OMAP3_GPIO_6	/* GPIO186 is in GPIO bank 6  */
 #endif
 
+/* Display Configuration */
+#define CONFIG_OMAP3_GPIO_2
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_VIDEO_OMAP3
+#define LCD_BPP		LCD_COLOR16
+
+#define CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASHIMAGE_GUARD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_SCF0403_LCD
+
+#define CONFIG_OMAP3_SPI
+
 #endif /* __CONFIG_H */