arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

PATCH Superseded Stefan Roese 4 participants 6 messages Nov 7, 2014 – Nov 14, 2014

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Device tree bindings Arm (32-bit) Reset controller framework

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Stefan Roese

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2014-11-07 13:10 UTC #0 lore raw

PATCH v3 1/1 arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support.

Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT.

One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport.

Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img.

Signed-off-by Stefan Roese <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Albert Aribaud <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Simon Glass <[email protected]>

---
v3:
- Add missing gpio.h (even if empty). This header is needed for lib/fdtdec.c to compile.

v2:
- As mentioned in the commit text, this new version does not move the default target to DT (yet). It adds support for the SoCrates board now based on this DT support as the first example. Nothing changes for the current socfpga_cyclone5 target.

 arch/arm/dts/Makefile                      |   2 +
 arch/arm/dts/socfpga.dtsi                  | 755 +++++++++++++++++++++++++++++
 arch/arm/dts/socfpga_cyclone5.dtsi         |  51 ++
 arch/arm/dts/socfpga_cyclone5_socrates.dts |  50 ++
 arch/arm/include/asm/arch-socfpga/gpio.h   |  10 +
 configs/socfpga_socrates_defconfig         |   5 +
 include/dt-bindings/reset/altr,rst-mgr.h   |  90 ++++
 7 files changed, 963 insertions(+)
 create mode 100644 arch/arm/dts/socfpga.dtsi
 create mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates.dts
 create mode 100644 arch/arm/include/asm/arch-socfpga/gpio.h
 create mode 100644 configs/socfpga_socrates_defconfig
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h

arch/arm/dts/Makefile +2 -0

index 52f8926..b946abe 100644
@@ -40,6 +40,8 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
+dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000

arch/arm/dts/socfpga.dtsi new file +755 -0

755 lines not on this page · raw message

arch/arm/dts/socfpga_cyclone5.dtsi new file +51 -0

51 lines not on this page · raw message

arch/arm/dts/socfpga_cyclone5_socrates.dts new file +50 -0

50 lines not on this page · raw message

arch/arm/include/asm/arch-socfpga/gpio.h new file +10 -0

new file mode 100644
index 0000000..6c61f18
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_GPIO_H
+#define _SOCFPGA_GPIO_H
+
+#endif /* _SOCFPGA_GPIO_H */

configs/socfpga_socrates_defconfig new file +5 -0

new file mode 100644
index 0000000..0f3896d
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"

include/dt-bindings/reset/altr,rst-mgr.h new file +90 -0

90 lines not on this page · raw message

Signature · 1 line

2.1.3

Marek Vasut

Applied

2014-11-07 14:59 UTC #1 lore raw

PATCH v3 1/1 arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

Quoted 22 lines · Stefan Roese

This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support.
Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT.
One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport.
Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img.

Quoted 8 lines

Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Simon Glass <[email protected]>

Applied, thanks!

Best regards,
Marek Vasut

Pavel Machek

2014-11-12 17:56 UTC #2 lore raw

PATCH v3 1/1 arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

In reply to Stefan Roese

Quoted 81 lines · Stefan Roese

This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support.
Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT.
One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport.
Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img.
Signed-off-by Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Simon Glass <[email protected]>
---
v3:
- Add missing gpio.h (even if empty). This header is needed for lib/fdtdec.c to compile.
v2:
- As mentioned in the commit text, this new version does not move the default target to DT (yet). It adds support for the SoCrates board now based on this DT support as the first example. Nothing changes for the current socfpga_cyclone5 target.
 arch/arm/dts/Makefile                      |   2 +
 arch/arm/dts/socfpga.dtsi                  | 755 +++++++++++++++++++++++++++++
 arch/arm/dts/socfpga_cyclone5.dtsi         |  51 ++
 arch/arm/dts/socfpga_cyclone5_socrates.dts |  50 ++
 arch/arm/include/asm/arch-socfpga/gpio.h   |  10 +
 configs/socfpga_socrates_defconfig         |   5 +
 include/dt-bindings/reset/altr,rst-mgr.h   |  90 ++++
 7 files changed, 963 insertions(+)
 create mode 100644 arch/arm/dts/socfpga.dtsi
 create mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates.dts
 create mode 100644 arch/arm/include/asm/arch-socfpga/gpio.h
 create mode 100644 configs/socfpga_socrates_defconfig
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h
arch/arm/dts/Makefile +2 -0
index 52f8926..b946abe 100644
@@ -40,6 +40,8 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
+dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
arch/arm/dts/socfpga.dtsi new file +6 -0
new file mode 100644
index 0000000..4472fd9
@@ -0,0 +1,755 @@
+/*
+ *  Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or

arch/arm/dts/socfpga.dtsi line 16

Quoted 10 lines

arch/arm/dts/socfpga.dtsi new file +10 -0

+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */

SPDX? Or do we want to keep it exactly same as in linux?

arch/arm/dts/socfpga.dtsi line 476

Quoted 8 lines

arch/arm/dts/socfpga.dtsi new file +8 -0

+					qspi_clk: qspi_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+						clk-gate = <0xa0 11>;
+					};
+				};
+			};

Any chance to wrap at 80 columns?

Quoted 6 lines

index 0000000..3f04908
include/dt-bindings/reset/altr,rst-mgr.h new file +2 -0
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <[email protected]>

include/dt-bindings/reset/altr,rst-mgr.h line 12

Quoted 10 lines

include/dt-bindings/reset/altr,rst-mgr.h new file +10 -0

+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */

SPDX?

Thanks,
Pavel

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Masahiro Yamada

2014-11-14 06:03 UTC #3 lore raw

PATCH v3 1/1 arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

In reply to Stefan Roese

Hi Stefan,

Quoted 19 lines · On Fri, 7 Nov 2014 14:10:41 +0100 Stefan Roese <[email protected]> wrote:

This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support.
Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT.
One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport.

Quoted 2 lines

Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img.

Since this patch was applied, I see a warning message
WARNING: no status info for 'socfpga_socrates'
WARNING: no maintainers for 'socfpga_socrates'
when I run tools/genboardscfg.py

I think you should add the maintainership info
F: configs/socfpga_socrates_defconfig
to somewhere of MAINTAINERS to suppress the warning message.

Best Regards
Masahiro Yamada

Stefan Roese

author

2014-11-14 07:20 UTC #4 lore raw

PATCH v3 1/1 arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

Hi Masahiro-san,

Quoted 29 lines · Masahiro Yamada

Quoted 19 lines
This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support.
Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT.
One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport.
Quoted 2 lines
Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img.
Since this patch was applied, I see a warning message
WARNING: no status info for 'socfpga_socrates'
WARNING: no maintainers for 'socfpga_socrates'
when I run tools/genboardscfg.py

Quoted 3 lines

I think you should add the maintainership info
F: configs/socfpga_socrates_defconfig
to somewhere of MAINTAINERS to suppress the warning message.

Yes, should be done. Not sure where I should add such information though. We don't have a board directory for this socrates board (yet). And the toplevel MAINTAINERS file seems to be reserved for the custodian entries.

Any ideas / suggestions welcome.

Thanks,
Stefan

Masahiro Yamada

2014-11-14 07:33 UTC #5 lore raw

PATCH v3 1/1 arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

Hi Stefan,

Quoted 32 lines · On Fri, 14 Nov 2014 08:20:06 +0100 Stefan Roese <[email protected]> wrote:

Hi Masahiro-san,
Quoted 29 lines · Masahiro Yamada
Quoted 19 lines
This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support.
Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT.
One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport.
Quoted 2 lines
Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img.
Since this patch was applied, I see a warning message
WARNING: no status info for 'socfpga_socrates'
WARNING: no maintainers for 'socfpga_socrates'
when I run tools/genboardscfg.py

Quoted 8 lines

Quoted 3 lines
I think you should add the maintainership info
F: configs/socfpga_socrates_defconfig
to somewhere of MAINTAINERS to suppress the warning message.
Yes, should be done. Not sure where I should add such information though. We don't have a board directory for this socrates board (yet). And the toplevel MAINTAINERS file seems to be reserved for the custodian entries.
Any ideas / suggestions welcome.

It looks like this socfpga_socrates board borrows most of the parts from socfpga_cyclone board, so I think you can append your maintainership info to board/altera/socfpga/MAINTAINERS.

Perhaps it might be helpful to refer to board/sunxi/MAINTAINERS. The core support of SUNXI boards are owned by Hans de Goede and some additional files are maintained by other people.

Best Regards
Masahiro Yamada