x86: Add additional system setup for ivybridge

At present there is a string for the build date and time. In the case of an Real Time Clock which needs to be reset, it is useful to reset it to the build date, since it can't be earlier than that.

Dear Simon,

Quoted 3 lines · In message <[email protected]> you wrote:

At present there is a string for the build date and time. In the case of an Real Time Clock which needs to be reset, it is useful to reset it to the build date, since it can't be earlier than that.

I can't see the fundamental difference between two wrong dates? The build time of U-Boot is as wrong as any other time.

This function is not needed. Remove it to improve the generic init sequence slightly.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/coreboot/coreboot.c    | 11 -----------
 board/google/chromebook_link/link.c |  5 -----
 common/board_r.c                    |  3 ---
 include/configs/chromebook_link.h   |  1 -
 4 files changed, 20 deletions(-)

arch/x86/cpu/coreboot/coreboot.c +0 -11

index d8ce768..e995e7f 100644
@@ -39,17 +39,6 @@ int board_early_init_f(void)
        return 0;
 }
 
-int board_early_init_r(void)
-{
-       /* CPU Speed to 100MHz */
-       gd->cpu_clk = 100000000;
-
-       /* Crystal is 33.000MHz */
-       gd->bus_clk = 33000000;
-
-       return 0;
-}
-
 int last_stage_init(void)
 {
        if (gd->flags & GD_FLG_COLD_BOOT)

board/google/chromebook_link/link.c +0 -5

index 88cee05..0a1ae61 100644
@@ -12,11 +12,6 @@ int arch_early_init_r(void)
        return 0;
 }
 
-int board_early_init_r(void)
-{
-       return 0;
-}
-
 static const struct pch_gpio_set1 pch_gpio_set1_mode = {
        .gpio0 = GPIO_MODE_GPIO,  /* NMI_DBG# */
        .gpio3 = GPIO_MODE_GPIO,  /* ALS_INT# */

common/board_r.c +0 -3

index 7c33900..8625a90 100644
@@ -837,9 +837,6 @@ init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_CMD_KGDB
        initr_kgdb,
 #endif
-#ifdef CONFIG_X86
-       board_early_init_r,
-#endif
        interrupt_init,
 #if defined(CONFIG_ARM) || defined(CONFIG_x86)
        initr_enable_interrupts,

include/configs/chromebook_link.h +0 -0

index 8caeca6..cd4a8a0 100644

This normally indicates a problem which will prevent relocation from functioning, resulting in a hang. Panic in this case to make it easier to debug.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/lib/relocate.c | 3 +++
 1 file changed, 3 insertions(+)

arch/x86/lib/relocate.c +0 -0

index faca38f..b33586b 100644

Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/u-boot.lds | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

arch/x86/cpu/u-boot.lds +0 -0

index f48bff5..95ab7dd 100644

Quoted 16 lines · Simon Glass

Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/u-boot.lds | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

arch/x86/cpu/u-boot.lds +0 -0

index f48bff5..95ab7dd 100644
@@ -44,7 +44,9 @@ SECTIONS
 

arch/x86/cpu/u-boot.lds SECTIONS · line 48

Quoted 5 lines

arch/x86/cpu/u-boot.lds +2 -1

        . = ALIGN(4);
        __rel_dyn_start = .;
-       .rel.dyn : { *(.rel.dyn) }
+       .rel.dyn : {
+               *(.rel.*)

Should it be more generic to use *(.rel*) here?

arch/x86/cpu/u-boot.lds SECTIONS

Quoted 6 lines

arch/x86/cpu/u-boot.lds +1 -1

+       }
        __rel_dyn_end = .;
        . = ALIGN(4);
        _end = .;
--

Hi Bin,

Quoted 17 lines · Bin Meng

Quoted 16 lines · Simon Glass

Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/u-boot.lds | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

arch/x86/cpu/u-boot.lds +0 -0

index f48bff5..95ab7dd 100644
@@ -44,7 +44,9 @@ SECTIONS
 

Quoted 7 lines

arch/x86/cpu/u-boot.lds SECTIONS · line 48

Quoted 5 lines

arch/x86/cpu/u-boot.lds +2 -1

        . = ALIGN(4);
        __rel_dyn_start = .;
-       .rel.dyn : { *(.rel.dyn) }
+       .rel.dyn : {
+               *(.rel.*)

Should it be more generic to use *(.rel*) here?

I suspect that would be safe, but why?

Quoted 6 lines

arch/x86/cpu/u-boot.lds SECTIONS

Quoted 6 lines

arch/x86/cpu/u-boot.lds +1 -1

+       }
        __rel_dyn_end = .;
        . = ALIGN(4);
        _end = .;
--

Regards,
Simon

This is not needed on x86 and creates a 4GB file due to the addressing used on x86.

This needs to be investigated.

Signed-off-by Simon Glass <[email protected]>

---

 Makefile | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Makefile +0 -0

index fb72c29..c54a2f1 100644
@@ -722,7 +722,10 @@ DO_STATIC_RELA =
 endif
 

Define the reset base in config.mk so that it does not need to be calculated twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values to fit with this new approach.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/config.mk  |  5 +++--
 arch/x86/cpu/u-boot.lds | 13 +++++++++----
 2 files changed, 12 insertions(+), 6 deletions(-)

arch/x86/cpu/config.mk +3 -2

index f7b01d3..84aeaf3 100644
@@ -12,5 +12,6 @@ PLATFORM_CPPFLAGS += -D__I386__ -Werror
 # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
 LDPPFLAGS += -DRESET_SEG_START=0xffff0000
 LDPPFLAGS += -DRESET_SEG_SIZE=0x10000
-LDPPFLAGS += -DRESET_VEC_LOC=0xfff0
-LDPPFLAGS += -DSTART_16=0xf800
+LDPPFLAGS += -DRESET_VEC_LOC=0xfffffff0
+LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16)
+LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)"

arch/x86/cpu/u-boot.lds +0 -0

index 95ab7dd..2a23e18 100644

If the RTC needs to be cleared, write the U-Boot build date to it. In any case make sure the settings are correct.

Signed-off-by Simon Glass <[email protected]>

---

 drivers/rtc/mc146818.c | 49 +++++++++++++++++++++++++++++++++++++++++++++----
 include/rtc.h          |  7 +++++++
 2 files changed, 52 insertions(+), 4 deletions(-)

drivers/rtc/mc146818.c +11 -4

index f7cf106..7528044 100644
@@ -14,6 +14,7 @@
 #include <common.h>
 #include <command.h>
 #include <rtc.h>
+#include <version.h>
 
 #if defined(__I386__) || defined(CONFIG_MALTA)
 #include <asm/io.h>

@@ -42,6 +43,12 @@ static void  rtc_write (uchar reg, uchar val);
 #define RTC_CONFIG_C           0x0C
 #define RTC_CONFIG_D           0x0D
 
+#define RTC_CONFIG_A_REF_CLCK_32KHZ    (1 << 5)
+#define RTC_CONFIG_A_RATE_1024HZ       6
+
+#define RTC_CONFIG_B_24H               (1 << 1)
+
+#define RTC_CONFIG_D_VALID_RAM_AND_TIME        0x80
 
 /* ------------------------------------------------------------------------- */
 

@@ -128,25 +135,59 @@ void rtc_reset (void)
  */
 static uchar rtc_read (uchar reg)
 {
-       return(in8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg));
+       return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
 }
 
 static void rtc_write (uchar reg, uchar val)
 {
-       out8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg, val);
+       out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val);
 }
 #else
 static uchar rtc_read (uchar reg)
 {
        out8(RTC_PORT_MC146818,reg);
-       return(in8(RTC_PORT_MC146818+1));
+       return in8(RTC_PORT_MC146818 + 1);
 }
 
 static void rtc_write (uchar reg, uchar val)
 {
        out8(RTC_PORT_MC146818,reg);
-       out8(RTC_PORT_MC146818+1,val);
+       out8(RTC_PORT_MC146818+1, val);
 }

drivers/rtc/mc146818.c +19 -0

+               for (i = 10; i < 128; i++)
+                       rtc_write(i, 0);
+#endif
+               printf("RTC:%s%s\n",
+                      invalid ? " Clear requested" : "",
+                      CLEAR_CMOS ? " zeroing cmos" : "");
+       }
+
+       /* Setup the real time clock */
+       rtc_write(RTC_CONFIG_B, RTC_CONFIG_B_24H);
+       /* Setup the frequency it operates at */
+       rtc_write(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ |
+                 RTC_CONFIG_A_RATE_1024HZ);
+       /* Ensure all reserved bits are 0 in register D */
+       rtc_write(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME);
+
+       /* Clear any pending interrupts */
+       rtc_read(RTC_CONFIG_C);
+}

include/rtc.h +0 -0

index c034966..8be06bb 100644
@@ -50,4 +50,11 @@ void to_tm (int, struct rtc_time *);
 unsigned long mktime (unsigned int, unsigned int, unsigned int,
                      unsigned int, unsigned int, unsigned int);

If the RTC needs to be cleared, write the U-Boot build date to it. In any case make sure the settings are correct.

Dear Simon,

Quoted 2 lines · In message <[email protected]> you wrote:

If the RTC needs to be cleared, write the U-Boot build date to it. In any case make sure the settings are correct.

Is this really a good idea? Why writing the build date? It is as wrong as any other arbitrarily chose point of time, and when each device comes up with a different (incorrect) time this could be pretty much confusing.

If you need a sane time for initialization, would it not make more sense to chose a fixed date? If you don't want to use the epoch (say, to avoid y2038 issues), you could use 2010-01-01 00:00 or similar instead.

If I see the clock comes up at such a date I will notice that this is an uninitialized time. It it comes up with something as "Tue, 11 Nov 2014 17:17:58" I will assume this is a real time, and wonder what's gone wrong that i's in the past.

Some boards will want to do some setup before and after a PCI hose is scanned.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/pci.c         | 14 +++++++++++++-
 arch/x86/include/asm/pci.h |  3 +++
 2 files changed, 16 insertions(+), 1 deletion(-)

arch/x86/cpu/pci.c +13 -1

index 36057c6..43a4cb9 100644
@@ -32,6 +32,16 @@ int pci_early_init_hose(struct pci_controller **hosep)
        return 0;
 }
 
+__weak int board_pci_pre_scan(struct pci_controller *hose)
+{
+       return 0;
+}
+
+__weak int board_pci_post_scan(struct pci_controller *hose)
+{
+       return 0;
+}
+
 void pci_init_board(void)
 {
        struct pci_controller *hose = &x86_hose;

@@ -42,7 +52,9 @@ void pci_init_board(void)
        board_pci_setup_hose(hose);
        pci_register_hose(hose);
 
-       pci_hose_scan(hose);
+       board_pci_pre_scan(hose);
+       hose->last_busno = pci_hose_scan(hose);
+       board_pci_post_scan(hose);
 }
 
 static struct pci_controller *get_hose(void)

arch/x86/include/asm/pci.h +0 -0

index 98817aa..ac1a808 100644

Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR.

Signed-off-by Simon Glass <[email protected]>

---

 drivers/pci/pci.c | 24 +++++++++++++++++++++---
 include/pci.h     | 23 +++++++++++++++++++++++
 2 files changed, 44 insertions(+), 3 deletions(-)

drivers/pci/pci.c +0 -2

index 60c333e..e879d1e 100644
@@ -363,9 +363,27 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
        return phys_addr;
 }
 
-/*
- *

drivers/pci/pci.c +0 -0

 int pci_hose_config_device(struct pci_controller *hose,
                           pci_dev_t dev,

include/pci.h +16 -0

index 2ff7365..05c67bc 100644
@@ -677,5 +677,28 @@ extern void pci_mpc824x_init (struct pci_controller *hose);
 extern void pci_mpc85xx_init (struct pci_controller *hose);
 #endif
 
+/**
+ * pci_config_fixed() - Write the address of a BAR including control bits
+ *
+ * This writes a raw address (with control bits) to a bar
+ *
+ * @hose:      PCI hose to use
+ * @dev:       PCI device to update
+ * @barnum:    BAR number (0-5)
+ * @addr:      BAR address with controll bits
+ */
+void pci_config_fixed(struct pci_controller *hose, pci_dev_t dev, int barnum,
+                     u32 addr);
+
+/**
+ * pci_read_bar() - read the address of a bar
+ *

The i8259 is a basic interrupt controller from the 1970s which is still present in modern Intel hardware. Add some code to set it up.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/include/asm/i8259.h |   3 +
 arch/x86/lib/Makefile        |   1 +
 arch/x86/lib/i8259.c         | 134 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 138 insertions(+)
 create mode 100644 arch/x86/lib/i8259.c

arch/x86/include/asm/i8259.h +3 -0

index 73113f9..bac073d 100644
@@ -69,4 +69,7 @@
 #define        ICW4_AEOI       0x02    /* Automatic EOI Mode */
 #define ICW4_PM                0x01    /* Microprocessor Mode */
 
+void i8259_setup(void);
+void i8259_configure_irq_trigger(int int_num, bool is_level_triggered);
+
 #endif

arch/x86/lib/Makefile +1 -0

index d0c7f30..2d75f9f 100644
@@ -8,6 +8,7 @@
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y  += cmd_boot.o
 obj-y  += gcc.o
+obj-y += i8259.o
 obj-y  += init_helpers.o
 obj-y  += interrupts.o
 obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o

arch/x86/lib/i8259.c new file +125 -0

new file mode 100644
index 0000000..442d904
@@ -0,0 +1,134 @@
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/i8259.h>
+
+#define MASTER_PIC_ICW1                0x20
+#define SLAVE_PIC_ICW1         0xa0
+#define   ICW_SELECT           (1 << 4)
+#define   OCW_SELECT           (0 << 4)
+#define   ADI                  (1 << 2)
+#define   SNGL                 (1 << 1)
+#define   IC4                  (1 << 0)
+
+#define MASTER_PIC_ICW2                0x21
+#define SLAVE_PIC_ICW2         0xa1
+#define   INT_VECTOR_MASTER    0x20
+#define   IRQ0                 0x00
+#define   IRQ1                 0x01
+#define   INT_VECTOR_SLAVE     0x28
+#define   IRQ8                 0x00
+#define   IRQ9                 0x01
+
+#define MASTER_PIC_ICW3                0x21
+#define   CASCADED_PIC         (1 << 2)
+
+#define MASTER_PIC_ICW4                0x21
+#define SLAVE_PIC_ICW4         0xa1
+#define   MICROPROCESSOR_MODE  (1 << 0)
+
+#define SLAVE_PIC_ICW3         0xa1
+#define    SLAVE_ID            0x02
+
+#define MASTER_PIC_OCW1                0x21
+#define SLAVE_PIC_OCW1         0xa1
+#define    IRQ2                        (1 << 2)
+#define    ALL_IRQS            0xff
+
+#define ELCR1                  0x4d0
+#define ELCR2                  0x4d1
+
+void i8259_setup(void)
+{
+       /* A write to ICW1 starts the Interrupt Controller Initialization
+        * Sequence. This implicitly causes the following to happen:
+        *   - Interrupt Mask register is cleared
+        *   - Priority 7 is assigned to IRQ7 input
+        *   - Slave mode address is set to 7
+        *   - Special mask mode is cleared
+        *
+        * We send the initialization sequence to both the master and
+        * slave i8259 controller.
+        */
+       outb(ICW_SELECT|IC4, MASTER_PIC_ICW1);
+       outb(ICW_SELECT|IC4, SLAVE_PIC_ICW1);
+
+       /* Now the interrupt controller expects us to write to ICW2. */
+       outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2);
+       outb(INT_VECTOR_SLAVE  | IRQ8, SLAVE_PIC_ICW2);
+
+       /* Now the interrupt controller expects us to write to ICW3.
+        *
+        * The normal scenario is to set up cascading on IRQ2 on the master
+        * i8259 and assign the slave ID 2 to the slave i8259.
+        */
+       outb(CASCADED_PIC, MASTER_PIC_ICW3);
+       outb(SLAVE_ID, SLAVE_PIC_ICW3);
+
+       /* Now the interrupt controller expects us to write to ICW4.
+        *
+        * We switch both i8259 to microprocessor mode because they're
+        * operating as part of an x86 architecture based chipset
+        */
+       outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2);
+       outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2);
+
+       /* Now clear the interrupts through OCW1.
+        * First we mask off all interrupts on the slave interrupt controller
+        * then we mask off all interrupts but interrupt 2 on the master
+        * controller. This way the cascading stays alife.
+        */
+       outb(ALL_IRQS, SLAVE_PIC_OCW1);
+       outb(ALL_IRQS & ~IRQ2, MASTER_PIC_OCW1);
+       debug("i8259 inited\n");
+}
+
+/**
+ * i8259_configure_irq_trigger() - Configure IRQ triggering
+ *
+ * Switch the given interrupt to be level / edge triggered
+ *
+ * @param int_num legacy interrupt number (3-7, 9-15)
+ * @param is_level_triggered true for level triggered interrupt, false for
+ *     edge triggered interrupt
+ */
+void i8259_configure_irq_trigger(int int_num, bool is_level_triggered)
+{
+       u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
+
+       debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
+       if (is_level_triggered)
+               int_bits |= (1 << int_num);
+       else
+               int_bits &= ~(1 << int_num);
+
+       /* Write new values */
+       debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
+       outb((u8)(int_bits & 0xff), ELCR1);
+       outb((u8)(int_bits >> 8), ELCR2);
+
+#ifdef PARANOID_IRQ_TRIGGERS
+       /*
+        * Try reading back the new values. This seems like an error but is
+        * not
+        */
+       if (inb(ELCR1) != (int_bits & 0xff)) {
+               printf("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
+                      __func__, (int_bits & 0xff), inb(ELCR1));
+       }

Add simple init for the ISA DMA settings.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/include/asm/isa_dma.h | 14 +++++++++++
 arch/x86/lib/Makefile          |  1 +
 arch/x86/lib/isa_dma.c         | 56 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)
 create mode 100644 arch/x86/include/asm/isa_dma.h
 create mode 100644 arch/x86/lib/isa_dma.c

arch/x86/include/asm/isa_dma.h new file +14 -0

new file mode 100644
index 0000000..69c6a84
@@ -0,0 +1,14 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2014 Google, Inc
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef __ASM_ISA_DMA_H
+#define _ASM_ISA_DMA_H
+
+void isa_dma_init(void);
+
+#endif

arch/x86/lib/Makefile +1 -0

index 2d75f9f..622ef08 100644
@@ -11,6 +11,7 @@ obj-y += gcc.o
 obj-y += i8259.o
 obj-y  += init_helpers.o
 obj-y  += interrupts.o
+obj-y += isa_dma.o
 obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
 obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
 obj-$(CONFIG_PCI) += pci_type1.o

arch/x86/lib/isa_dma.c new file +47 -0

new file mode 100644
index 0000000..36d6ee5
@@ -0,0 +1,56 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2014 Google, Inc
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/isa_dma.h>
+
+/* DMA controller registers */
+#define DMA1_CMD_REG           0x08    /* command register (w) */
+#define DMA1_STAT_REG          0x08    /* status register (r) */
+#define DMA1_REQ_REG            0x09    /* request register (w) */
+#define DMA1_MASK_REG          0x0A    /* single-channel mask (w) */
+#define DMA1_MODE_REG          0x0B    /* mode register (w) */
+#define DMA1_CLEAR_FF_REG      0x0C    /* clear pointer flip-flop (w) */
+#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
+#define DMA1_RESET_REG         0x0D    /* Master Clear (w) */
+#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
+#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
+
+#define DMA2_CMD_REG           0xD0    /* command register (w) */
+#define DMA2_STAT_REG          0xD0    /* status register (r) */
+#define DMA2_REQ_REG            0xD2    /* request register (w) */
+#define DMA2_MASK_REG          0xD4    /* single-channel mask (w) */
+#define DMA2_MODE_REG          0xD6    /* mode register (w) */
+#define DMA2_CLEAR_FF_REG      0xD8    /* clear pointer flip-flop (w) */
+#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
+#define DMA2_RESET_REG         0xDA    /* Master Clear (w) */
+#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
+#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
+
+/* I/O to memory, no autoinit, increment, single mode */
+#define DMA_MODE_READ  0x44
+/* memory to I/O, no autoinit, increment, single mode */
+#define DMA_MODE_WRITE 0x48
+#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
+
+#define DMA_AUTOINIT   0x10
+
+void isa_dma_init(void)
+{
+       /*
+        * slave at 0x00 - 0x0f

Add code to set up the SATA interfaces on boot.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/ivybridge/Makefile               |   1 +
 arch/x86/cpu/ivybridge/bd82x6x.c              |  20 +++
 arch/x86/cpu/ivybridge/sata.c                 | 243 ++++++++++++++++++++++++++
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h |   2 +
 arch/x86/include/asm/arch-ivybridge/pch.h     |  58 ++++++
 doc/device-tree-bindings/ata/intel-sata.txt   |  26 +++
 include/fdtdec.h                              |   1 +
 lib/fdtdec.c                                  |   1 +
 8 files changed, 352 insertions(+)
 create mode 100644 arch/x86/cpu/ivybridge/sata.c
 create mode 100644 doc/device-tree-bindings/ata/intel-sata.txt

arch/x86/cpu/ivybridge/Makefile +1 -0

index 479e446..c6342cd 100644
@@ -15,4 +15,5 @@ obj-y += microcode_intel.o
 obj-y += pch.o
 obj-y += pci.o
 obj-y += report_platform.o
+obj-y += sata.o
 obj-y += sdram.o

arch/x86/cpu/ivybridge/bd82x6x.c +20 -0

index be4db74..b54f5c7 100644
@@ -88,18 +88,38 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
 
 int bd82x6x_init_pci_devices(void)
 {
+       const void *blob = gd->fdt_blob;
        struct pci_controller *hose;
+       int sata_node;
 
        hose = pci_bus_to_hose(0);
        lpc_enable(PCH_LPC_DEV);
        lpc_init(hose, PCH_LPC_DEV);
+       sata_node = fdtdec_next_compatible(blob, 0,
+                                          COMPAT_INTEL_PANTHERPOINT_AHCI);
+       if (sata_node < 0) {
+               debug("%s: Cannot find SATA node\n", __func__);
+               return -EINVAL;
+       }
+       bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
 
        return 0;
 }
 
 int bd82x6x_init(void)
 {
+       const void *blob = gd->fdt_blob;
+       int sata_node;
+
+       sata_node = fdtdec_next_compatible(blob, 0,
+                                          COMPAT_INTEL_PANTHERPOINT_AHCI);
+       if (sata_node < 0) {
+               debug("%s: Cannot find SATA node\n", __func__);
+               return -EINVAL;
+       }
+
        bd82x6x_pci_init(PCH_DEV);
+       bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
 
        return 0;
 }

arch/x86/cpu/ivybridge/sata.c new file +213 -0

new file mode 100644
index 0000000..134afb9
@@ -0,0 +1,243 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/bd82x6x.h>
+
+static inline u32 sir_read(pci_dev_t dev, int idx)
+{
+       pci_write_config32(dev, SATA_SIRI, idx);
+       return pci_read_config32(dev, SATA_SIRD);
+}
+
+static inline void sir_write(pci_dev_t dev, int idx, u32 value)
+{
+       pci_write_config32(dev, SATA_SIRI, idx);
+       pci_write_config32(dev, SATA_SIRD, value);
+}
+
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
+{
+       unsigned int port_map, speed_support, port_tx;
+       const char *mode;
+       u32 reg32;
+       u16 reg16;
+
+       debug("SATA: Initializing...\n");
+
+       /* SATA configuration */
+       port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+       speed_support = fdtdec_get_int(blob, node,
+                                      "sata_interface_speed_support", 0);
+
+       /* Enable BARs */
+       pci_write_config16(dev, PCI_COMMAND, 0x0007);
+
+       mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+       if (!mode || !strcmp(mode, "ahci")) {
+               u32 abar;
+
+               debug("SATA: Controller in AHCI mode\n");
+
+               /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
+               pci_write_config8(dev, INTR_LN, 0x0a);
+
+               /* Set timings */
+               pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+                               IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+                               IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+               pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+                               IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+               /* Sync DMA */
+               pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+               pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+
+               /* Set IDE I/O Configuration */
+               reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 |
+                               PCB0;
+               pci_write_config32(dev, IDE_CONFIG, reg32);
+
+               /* for AHCI, Port Enable is managed in memory-mapped space */
+               reg16 = pci_read_config16(dev, 0x92);
+               reg16 &= ~0x3f; /* 6 ports SKU + ORM */
+               reg16 |= 0x8000 | port_map;
+               pci_write_config16(dev, 0x92, reg16);
+
+               /* SATA Initialization register */
+               pci_write_config32(dev, 0x94,
+                                  ((port_map ^ 0x3f) << 24) | 0x183);
+
+               /* Initialize AHCI memory-mapped space */
+               abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5) & ~1;
+               debug("ABAR: %08X\n", abar);
+               /* CAP (HBA Capabilities) : enable power management */
+               reg32 = readl(abar + 0x00);
+               reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
+               reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
+               /* Set ISS, if available */
+               if (speed_support) {
+                       reg32 &= ~0x00f00000;
+                       reg32 |= (speed_support & 0x03) << 20;
+               }
+               writel(reg32, abar + 0x00);
+               /* PI (Ports implemented) */
+               writel(port_map, abar + 0x0c);
+               (void) readl(abar + 0x0c); /* Read back 1 */
+               (void) readl(abar + 0x0c); /* Read back 2 */
+               /* CAP2 (HBA Capabilities Extended)*/
+               reg32 = readl(abar + 0x24);
+               reg32 &= ~0x00000002;
+               writel(reg32, abar + 0x24);
+               /* VSP (Vendor Specific Register */
+               reg32 = readl(abar + 0xa0);
+               reg32 &= ~0x00000005;
+               writel(reg32, abar + 0xa0);
+       } else if (!strcmp(mode, "combined")) {
+               debug("SATA: Controller in combined mode\n");
+
+               /* No AHCI: clear AHCI base */
+               pci_write_config32(dev, 0x24, 0x00000000);
+               /* And without AHCI BAR no memory decoding */
+               reg16 = pci_read_config16(dev, PCI_COMMAND);
+               reg16 &= ~PCI_COMMAND_MEMORY;
+               pci_write_config16(dev, PCI_COMMAND, reg16);
+
+               pci_write_config8(dev, 0x09, 0x80);
+
+               /* Set timings */
+               pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+                               IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+               pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+                               IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+                               IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+
+               /* Sync DMA */
+               pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+               pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+
+               /* Set IDE I/O Configuration */
+               reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 |
+                               PCB0;
+               pci_write_config32(dev, IDE_CONFIG, reg32);
+
+               /* Port enable */
+               reg16 = pci_read_config16(dev, 0x92);
+               reg16 &= ~0x3f;
+               reg16 |= port_map;
+               pci_write_config16(dev, 0x92, reg16);
+
+               /* SATA Initialization register */
+               pci_write_config32(dev, 0x94,
+                                  ((port_map ^ 0x3f) << 24) | 0x183);
+       } else {
+               debug("SATA: Controller in plain-ide mode\n");
+
+               /* No AHCI: clear AHCI base */
+               pci_write_config32(dev, 0x24, 0x00000000);
+
+               /* And without AHCI BAR no memory decoding */
+               reg16 = pci_read_config16(dev, PCI_COMMAND);
+               reg16 &= ~PCI_COMMAND_MEMORY;
+               pci_write_config16(dev, PCI_COMMAND, reg16);
+
+               /*
+                * Native mode capable on both primary and secondary (0xa)
+                * OR'ed with enabled (0x50) = 0xf
+                */
+               pci_write_config8(dev, 0x09, 0x8f);
+
+               /* Set Interrupt Line */
+               /* Interrupt Pin is set by D31IP.PIP */
+               pci_write_config8(dev, INTR_LN, 0xff);
+
+               /* Set timings */
+               pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+                               IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+                               IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+               pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+                               IDE_SITRE | IDE_ISP_3_CLOCKS |
+                               IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+
+               /* Sync DMA */
+               pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+               pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+
+               /* Set IDE I/O Configuration */
+               reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 |
+                               PCB0;
+               pci_write_config32(dev, IDE_CONFIG, reg32);
+
+               /* Port enable */
+               reg16 = pci_read_config16(dev, 0x92);
+               reg16 &= ~0x3f;
+               reg16 |= port_map;
+               pci_write_config16(dev, 0x92, reg16);
+
+               /* SATA Initialization register */
+               pci_write_config32(dev, 0x94,
+                                  ((port_map ^ 0x3f) << 24) | 0x183);
+       }
+
+       /* Set Gen3 Transmitter settings if needed */
+       port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
+       if (port_tx)
+               pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
+
+       port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
+       if (port_tx)
+               pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
+
+       /* Additional Programming Requirements */
+       sir_write(dev, 0x04, 0x00001600);
+       sir_write(dev, 0x28, 0xa0000033);
+       reg32 = sir_read(dev, 0x54);
+       reg32 &= 0xff000000;
+       reg32 |= 0x5555aa;
+       sir_write(dev, 0x54, reg32);
+       sir_write(dev, 0x64, 0xcccc8484);
+       reg32 = sir_read(dev, 0x68);
+       reg32 &= 0xffff0000;
+       reg32 |= 0xcccc;
+       sir_write(dev, 0x68, reg32);
+       reg32 = sir_read(dev, 0x78);
+       reg32 &= 0x0000ffff;
+       reg32 |= 0x88880000;

arch/x86/cpu/ivybridge/sata.c new file +20 -0

+}
+
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
+{
+       unsigned port_map;
+       const char *mode;
+       u16 map = 0;
+
+       /*
+        * Set SATA controller mode early so the resource allocator can
+        * properly assign IO/Memory resources for the controller.
+        */
+       mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+       if (mode && !strcmp(mode, "ahci"))
+               map = 0x0060;
+       port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+
+       map |= (port_map ^ 0x3f) << 8;
+       pci_write_config16(dev, 0x90, map);
+}

arch/x86/include/asm/arch-ivybridge/bd82x6x.h +2 -0

index e02520c..644755f 100644
@@ -7,6 +7,8 @@
 #ifndef _ASM_ARCH_BD82X6X_H
 #define _ASM_ARCH_BD82X6X_H
 
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_pci_init(pci_dev_t dev);
 int bd82x6x_init_pci_devices(void);
 int bd82x6x_init(void);

arch/x86/include/asm/arch-ivybridge/pch.h +58 -0

index b3ec7c5..21df083 100644
@@ -122,6 +122,64 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 #define LPC_GEN4_DEC           0x90 /* LPC IF Generic Decode Range 4 */
 #define LPC_GENX_DEC(x)                (0x84 + 4 * (x))
 
+/* PCI Configuration Space (D31:F1): IDE */
+#define PCH_IDE_DEV            PCI_BDF(0, 0x1f, 1)
+#define PCH_SATA_DEV           PCI_BDF(0, 0x1f, 2)
+#define PCH_SATA2_DEV          PCI_BDF(0, 0x1f, 5)
+
+#define INTR_LN                        0x3c
+#define IDE_TIM_PRI            0x40    /* IDE timings, primary */
+#define   IDE_DECODE_ENABLE    (1 << 15)
+#define   IDE_SITRE            (1 << 14)
+#define   IDE_ISP_5_CLOCKS     (0 << 12)
+#define   IDE_ISP_4_CLOCKS     (1 << 12)
+#define   IDE_ISP_3_CLOCKS     (2 << 12)
+#define   IDE_RCT_4_CLOCKS     (0 <<  8)
+#define   IDE_RCT_3_CLOCKS     (1 <<  8)
+#define   IDE_RCT_2_CLOCKS     (2 <<  8)
+#define   IDE_RCT_1_CLOCKS     (3 <<  8)
+#define   IDE_DTE1             (1 <<  7)
+#define   IDE_PPE1             (1 <<  6)
+#define   IDE_IE1              (1 <<  5)
+#define   IDE_TIME1            (1 <<  4)
+#define   IDE_DTE0             (1 <<  3)
+#define   IDE_PPE0             (1 <<  2)
+#define   IDE_IE0              (1 <<  1)
+#define   IDE_TIME0            (1 <<  0)
+#define IDE_TIM_SEC            0x42    /* IDE timings, secondary */
+
+#define IDE_SDMA_CNT           0x48    /* Synchronous DMA control */
+#define   IDE_SSDE1            (1 <<  3)
+#define   IDE_SSDE0            (1 <<  2)
+#define   IDE_PSDE1            (1 <<  1)
+#define   IDE_PSDE0            (1 <<  0)
+
+#define IDE_SDMA_TIM           0x4a
+
+#define IDE_CONFIG             0x54    /* IDE I/O Configuration Register */
+#define   SIG_MODE_SEC_NORMAL  (0 << 18)
+#define   SIG_MODE_SEC_TRISTATE        (1 << 18)
+#define   SIG_MODE_SEC_DRIVELOW        (2 << 18)
+#define   SIG_MODE_PRI_NORMAL  (0 << 16)
+#define   SIG_MODE_PRI_TRISTATE        (1 << 16)
+#define   SIG_MODE_PRI_DRIVELOW        (2 << 16)
+#define   FAST_SCB1            (1 << 15)
+#define   FAST_SCB0            (1 << 14)
+#define   FAST_PCB1            (1 << 13)
+#define   FAST_PCB0            (1 << 12)
+#define   SCB1                 (1 <<  3)
+#define   SCB0                 (1 <<  2)
+#define   PCB1                 (1 <<  1)
+#define   PCB0                 (1 <<  0)
+
+#define SATA_SIRI              0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD              0xa4 /* SATA Indexed Register Data */
+#define SATA_SP                        0xd0 /* Scratchpad */
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR      0xea000151
+#define SATA_IOBP_SP1G3IR      0xea000051
+
 /* PCI Configuration Space (D31:F3): SMBus */
 #define PCH_SMBUS_DEV          PCI_BDF(0, 0x1f, 3)
 #define SMB_BASE               0x20

doc/device-tree-bindings/ata/intel-sata.txt new file +26 -0

new file mode 100644
index 0000000..5e4da83
@@ -0,0 +1,26 @@
+Intel Pantherpoint SATA Device Binding
+======================================
+
+The device tree node which describes the operation of the Intel Pantherpoint
+SATA device is as follows:
+
+Required properties :
+- compatible = "intel,pantherpoint-ahci"
+- intel,sata-mode : string, one of:
+     "ahci" : Use AHCI mode (default)
+     "combined" : Use combined IDE + legacy mode
+     "plain-ide" : Use plain IDE mode
+- intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
+    bit 1=enable second port, etc.
+- intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
+- intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
+
+Example
+-------
+
+sata {
+       compatible = "intel,pantherpoint-ahci";
+       intel,sata-mode = "ahci";
+       intel,sata-port-map = <1>;
+       intel,sata-port0-gen3-tx = <0x00880a7f>;
+};

include/fdtdec.h +0 -0

index abfd678..0a0afce 100644

include/fdtdec.h +0 -0

        COMPAT_COUNT,
 };

lib/fdtdec.c +0 -0

index aafc4f9..8865a26 100644

Hi Simon,

Quoted 289 lines · Simon Glass

Add code to set up the SATA interfaces on boot.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/ivybridge/Makefile               |   1 +
 arch/x86/cpu/ivybridge/bd82x6x.c              |  20 +++
 arch/x86/cpu/ivybridge/sata.c                 | 243 ++++++++++++++++++++++++++
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h |   2 +
 arch/x86/include/asm/arch-ivybridge/pch.h     |  58 ++++++
 doc/device-tree-bindings/ata/intel-sata.txt   |  26 +++
 include/fdtdec.h                              |   1 +
 lib/fdtdec.c                                  |   1 +
 8 files changed, 352 insertions(+)
 create mode 100644 arch/x86/cpu/ivybridge/sata.c
 create mode 100644 doc/device-tree-bindings/ata/intel-sata.txt

arch/x86/cpu/ivybridge/Makefile +1 -0

index 479e446..c6342cd 100644
@@ -15,4 +15,5 @@ obj-y += microcode_intel.o
 obj-y += pch.o
 obj-y += pci.o
 obj-y += report_platform.o
+obj-y += sata.o
 obj-y += sdram.o

arch/x86/cpu/ivybridge/bd82x6x.c +20 -0

index be4db74..b54f5c7 100644
@@ -88,18 +88,38 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
 
 int bd82x6x_init_pci_devices(void)
 {
+       const void *blob = gd->fdt_blob;
        struct pci_controller *hose;
+       int sata_node;
 
        hose = pci_bus_to_hose(0);
        lpc_enable(PCH_LPC_DEV);
        lpc_init(hose, PCH_LPC_DEV);
+       sata_node = fdtdec_next_compatible(blob, 0,
+                                          COMPAT_INTEL_PANTHERPOINT_AHCI);
+       if (sata_node < 0) {
+               debug("%s: Cannot find SATA node\n", __func__);
+               return -EINVAL;
+       }
+       bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
 
        return 0;
 }
 
 int bd82x6x_init(void)
 {
+       const void *blob = gd->fdt_blob;
+       int sata_node;
+
+       sata_node = fdtdec_next_compatible(blob, 0,
+                                          COMPAT_INTEL_PANTHERPOINT_AHCI);
+       if (sata_node < 0) {
+               debug("%s: Cannot find SATA node\n", __func__);
+               return -EINVAL;
+       }
+
        bd82x6x_pci_init(PCH_DEV);
+       bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
 
        return 0;
 }

arch/x86/cpu/ivybridge/sata.c new file +213 -0

new file mode 100644
index 0000000..134afb9
@@ -0,0 +1,243 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/bd82x6x.h>
+
+static inline u32 sir_read(pci_dev_t dev, int idx)
+{
+       pci_write_config32(dev, SATA_SIRI, idx);
+       return pci_read_config32(dev, SATA_SIRD);
+}
+
+static inline void sir_write(pci_dev_t dev, int idx, u32 value)
+{
+       pci_write_config32(dev, SATA_SIRI, idx);
+       pci_write_config32(dev, SATA_SIRD, value);
+}
+
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
+{
+       unsigned int port_map, speed_support, port_tx;
+       const char *mode;
+       u32 reg32;
+       u16 reg16;
+
+       debug("SATA: Initializing...\n");
+
+       /* SATA configuration */
+       port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+       speed_support = fdtdec_get_int(blob, node,
+                                      "sata_interface_speed_support", 0);
+
+       /* Enable BARs */
+       pci_write_config16(dev, PCI_COMMAND, 0x0007);
+
+       mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+       if (!mode || !strcmp(mode, "ahci")) {
+               u32 abar;
+
+               debug("SATA: Controller in AHCI mode\n");
+
+               /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
+               pci_write_config8(dev, INTR_LN, 0x0a);
+
+               /* Set timings */
+               pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+                               IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+                               IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+               pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+                               IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+               /* Sync DMA */
+               pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+               pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+
+               /* Set IDE I/O Configuration */
+               reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 |
+                               PCB0;
+               pci_write_config32(dev, IDE_CONFIG, reg32);
+
+               /* for AHCI, Port Enable is managed in memory-mapped space */
+               reg16 = pci_read_config16(dev, 0x92);
+               reg16 &= ~0x3f; /* 6 ports SKU + ORM */
+               reg16 |= 0x8000 | port_map;
+               pci_write_config16(dev, 0x92, reg16);
+
+               /* SATA Initialization register */
+               pci_write_config32(dev, 0x94,
+                                  ((port_map ^ 0x3f) << 24) | 0x183);
+
+               /* Initialize AHCI memory-mapped space */
+               abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5) & ~1;
+               debug("ABAR: %08X\n", abar);
+               /* CAP (HBA Capabilities) : enable power management */
+               reg32 = readl(abar + 0x00);
+               reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
+               reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
+               /* Set ISS, if available */
+               if (speed_support) {
+                       reg32 &= ~0x00f00000;
+                       reg32 |= (speed_support & 0x03) << 20;
+               }
+               writel(reg32, abar + 0x00);
+               /* PI (Ports implemented) */
+               writel(port_map, abar + 0x0c);
+               (void) readl(abar + 0x0c); /* Read back 1 */
+               (void) readl(abar + 0x0c); /* Read back 2 */
+               /* CAP2 (HBA Capabilities Extended)*/
+               reg32 = readl(abar + 0x24);
+               reg32 &= ~0x00000002;
+               writel(reg32, abar + 0x24);
+               /* VSP (Vendor Specific Register */
+               reg32 = readl(abar + 0xa0);
+               reg32 &= ~0x00000005;
+               writel(reg32, abar + 0xa0);
+       } else if (!strcmp(mode, "combined")) {
+               debug("SATA: Controller in combined mode\n");
+
+               /* No AHCI: clear AHCI base */
+               pci_write_config32(dev, 0x24, 0x00000000);
+               /* And without AHCI BAR no memory decoding */
+               reg16 = pci_read_config16(dev, PCI_COMMAND);
+               reg16 &= ~PCI_COMMAND_MEMORY;
+               pci_write_config16(dev, PCI_COMMAND, reg16);
+
+               pci_write_config8(dev, 0x09, 0x80);
+
+               /* Set timings */
+               pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+                               IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+               pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+                               IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+                               IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+
+               /* Sync DMA */
+               pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+               pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+
+               /* Set IDE I/O Configuration */
+               reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 |
+                               PCB0;
+               pci_write_config32(dev, IDE_CONFIG, reg32);
+
+               /* Port enable */
+               reg16 = pci_read_config16(dev, 0x92);
+               reg16 &= ~0x3f;
+               reg16 |= port_map;
+               pci_write_config16(dev, 0x92, reg16);
+
+               /* SATA Initialization register */
+               pci_write_config32(dev, 0x94,
+                                  ((port_map ^ 0x3f) << 24) | 0x183);
+       } else {
+               debug("SATA: Controller in plain-ide mode\n");
+
+               /* No AHCI: clear AHCI base */
+               pci_write_config32(dev, 0x24, 0x00000000);
+
+               /* And without AHCI BAR no memory decoding */
+               reg16 = pci_read_config16(dev, PCI_COMMAND);
+               reg16 &= ~PCI_COMMAND_MEMORY;
+               pci_write_config16(dev, PCI_COMMAND, reg16);
+
+               /*
+                * Native mode capable on both primary and secondary (0xa)
+                * OR'ed with enabled (0x50) = 0xf
+                */
+               pci_write_config8(dev, 0x09, 0x8f);
+
+               /* Set Interrupt Line */
+               /* Interrupt Pin is set by D31IP.PIP */
+               pci_write_config8(dev, INTR_LN, 0xff);
+
+               /* Set timings */
+               pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+                               IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+                               IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+               pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+                               IDE_SITRE | IDE_ISP_3_CLOCKS |
+                               IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+
+               /* Sync DMA */
+               pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+               pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+
+               /* Set IDE I/O Configuration */
+               reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 |
+                               PCB0;
+               pci_write_config32(dev, IDE_CONFIG, reg32);
+
+               /* Port enable */
+               reg16 = pci_read_config16(dev, 0x92);
+               reg16 &= ~0x3f;
+               reg16 |= port_map;
+               pci_write_config16(dev, 0x92, reg16);
+
+               /* SATA Initialization register */
+               pci_write_config32(dev, 0x94,
+                                  ((port_map ^ 0x3f) << 24) | 0x183);
+       }
+
+       /* Set Gen3 Transmitter settings if needed */
+       port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
+       if (port_tx)
+               pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
+
+       port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
+       if (port_tx)
+               pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
+
+       /* Additional Programming Requirements */
+       sir_write(dev, 0x04, 0x00001600);
+       sir_write(dev, 0x28, 0xa0000033);
+       reg32 = sir_read(dev, 0x54);
+       reg32 &= 0xff000000;
+       reg32 |= 0x5555aa;
+       sir_write(dev, 0x54, reg32);
+       sir_write(dev, 0x64, 0xcccc8484);
+       reg32 = sir_read(dev, 0x68);
+       reg32 &= 0xffff0000;
+       reg32 |= 0xcccc;
+       sir_write(dev, 0x68, reg32);
+       reg32 = sir_read(dev, 0x78);
+       reg32 &= 0x0000ffff;
+       reg32 |= 0x88880000;

arch/x86/cpu/ivybridge/sata.c line 223

Quoted 10 lines

arch/x86/cpu/ivybridge/sata.c new file +10 -0

+       sir_write(dev, 0x78, reg32);
+       sir_write(dev, 0x84, 0x001c7000);
+       sir_write(dev, 0x88, 0x88338822);
+       sir_write(dev, 0xa0, 0x001c7000);
+       sir_write(dev, 0xc4, 0x0c0c0c0c);
+       sir_write(dev, 0xc8, 0x0c0c0c0c);
+       sir_write(dev, 0xd4, 0x10000000);
+
+       pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
+       pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);

There are many magic numbers here.

Quoted 139 lines

arch/x86/cpu/ivybridge/sata.c new file +20 -0

+}
+
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
+{
+       unsigned port_map;
+       const char *mode;
+       u16 map = 0;
+
+       /*
+        * Set SATA controller mode early so the resource allocator can
+        * properly assign IO/Memory resources for the controller.
+        */
+       mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
+       if (mode && !strcmp(mode, "ahci"))
+               map = 0x0060;
+       port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+
+       map |= (port_map ^ 0x3f) << 8;
+       pci_write_config16(dev, 0x90, map);
+}

arch/x86/include/asm/arch-ivybridge/bd82x6x.h +2 -0

index e02520c..644755f 100644
@@ -7,6 +7,8 @@
 #ifndef _ASM_ARCH_BD82X6X_H
 #define _ASM_ARCH_BD82X6X_H
 
+void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
+void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_pci_init(pci_dev_t dev);
 int bd82x6x_init_pci_devices(void);
 int bd82x6x_init(void);

arch/x86/include/asm/arch-ivybridge/pch.h +58 -0

index b3ec7c5..21df083 100644
@@ -122,6 +122,64 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 #define LPC_GEN4_DEC           0x90 /* LPC IF Generic Decode Range 4 */
 #define LPC_GENX_DEC(x)                (0x84 + 4 * (x))
 
+/* PCI Configuration Space (D31:F1): IDE */
+#define PCH_IDE_DEV            PCI_BDF(0, 0x1f, 1)
+#define PCH_SATA_DEV           PCI_BDF(0, 0x1f, 2)
+#define PCH_SATA2_DEV          PCI_BDF(0, 0x1f, 5)
+
+#define INTR_LN                        0x3c
+#define IDE_TIM_PRI            0x40    /* IDE timings, primary */
+#define   IDE_DECODE_ENABLE    (1 << 15)
+#define   IDE_SITRE            (1 << 14)
+#define   IDE_ISP_5_CLOCKS     (0 << 12)
+#define   IDE_ISP_4_CLOCKS     (1 << 12)
+#define   IDE_ISP_3_CLOCKS     (2 << 12)
+#define   IDE_RCT_4_CLOCKS     (0 <<  8)
+#define   IDE_RCT_3_CLOCKS     (1 <<  8)
+#define   IDE_RCT_2_CLOCKS     (2 <<  8)
+#define   IDE_RCT_1_CLOCKS     (3 <<  8)
+#define   IDE_DTE1             (1 <<  7)
+#define   IDE_PPE1             (1 <<  6)
+#define   IDE_IE1              (1 <<  5)
+#define   IDE_TIME1            (1 <<  4)
+#define   IDE_DTE0             (1 <<  3)
+#define   IDE_PPE0             (1 <<  2)
+#define   IDE_IE0              (1 <<  1)
+#define   IDE_TIME0            (1 <<  0)
+#define IDE_TIM_SEC            0x42    /* IDE timings, secondary */
+
+#define IDE_SDMA_CNT           0x48    /* Synchronous DMA control */
+#define   IDE_SSDE1            (1 <<  3)
+#define   IDE_SSDE0            (1 <<  2)
+#define   IDE_PSDE1            (1 <<  1)
+#define   IDE_PSDE0            (1 <<  0)
+
+#define IDE_SDMA_TIM           0x4a
+
+#define IDE_CONFIG             0x54    /* IDE I/O Configuration Register */
+#define   SIG_MODE_SEC_NORMAL  (0 << 18)
+#define   SIG_MODE_SEC_TRISTATE        (1 << 18)
+#define   SIG_MODE_SEC_DRIVELOW        (2 << 18)
+#define   SIG_MODE_PRI_NORMAL  (0 << 16)
+#define   SIG_MODE_PRI_TRISTATE        (1 << 16)
+#define   SIG_MODE_PRI_DRIVELOW        (2 << 16)
+#define   FAST_SCB1            (1 << 15)
+#define   FAST_SCB0            (1 << 14)
+#define   FAST_PCB1            (1 << 13)
+#define   FAST_PCB0            (1 << 12)
+#define   SCB1                 (1 <<  3)
+#define   SCB0                 (1 <<  2)
+#define   PCB1                 (1 <<  1)
+#define   PCB0                 (1 <<  0)
+
+#define SATA_SIRI              0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD              0xa4 /* SATA Indexed Register Data */
+#define SATA_SP                        0xd0 /* Scratchpad */
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR      0xea000151
+#define SATA_IOBP_SP1G3IR      0xea000051
+
 /* PCI Configuration Space (D31:F3): SMBus */
 #define PCH_SMBUS_DEV          PCI_BDF(0, 0x1f, 3)
 #define SMB_BASE               0x20

doc/device-tree-bindings/ata/intel-sata.txt new file +26 -0

new file mode 100644
index 0000000..5e4da83
@@ -0,0 +1,26 @@
+Intel Pantherpoint SATA Device Binding
+======================================
+
+The device tree node which describes the operation of the Intel Pantherpoint
+SATA device is as follows:
+
+Required properties :
+- compatible = "intel,pantherpoint-ahci"
+- intel,sata-mode : string, one of:
+     "ahci" : Use AHCI mode (default)
+     "combined" : Use combined IDE + legacy mode
+     "plain-ide" : Use plain IDE mode
+- intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
+    bit 1=enable second port, etc.
+- intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
+- intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
+
+Example
+-------
+
+sata {
+       compatible = "intel,pantherpoint-ahci";
+       intel,sata-mode = "ahci";
+       intel,sata-port-map = <1>;
+       intel,sata-port0-gen3-tx = <0x00880a7f>;
+};

include/fdtdec.h +0 -0

index abfd678..0a0afce 100644

include/fdtdec.h enum fdt_compat_id { · line 123

Quoted 4 lines

include/fdtdec.h +1 -0

@@ -120,6 +120,7 @@ enum fdt_compat_id {
        COMPAT_INTEL_LPC,               /* Intel Low Pin Count I/F */
        COMPAT_INTEL_MICROCODE,         /* Intel microcode update */
        COMPAT_MEMORY_SPD,              /* Memory SPD information */
+       COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */

I have not started to look into the new driver model and the of_control device tree stuff. One questoin that comes just off the top