ls102xa: HYP/non-sec: for ls102xa.

Change for V2:
- All the registers are defined as a struct, here use it.
- Use CONFIG_PEN_ADDR_BIG_ENDIAN instead of CONFIG_SOC_BIG_ENDIAN.

Xiubo Li (4):
ARM: HYP/non-sec: add the pen address byte reverting support.
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
ls102xa: HYP/non-sec: support for ls102xa boards
ARM: ls102xa: allow all the peripheral access permissions as R/W.

 arch/arm/cpu/armv7/ls102xa/cpu.c                  |  16 +++
 arch/arm/cpu/armv7/nonsec_virt.S                  |   7 +-
 arch/arm/include/asm/arch-ls102xa/config.h        |   3 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |   3 +
 arch/arm/include/asm/arch-ls102xa/ns_access.h     | 118 ++++++++++++++++++++++
 board/freescale/common/Makefile                   |   2 +
 board/freescale/common/ns_access.c                |  32 ++++++
 board/freescale/ls1021aqds/ls1021aqds.c           |  92 +++++++++++++++++
 board/freescale/ls1021atwr/ls1021atwr.c           |  91 +++++++++++++++++
 include/configs/ls1021aqds.h                      |   8 ++
 include/configs/ls1021atwr.h                      |   8 ++
 include/configs/sun7i.h                           |   1 +
 12 files changed, 379 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ns_access.h
 create mode 100644 board/freescale/common/ns_access.c

2.1.0.27.g96db324

For some SoCs, the pen address may has different endianness with the CPUs, so this need the byte revertion for it,

---
 arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
 1 file changed, 3 insertions(+)

index 745670e..1ab5d54 100644
@@ -191,6 +191,9 @@ ENTRY(smp_waitloop)
 	wfi
 	ldr	r1, =CONFIG_SMP_PEN_ADDR	@ load start address
 	ldr	r1, [r1]
+#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
+	rev	r1, r1
+#endif
 	cmp	r0, r1			@ make sure we dont execute this code
 	beq	smp_waitloop		@ again (due to a spurious wakeup)
 	mov	r0, r1

2.1.0.27.g96db324

For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency.

Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here.

---
 arch/arm/cpu/armv7/nonsec_virt.S | 4 ++--
 include/configs/sun7i.h          | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

index 1ab5d54..30d81db 100644
@@ -169,11 +169,11 @@ ENTRY(_nonsec_init)
  * we do this here instead.
  * But first check if we have the generic timer.
  */
-#ifdef CONFIG_SYS_CLK_FREQ
+#ifdef CONFIG_TIMER_CLK_FREQ
 	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
 	and	r0, r0, #CPUID_ARM_GENTIMER_MASK	@ mask arch timer bits
 	cmp	r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
-	ldreq	r1, =CONFIG_SYS_CLK_FREQ
+	ldreq	r1, =CONFIG_TIMER_CLK_FREQ
 	mcreq	p15, 0, r1, c14, c0, 0		@ write CNTFRQ
 #endif
 

index a902b84..6e201f2f 100644
@@ -35,6 +35,7 @@
 #define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_SYS_CLK_FREQ		24000000
+#define CONFIG_SYS_TIMER_CLK_FREQ	CONFIG_SYS_CLK_FREQ
 
 /*
  * Include common sunxi configuration where most the settings are

2.1.0.27.g96db324

Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner.

---
 arch/arm/cpu/armv7/ls102xa/cpu.c                  | 15 +++++++++++++++
 arch/arm/include/asm/arch-ls102xa/config.h        |  2 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  3 +++
 include/configs/ls1021aqds.h                      |  7 +++++++
 include/configs/ls1021atwr.h                      |  7 +++++++
 5 files changed, 34 insertions(+)

index b7dde45..69d1801 100644
@@ -101,3 +101,18 @@ int cpu_eth_init(bd_t *bis)
 
 	return 0;
 }
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Setting the address at which secondary cores start from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	/*
+	 * After setting the secondary cores start address,
+	 * just release them to boot.
+	 */
+	out_be32(&gur->scratchrw[0], addr);
+	out_be32(&gur->brrl, 0x2);
+}
+#endif

index ed78c33..4856388 100644
@@ -11,6 +11,8 @@
 
 #define OCRAM_BASE_ADDR				0x10000000
 #define OCRAM_SIZE				0x00020000
+#define OCRAM_BASE_S_ADDR			0x10010000
+#define OCRAM_S_SIZE				0x00010000
 
 #define CONFIG_SYS_IMMR				0x01000000
 

index 7995fe2..0bac353 100644
@@ -17,6 +17,9 @@
 #define SOC_VER_LS1021		0x11
 #define SOC_VER_LS1022		0x12
 
+#define CCSR_BRR_OFFSET		0xe4
+#define CCSR_SCRATCHRW1_OFFSET	0x200
+
 #define RCWSR0_SYS_PLL_RAT_SHIFT	25
 #define RCWSR0_SYS_PLL_RAT_MASK		0x1f
 #define RCWSR0_MEM_PLL_RAT_SHIFT	16

index 657e3b6..6976cfa 100644
@@ -324,6 +324,13 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_CMD_IMLS
 
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_SMP_PEN_ADDR		0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ		12500000
+#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR
+
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 

index 45b2272..655b39a 100644
@@ -227,6 +227,13 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_CMD_IMLS
 
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_SMP_PEN_ADDR		0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ		12500000
+#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR
+
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 

2.1.0.27.g96db324

The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data.

For now we configure all the peripheral access permissions as R/W.

---
 arch/arm/include/asm/arch-ls102xa/config.h    |   1 +
 arch/arm/include/asm/arch-ls102xa/ns_access.h | 118 ++++++++++++++++++++++++++
 board/freescale/common/Makefile               |   2 +
 board/freescale/common/ns_access.c            |  30 +++++++
 board/freescale/ls1021aqds/ls1021aqds.c       |  92 ++++++++++++++++++++
 board/freescale/ls1021atwr/ls1021atwr.c       |  91 ++++++++++++++++++++
 include/configs/ls1021aqds.h                  |   1 +
 include/configs/ls1021atwr.h                  |   1 +
 8 files changed, 336 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ns_access.h
 create mode 100644 board/freescale/common/ns_access.c

index 4856388..0754296 100644
@@ -18,6 +18,7 @@
 
 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)

index 32b5a3b..7296bbb 100644
@@ -60,4 +60,6 @@ obj-$(CONFIG_P3041DS)	+= p_corenet/
 obj-$(CONFIG_P4080DS)	+= p_corenet/
 obj-$(CONFIG_P5020DS)	+= p_corenet/
 obj-$(CONFIG_P5040DS)	+= p_corenet/
+
+obj-$(CONFIG_LS102XA_NS_ACESS)	+= ns_access.o
 endif

new file mode 100644
index 0000000..d7de982
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ns_access.h>
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+	u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+	u32 *reg;
+	uint32_t val;
+	int i;
+
+	for (i = 0; i < num; i++) {
+		reg = base + ns_dev[i].ind / 2;
+		val = in_be32(reg);
+		if (ns_dev[i].ind % 2 == 0) {
+			val &= 0x0000ffff;
+			val |= ns_dev[i].val << 16;
+		} else {
+			val &= 0xffff0000;
+			val |= ns_dev[i].val;
+		}
+		out_be32(reg, val);
+	}
+}

index 6976cfa..0203dd9 100644
@@ -327,6 +327,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 #define CONFIG_TIMER_CLK_FREQ		12500000
 #define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

index 655b39a..3d3f109 100644
@@ -230,6 +230,7 @@
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 #define CONFIG_TIMER_CLK_FREQ		12500000
 #define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

2.1.0.27.g96db324

Hello York,

I see half this set is delegated to you and half to me. If you just give your Acked-by: to patches 3 and 4, I will handle the whole set.

Amicalement,

Albert.

I will take a closer look tomorrow. Being crazy busy lately.

York

________________________________
From: Albert ARIBAUD
Sent: Wed, 12/11/2014 22:08
To: Sun York-R58495 <[email protected]>
CC: Xiubo Li-B47053 <[email protected]>; Sun York-R58495 <[email protected]>; u-boot at lists.denx.de
Subject: Re: [PATCH v2 4/4] ARM: ls102xa: allow all the peripheral access permissions as R/W.

Hello York,

I see half this set is delegated to you and half to me. If you just give your Acked-by: to patches 3 and 4, I will handle the whole set.

Amicalement,
--
Albert.

Albert,

This set should be marked as superseded.

York

Hello York,

Ok, thanks.

Amicalement,

Albert.