NVIDIA Tegra memory controller and IOMMU support
Subsystems (11)
v7 cover NVIDIA Tegra memory controller and IOMMU support
From: Thierry Reding <[email protected]>
This is the sixth installment in the Tegra IOMMU and memory controller support series. This version addresses the final outstanding comments from Olof about using proper Kconfig symbols to track the dependencies. It also splits up the driver into one part that implements the memory controller only and a second part that implements the SMMU. This plays nicely with the new Kconfig options introduced.
Patch 1 is a preparatory patch that exposes the memory controller clock.
Patches 2 and 3 is a pair of precursory patches needed to make this all work on 64-bit ARM in the future.
The device tree binding for the Tegra memory controller is added in patch 4 and patch 5 is the bulk of the series that move the existing memory controller and IOMMU drivers into the new unified driver that supports Tegra30, Tegra114 and Tegra124.
Patches 6, 7 and 8 add the DT nodes for the memory controller/IOMMU on Tegra30, Tegra114 and Tegra124.
IOMMU support is enabled for the display controllers in patches 9, 10 and
11. This will allow the display controllers to have their memory accesses translated by the SMMU, which will enable non-contiguous buffers to be used for scan-out.
Finally patch 12 also adds support for Tegra132. It is kept separate because none of the other Tegra132 patches have been merged yet, but I've included it here for completeness.
Because the patches are rather intertwined, I'd like to merge them all via the Tegra tree. For that I'll need Acked-bys from Mike, Russell and Joerg on patches 1, 2 and 3, and 5, respectively.
Thierry
Thierry Reding (12):
clk: tegra: Implement memory-controller clock
amba: Add Kconfig file
ARM: tegra: Move AHB Kconfig to drivers/amba
of: Add NVIDIA Tegra memory controller binding
memory: Add NVIDIA Tegra memory controller support
ARM: tegra: Add memory controller support for Tegra30
ARM: tegra: Add memory controller support for Tegra114
ARM: tegra: Add memory controller support for Tegra124
ARM: tegra: Enable IOMMU for display controllers on Tegra30
ARM: tegra: Enable IOMMU for display controllers on Tegra114
ARM: tegra: Enable IOMMU for display controllers on Tegra124
memory: tegra: Add Tegra132 support
.../memory-controllers/nvidia,tegra-mc.txt | 36 + arch/arm/Kconfig | 3 - arch/arm/boot/dts/tegra114.dtsi | 23 +- arch/arm/boot/dts/tegra124.dtsi | 16 + arch/arm/boot/dts/tegra30.dtsi | 25 +- arch/arm/mach-tegra/Kconfig | 9 +- arch/arm64/Kconfig | 3 - drivers/Kconfig | 2 + drivers/amba/Kconfig | 14 + drivers/clk/tegra/clk-divider.c | 13 + drivers/clk/tegra/clk-tegra114.c | 7 +- drivers/clk/tegra/clk-tegra124.c | 7 +- drivers/clk/tegra/clk-tegra20.c | 8 +- drivers/clk/tegra/clk-tegra30.c | 7 +- drivers/clk/tegra/clk.h | 2 + drivers/iommu/Kconfig | 12 +- drivers/iommu/tegra-smmu.c | 1601 +++++++------------- drivers/memory/Kconfig | 12 +- drivers/memory/Makefile | 3 +- drivers/memory/tegra/Kconfig | 7 + drivers/memory/tegra/Makefile | 8 + drivers/memory/tegra/mc.c | 304 ++++ drivers/memory/tegra/mc.h | 57 + drivers/memory/tegra/tegra114.c | 948 ++++++++++++ drivers/memory/tegra/tegra124.c | 1028 +++++++++++++ drivers/memory/tegra/tegra30.c | 970 ++++++++++++ drivers/memory/tegra30-mc.c | 377 ----- include/dt-bindings/clock/tegra114-car.h | 2 +- include/dt-bindings/clock/tegra124-car.h | 2 +- include/dt-bindings/clock/tegra20-car.h | 2 +- include/dt-bindings/memory/tegra114-mc.h | 25 + include/dt-bindings/memory/tegra124-mc.h | 31 + include/dt-bindings/memory/tegra30-mc.h | 24 + include/soc/tegra/mc.h | 107 ++ 34 files changed, 4170 insertions(+), 1525 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt create mode 100644 drivers/amba/Kconfig create mode 100644 drivers/memory/tegra/Kconfig create mode 100644 drivers/memory/tegra/Makefile create mode 100644 drivers/memory/tegra/mc.c create mode 100644 drivers/memory/tegra/mc.h create mode 100644 drivers/memory/tegra/tegra114.c create mode 100644 drivers/memory/tegra/tegra124.c create mode 100644 drivers/memory/tegra/tegra30.c delete mode 100644 drivers/memory/tegra30-mc.c create mode 100644 include/dt-bindings/memory/tegra114-mc.h create mode 100644 include/dt-bindings/memory/tegra124-mc.h create mode 100644 include/dt-bindings/memory/tegra30-mc.h create mode 100644 include/soc/tegra/mc.h
Signature · 1 line
2.1.3
PATCH v7 1/12 clk: tegra: Implement memory-controller clock
From: Thierry Reding <[email protected]>
The memory controller clock runs either at half or the same frequency as the EMC clock.
---
Mike, as I said in the cover letter there are tight dependencies between the patches in this series, so I'd like to get your Acked-by on this one so I can take it through the Tegra tree along with the others.
Thanks,
Thierry
Changes in v4:
- use name and parent name parameters passed in when registering clock
Changes in v3:
- split registration into a separate function that can be reused for all SoC generations, but pass in the name and parent parameters for clarity as well as the register address (in case it ever changes) and the EMC spin-lock since it isn't globally available
drivers/clk/tegra/clk-divider.c | 13 +++++++++++++ drivers/clk/tegra/clk-tegra114.c | 7 ++++++- drivers/clk/tegra/clk-tegra124.c | 7 ++++++- drivers/clk/tegra/clk-tegra20.c | 8 +++++++- drivers/clk/tegra/clk-tegra30.c | 7 ++++++- drivers/clk/tegra/clk.h | 2 ++ include/dt-bindings/clock/tegra114-car.h | 2 +- include/dt-bindings/clock/tegra124-car.h | 2 +- include/dt-bindings/clock/tegra20-car.h | 2 +- 9 files changed, 43 insertions(+), 7 deletions(-)
drivers/clk/tegra/clk-divider.c +13 -0
@@ -185,3 +185,16 @@ struct clk *tegra_clk_register_divider(const char *name,return clk; } + +static const struct clk_div_table mc_div_table[] = { + { .val =0 , .div =2 }, + { .val =1 , .div =1 }, + { .val =0 , .div =0 }, +}; + +struct clk *tegra_clk_register_mc (const char *name,const char *parent_name, +void __iomem *reg,spinlock_t *lock) +{ +return clk_register_divider_table (NULL , name, parent_name,0 , reg, +16 ,1 ,0 , mc_div_table, lock); +}
drivers/clk/tegra/clk-tegra114.c +6 -1
@@ -173,6 +173,7 @@ static DEFINE_SPINLOCK(pll_d_lock);static DEFINE_SPINLOCK (pll_d2_lock);static DEFINE_SPINLOCK (pll_u_lock);static DEFINE_SPINLOCK (pll_re_lock); +static DEFINE_SPINLOCK (emc_lock);static struct div_nmp pllxc_nmp = { .divm_shift =0 ,
@@ -1228,7 +1229,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,ARRAY_SIZE (mux_pllmcp_clkm),CLK_SET_RATE_NO_REPARENT , clk_base +CLK_SOURCE_EMC , - 29, 3, 0, NULL); + 29, 3, 0, &emc_lock); + + clk =tegra_clk_register_mc ("mc" ,"emc_mux" , clk_base +CLK_SOURCE_EMC , + &emc_lock); + clks[TEGRA114_CLK_MC ] = clk;for (i =0 ; i <ARRAY_SIZE (tegra_periph_clk_list); i++) { data = &tegra_periph_clk_list[i];
drivers/clk/tegra/clk-tegra124.c +6 -1
@@ -132,6 +132,7 @@ static DEFINE_SPINLOCK(pll_d2_lock);static DEFINE_SPINLOCK (pll_e_lock);static DEFINE_SPINLOCK (pll_re_lock);static DEFINE_SPINLOCK (pll_u_lock); +static DEFINE_SPINLOCK (emc_lock);/* possible OSC frequencies in Hz */ static unsigned long tegra124_input_freq[] = {
@@ -1127,7 +1128,11 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, clk =clk_register_mux (NULL ,"emc_mux" , mux_pllmcp_clkm,ARRAY_SIZE (mux_pllmcp_clkm),0 , clk_base +CLK_SOURCE_EMC , -29 ,3 ,0 ,NULL ); +29 ,3 ,0 , &emc_lock); + + clk =tegra_clk_register_mc ("mc" ,"emc_mux" , clk_base +CLK_SOURCE_EMC , + &emc_lock); + clks[TEGRA124_CLK_MC ] = clk;/* cml0 */ clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
drivers/clk/tegra/clk-tegra20.c +7 -1
@@ -140,6 +140,8 @@ static struct cpu_clk_suspend_context {static void __iomem *clk_base;static void __iomem *pmc_base; +static DEFINE_SPINLOCK (emc_lock); +#define TEGRA_INIT_DATA_MUX (_name, _parents, _offset, \ _clk_num, _gate_flags, _clk_id) \ TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
@@ -819,11 +821,15 @@ static void __init tegra20_periph_clk_init(void)ARRAY_SIZE (mux_pllmcp_clkm),CLK_SET_RATE_NO_REPARENT , clk_base +CLK_SOURCE_EMC , - 30, 2, 0, NULL); + 30, 2, 0, &emc_lock); clk =tegra_clk_register_periph_gate ("emc" ,"emc_mux" ,0 , clk_base,0 ,57 , periph_clk_enb_refcnt); clks[TEGRA20_CLK_EMC ] = clk; + clk =tegra_clk_register_mc ("mc" ,"emc_mux" , clk_base +CLK_SOURCE_EMC , + &emc_lock); + clks[TEGRA20_CLK_MC ] = clk; +/* dsi */ clk =tegra_clk_register_periph_gate ("dsi" ,"pll_d" ,0 , clk_base,0 ,48 , periph_clk_enb_refcnt);
drivers/clk/tegra/clk-tegra30.c +6 -1
@@ -177,6 +177,7 @@ static unsigned long input_freq;static DEFINE_SPINLOCK (cml_lock);static DEFINE_SPINLOCK (pll_d_lock); +static DEFINE_SPINLOCK (emc_lock);#define TEGRA_INIT_DATA_MUX (_name, _parents, _offset, \ _clk_num, _gate_flags, _clk_id) \
@@ -1157,11 +1158,15 @@ static void __init tegra30_periph_clk_init(void)ARRAY_SIZE (mux_pllmcp_clkm),CLK_SET_RATE_NO_REPARENT , clk_base +CLK_SOURCE_EMC , - 30, 2, 0, NULL); + 30, 2, 0, &emc_lock); clk =tegra_clk_register_periph_gate ("emc" ,"emc_mux" ,0 , clk_base,0 ,57 , periph_clk_enb_refcnt); clks[TEGRA30_CLK_EMC ] = clk; + clk =tegra_clk_register_mc ("mc" ,"emc_mux" , clk_base +CLK_SOURCE_EMC , + &emc_lock); + clks[TEGRA30_CLK_MC ] = clk; +/* cml0 */ clk =clk_register_gate (NULL ,"cml0" ,"pll_e" ,0 , clk_base +PLLE_AUX ,0 ,0 , &cml_lock);
drivers/clk/tegra/clk.h +2 -0
@@ -86,6 +86,8 @@ struct clk *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock); +struct clk *tegra_clk_register_mc (const char *name,const char *parent_name, +void __iomem *reg,spinlock_t *lock);/* * Tegra PLL:
include/dt-bindings/clock/tegra114-car.h +1 -1
@@ -49,7 +49,7 @@#define TEGRA114_CLK_I2S0 30/* 31 */ -/* 32 */ +#define TEGRA114_CLK_MC 32/* 33 */ #define TEGRA114_CLK_APBDMA 34/* 35 */
include/dt-bindings/clock/tegra124-car.h +1 -1
@@ -48,7 +48,7 @@#define TEGRA124_CLK_I2S0 30/* 31 */ -/* 32 */ +#define TEGRA124_CLK_MC 32/* 33 */ #define TEGRA124_CLK_APBDMA 34/* 35 */
include/dt-bindings/clock/tegra20-car.h +1 -1
@@ -49,7 +49,7 @@/* 30 */ #define TEGRA20_CLK_CACHE2 31 -#define TEGRA20_CLK_MEM 32 +#define TEGRA20_CLK_MC 32#define TEGRA20_CLK_AHBDMA 33#define TEGRA20_CLK_APBDMA 34/* 35 */
Signature · 1 line
2.1.3
PATCH v7 1/12 clk: tegra: Implement memory-controller clock
Quoting Thierry Reding (2014-11-13 01:32:26)
Quoted 11 lines
From: Thierry Reding <[email protected]>
The memory controller clock runs either at half or the same frequency as the EMC clock.
Reviewed-by Tomeu Vizoso <[email protected]>Signed-off-by Thierry Reding <[email protected]>---
Mike, as I said in the cover letter there are tight dependencies between the patches in this series, so I'd like to get your Acked-by on this one so I can take it through the Tegra tree along with the others.
Quoted 209 lines
Thanks,
ThierryChanges in v4:
- use name and parent name parameters passed in when registering clockChanges in v3:
- split registration into a separate function that can be reused for all SoC generations, but pass in the name and parent parameters for clarity as well as the register address (in case it ever changes) and the EMC spin-lock since it isn't globally availabledrivers/clk/tegra/clk-divider.c | 13 +++++++++++++ drivers/clk/tegra/clk-tegra114.c | 7 ++++++- drivers/clk/tegra/clk-tegra124.c | 7 ++++++- drivers/clk/tegra/clk-tegra20.c | 8 +++++++- drivers/clk/tegra/clk-tegra30.c | 7 ++++++- drivers/clk/tegra/clk.h | 2 ++ include/dt-bindings/clock/tegra114-car.h | 2 +- include/dt-bindings/clock/tegra124-car.h | 2 +- include/dt-bindings/clock/tegra20-car.h | 2 +- 9 files changed, 43 insertions(+), 7 deletions(-)drivers/clk/tegra/clk-divider.c +13
-0@@ -185,3 +185,16 @@ struct clk *tegra_clk_register_divider(const char *name,return clk; } + +static const struct clk_div_table mc_div_table[] = { + { .val =0 , .div =2 }, + { .val =1 , .div =1 }, + { .val =0 , .div =0 }, +}; + +struct clk *tegra_clk_register_mc (const char *name,const char *parent_name, +void __iomem *reg,spinlock_t *lock) +{ +return clk_register_divider_table (NULL , name, parent_name,0 , reg, +16 ,1 ,0 , mc_div_table, lock); +}drivers/clk/tegra/clk-tegra114.c +6
-1@@ -173,6 +173,7 @@ static DEFINE_SPINLOCK(pll_d_lock);static DEFINE_SPINLOCK (pll_d2_lock);static DEFINE_SPINLOCK (pll_u_lock);static DEFINE_SPINLOCK (pll_re_lock); +static DEFINE_SPINLOCK (emc_lock);static struct div_nmp pllxc_nmp = { .divm_shift =0 ,@@ -1228,7 +1229,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,ARRAY_SIZE (mux_pllmcp_clkm),CLK_SET_RATE_NO_REPARENT , clk_base +CLK_SOURCE_EMC , - 29, 3, 0, NULL); + 29, 3, 0, &emc_lock); + + clk =tegra_clk_register_mc ("mc" ,"emc_mux" , clk_base +CLK_SOURCE_EMC , + &emc_lock); + clks[TEGRA114_CLK_MC ] = clk;for (i =0 ; i <ARRAY_SIZE (tegra_periph_clk_list); i++) { data = &tegra_periph_clk_list[i];drivers/clk/tegra/clk-tegra124.c +6
-1@@ -132,6 +132,7 @@ static DEFINE_SPINLOCK(pll_d2_lock);static DEFINE_SPINLOCK (pll_e_lock);static DEFINE_SPINLOCK (pll_re_lock);static DEFINE_SPINLOCK (pll_u_lock); +static DEFINE_SPINLOCK (emc_lock);/* possible OSC frequencies in Hz */ static unsigned long tegra124_input_freq[] = {@@ -1127,7 +1128,11 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, clk =clk_register_mux (NULL ,"emc_mux" , mux_pllmcp_clkm,ARRAY_SIZE (mux_pllmcp_clkm),0 , clk_base +CLK_SOURCE_EMC , -29 ,3 ,0 ,NULL ); +29 ,3 ,0 , &emc_lock); + + clk =tegra_clk_register_mc ("mc" ,"emc_mux" , clk_base +CLK_SOURCE_EMC , + &emc_lock); + clks[TEGRA124_CLK_MC ] = clk;/* cml0 */ clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,drivers/clk/tegra/clk-tegra20.c +7
-1@@ -140,6 +140,8 @@ static struct cpu_clk_suspend_context {static void __iomem *clk_base;static void __iomem *pmc_base; +static DEFINE_SPINLOCK (emc_lock); +#define TEGRA_INIT_DATA_MUX (_name, _parents, _offset, \ _clk_num, _gate_flags, _clk_id) \ TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \@@ -819,11 +821,15 @@ static void __init tegra20_periph_clk_init(void)ARRAY_SIZE (mux_pllmcp_clkm),CLK_SET_RATE_NO_REPARENT , clk_base +CLK_SOURCE_EMC , - 30, 2, 0, NULL); + 30, 2, 0, &emc_lock); clk =tegra_clk_register_periph_gate ("emc" ,"emc_mux" ,0 , clk_base,0 ,57 , periph_clk_enb_refcnt); clks[TEGRA20_CLK_EMC ] = clk; + clk =tegra_clk_register_mc ("mc" ,"emc_mux" , clk_base +CLK_SOURCE_EMC , + &emc_lock); + clks[TEGRA20_CLK_MC ] = clk; +/* dsi */ clk =tegra_clk_register_periph_gate ("dsi" ,"pll_d" ,0 , clk_base,0 ,48 , periph_clk_enb_refcnt);drivers/clk/tegra/clk-tegra30.c +6
-1@@ -177,6 +177,7 @@ static unsigned long input_freq;static DEFINE_SPINLOCK (cml_lock);static DEFINE_SPINLOCK (pll_d_lock); +static DEFINE_SPINLOCK (emc_lock);#define TEGRA_INIT_DATA_MUX (_name, _parents, _offset, \ _clk_num, _gate_flags, _clk_id) \@@ -1157,11 +1158,15 @@ static void __init tegra30_periph_clk_init(void)ARRAY_SIZE (mux_pllmcp_clkm),CLK_SET_RATE_NO_REPARENT , clk_base +CLK_SOURCE_EMC , - 30, 2, 0, NULL); + 30, 2, 0, &emc_lock); clk =tegra_clk_register_periph_gate ("emc" ,"emc_mux" ,0 , clk_base,0 ,57 , periph_clk_enb_refcnt); clks[TEGRA30_CLK_EMC ] = clk; + clk =tegra_clk_register_mc ("mc" ,"emc_mux" , clk_base +CLK_SOURCE_EMC , + &emc_lock); + clks[TEGRA30_CLK_MC ] = clk; +/* cml0 */ clk =clk_register_gate (NULL ,"cml0" ,"pll_e" ,0 , clk_base +PLLE_AUX ,0 ,0 , &cml_lock);drivers/clk/tegra/clk.h +2
-0@@ -86,6 +86,8 @@ struct clk *tegra_clk_register_divider(const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, u8 frac_width, spinlock_t *lock); +struct clk *tegra_clk_register_mc (const char *name,const char *parent_name, +void __iomem *reg,spinlock_t *lock);/* * Tegra PLL: include/dt-bindings/clock/tegra114-car.h +1
-1@@ -49,7 +49,7 @@#define TEGRA114_CLK_I2S0 30/* 31 */ -/* 32 */ +#define TEGRA114_CLK_MC 32/* 33 */ #define TEGRA114_CLK_APBDMA 34/* 35 */ include/dt-bindings/clock/tegra124-car.h +1
-1@@ -48,7 +48,7 @@#define TEGRA124_CLK_I2S0 30/* 31 */ -/* 32 */ +#define TEGRA124_CLK_MC 32/* 33 */ #define TEGRA124_CLK_APBDMA 34/* 35 */ include/dt-bindings/clock/tegra20-car.h +1
-1@@ -49,7 +49,7 @@/* 30 */ #define TEGRA20_CLK_CACHE2 31 -#define TEGRA20_CLK_MEM 32 +#define TEGRA20_CLK_MC 32#define TEGRA20_CLK_AHBDMA 33#define TEGRA20_CLK_APBDMA 34/* 35 */ Signature · 1 line
2.1.3
PATCH v7 1/12 clk: tegra: Implement memory-controller clock
Quoted 6 lines · Mike Turquette
Quoting Thierry Reding (2014-11-13 01:32:26)
Quoted 5 lines
From: Thierry Reding <[email protected]>
The memory controller clock runs either at half or the same frequency as the EMC clock.
Quoted 8 lines
Quoted 6 lines
Reviewed-by Tomeu Vizoso <[email protected]>Signed-off-by Thierry Reding <[email protected]>---
Mike, as I said in the cover letter there are tight dependencies between the patches in this series, so I'd like to get your Acked-by on this one so I can take it through the Tegra tree along with the others.Acked-by Mike Turquette <[email protected]>
Thanks Mike,
Thierry
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PATCH v7 2/12 amba: Add Kconfig file
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
Rather than duplicate the ARM_AMBA Kconfig symbol in both 32-bit and 64-bit ARM architectures, move the common definition to drivers/amba where dependent drivers will be located.
---
Hi Russell, Will, Catalin,
As explained in the cover-letter there are tight dependencies between the patches in this series, so for simplicity I'd like to take this patch through the Tegra tree with your Acked-by.
Thanks,
Thierry
arch/arm/Kconfig | 3 --- arch/arm64/Kconfig | 3 --- drivers/amba/Kconfig | 2 ++ 3 files changed, 2 insertions(+), 6 deletions(-) create mode 100644 drivers/amba/Kconfig
arch/arm/Kconfig +0 -3
@@ -1242,9 +1242,6 @@ source "arch/arm/common/Kconfig" menu "Bus support" -config ARM_AMBA - bool - config ISA bool help
arch/arm64/Kconfig +0 -3
@@ -169,9 +169,6 @@ endmenu menu "Bus support" -config ARM_AMBA - bool - config PCI bool "PCI support" help
drivers/amba/Kconfig new file +2 -0
@@ -0,0 +1,2 @@ +config ARM_AMBA + bool
Signature · 1 line
2.1.3
PATCH v7 3/12 ARM: tegra: Move AHB Kconfig to drivers/amba
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
This will allow the Kconfig option to be shared among 32-bit and 64-bit ARM.
---
Hi Russell,
As explained in the cover-letter there are tight dependencies between the patches in this series, so for simplicity I'd like to take this patch through the Tegra tree with your Acked-by.
Thanks,
Thierry
Changes in v4:
- add precursory patch introducing drivers/amba/Kconfig, rebase on top
Changes in v3:
- select ARM_AMBA from ARCH_TEGRA to enable the TEGRA_AHB driver
arch/arm/mach-tegra/Kconfig | 9 +-------- drivers/Kconfig | 2 ++ drivers/amba/Kconfig | 12 ++++++++++++ 3 files changed, 15 insertions(+), 8 deletions(-)
arch/arm/mach-tegra/Kconfig +1 -8
@@ -2,6 +2,7 @@ menuconfig ARCH_TEGRA bool "NVIDIA Tegra" if ARCH_MULTI_V7 select ARCH_REQUIRE_GPIOLIB select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS + select ARM_AMBA select ARM_GIC select CLKSRC_MMIO select HAVE_ARM_SCU if SMP
@@ -59,12 +60,4 @@ config ARCH_TEGRA_124_SOC Support for NVIDIA Tegra T124 processor family, based on the ARM CortexA15MP CPU -config TEGRA_AHB - bool "Enable AHB driver for NVIDIA Tegra SoCs" - default y - help - Adds AHB configuration functionality for NVIDIA Tegra SoCs, - which controls AHB bus master arbitration and some - performance parameters(priority, prefech size). - endif
drivers/Kconfig +2 -0
@@ -1,5 +1,7 @@ menu "Device Drivers" +source "drivers/amba/Kconfig" + source "drivers/base/Kconfig" source "drivers/bus/Kconfig"
drivers/amba/Kconfig +12 -0
@@ -1,2 +1,14 @@ config ARM_AMBA bool + +if ARM_AMBA + +config TEGRA_AHB + bool "Enable AHB driver for NVIDIA Tegra SoCs" + default y if ARCH_TEGRA + help + Adds AHB configuration functionality for NVIDIA Tegra SoCs, + which controls AHB bus master arbitration and some performance + parameters (priority, prefetch size). + +endif
Signature · 1 line
2.1.3
PATCH v7 4/12 of: Add NVIDIA Tegra memory controller binding
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it.
In addition, the memory controller implements an SMMU (IOMMU) which can translate I/O virtual addresses to physical addresses for clients. This is useful for scatter-gather operation on devices that don't support it natively and for virtualization or process separation.
---
Changes in v3:
- add missing clocks and clock-names properties
- add example
.../memory-controllers/nvidia,tegra-mc.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt new file +36 -0
@@ -0,0 +1,36 @@ +NVIDIA Tegra Memory Controller device tree bindings +=================================================== + +Required properties: +- compatible: Should be "nvidia,tegra<chip>-mc" +- reg: Physical base address and length of the controller's registers. +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - mc: the module's clock input +- interrupts: The interrupt outputs from the controller. +- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines + the SWGROUP of the master. + +This device implements an IOMMU that complies with the generic IOMMU binding. +See ../iommu/iommu.txt for details. + +Example: +-------- + + mc: memory-controller at 0,70019000 { + compatible = "nvidia,tegra124-mc"; + reg = <0x0 0x70019000 0x0 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_MC>; + clock-names = "mc"; + + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + + #iommu-cells = <1>; + }; + + sdhci at 0,700b0000 { + compatible = "nvidia,tegra124-sdhci"; + ... + iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; + };
Signature · 1 line
2.1.3
A message that is not in the archive (sent off-list or not yet received): 1415871157-21968-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
PATCH v7 5/12 memory: Add NVIDIA Tegra memory controller support
From: Thierry Reding <[email protected]>
The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it.
Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements.
This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead.
---
Hi Joerg,
As I mentioned in the cover-letter, I would like to take this whole series through the Tegra tree to simplify dependency handling. Can I have your Acked-by on this patch?
Thanks,
Thierry
Changes in v7:
- move SMMU code back to drivers/iommu as requested by Joerg
Changes in v6:
- add Kconfig options so that dependencies can be properly encoded
- split memory-controller and SMMU code into separate files
- move num_address_bits field from SMMU to MC structure
Changes in v5:
- remove unused tegra_mc_set_bandwidth() function
- split Tegra132 support into a separate patch
- use correct register for GPU SWGROUP
- fix build failures on 64-bit
Changes in v4:
- remove DMA/IOMMU integration glue
- don't initialize linear SMMU mapping
- fail attachment for non-masters
- free empty page tables
Changes in v3:
- drop changes related to probe ordering that were rejected
- remove old SMMU driver
drivers/iommu/Kconfig | 12 +- drivers/iommu/tegra-smmu.c | 1601 ++++++++++-------------------- drivers/memory/Kconfig | 12 +- drivers/memory/Makefile | 3 +- drivers/memory/tegra/Kconfig | 7 + drivers/memory/tegra/Makefile | 7 + drivers/memory/tegra/mc.c | 301 ++++++ drivers/memory/tegra/mc.h | 53 + drivers/memory/tegra/tegra114.c | 948 ++++++++++++++++++ drivers/memory/tegra/tegra124.c | 995 +++++++++++++++++++ drivers/memory/tegra/tegra30.c | 970 ++++++++++++++++++ drivers/memory/tegra30-mc.c | 377 ------- include/dt-bindings/memory/tegra114-mc.h | 25 + include/dt-bindings/memory/tegra124-mc.h | 31 + include/dt-bindings/memory/tegra30-mc.h | 24 + include/soc/tegra/mc.h | 107 ++ 16 files changed, 3992 insertions(+), 1481 deletions(-) create mode 100644 drivers/memory/tegra/Kconfig create mode 100644 drivers/memory/tegra/Makefile create mode 100644 drivers/memory/tegra/mc.c create mode 100644 drivers/memory/tegra/mc.h create mode 100644 drivers/memory/tegra/tegra114.c create mode 100644 drivers/memory/tegra/tegra124.c create mode 100644 drivers/memory/tegra/tegra30.c delete mode 100644 drivers/memory/tegra30-mc.c create mode 100644 include/dt-bindings/memory/tegra114-mc.h create mode 100644 include/dt-bindings/memory/tegra124-mc.h create mode 100644 include/dt-bindings/memory/tegra30-mc.h create mode 100644 include/soc/tegra/mc.h
drivers/iommu/Kconfig +6 -6
@@ -176,14 +176,14 @@ config TEGRA_IOMMU_GART hardware included on Tegra SoCs. config TEGRA_IOMMU_SMMU - bool "Tegra SMMU IOMMU Support" - depends on ARCH_TEGRA && TEGRA_AHB + bool "NVIDIA Tegra SMMU Support" + depends on ARCH_TEGRA + depends on TEGRA_AHB + depends on TEGRA_MC select IOMMU_API help - Enables support for remapping discontiguous physical memory - shared with the operating system into contiguous I/O virtual - space through the SMMU (System Memory Management Unit) - hardware included on Tegra SoCs. + This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra + SoCs (Tegra30 up to Tegra124). config EXYNOS_IOMMU bool "Exynos IOMMU Support"
drivers/iommu/tegra-smmu.c +514 -1087
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drivers/memory/Kconfig +2 -10
@@ -61,16 +61,6 @@ config TEGRA20_MC analysis, especially for IOMMU/GART(Graphics Address Relocation Table) module. -config TEGRA30_MC - bool "Tegra30 Memory Controller(MC) driver" - default y - depends on ARCH_TEGRA_3x_SOC - help - This driver is for the Memory Controller(MC) module available - in Tegra30 SoCs, mainly for a address translation fault - analysis, especially for IOMMU/SMMU(System Memory Management - Unit) module. - config FSL_CORENET_CF tristate "Freescale CoreNet Error Reporting" depends on FSL_SOC_BOOKE
@@ -85,4 +75,6 @@ config FSL_IFC bool depends on FSL_SOC +source "drivers/memory/tegra/Kconfig" + endif
drivers/memory/Makefile +2 -1
@@ -12,4 +12,5 @@ obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o -obj-$(CONFIG_TEGRA30_MC) += tegra30-mc.o + +obj-$(CONFIG_TEGRA_MC) += tegra/
drivers/memory/tegra/Kconfig new file +7 -0
@@ -0,0 +1,7 @@ +config TEGRA_MC + bool "NVIDIA Tegra Memory Controller support" + default y + depends on ARCH_TEGRA + help + This driver supports the Memory Controller (MC) hardware found on + NVIDIA Tegra SoCs.
drivers/memory/tegra/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +tegra-mc-y := mc.o + +tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o +tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o +tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o + +obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
drivers/memory/tegra/mc.c new file +301 -0
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drivers/memory/tegra/mc.h new file +53 -0
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drivers/memory/tegra/tegra114.c new file +948 -0
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drivers/memory/tegra/tegra124.c new file +995 -0
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drivers/memory/tegra/tegra30.c new file +970 -0
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drivers/memory/tegra30-mc.c deleted +0 -377
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include/dt-bindings/memory/tegra114-mc.h new file +25 -0
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include/dt-bindings/memory/tegra124-mc.h new file +31 -0
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include/dt-bindings/memory/tegra30-mc.h new file +24 -0
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include/soc/tegra/mc.h new file +107 -0
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2.1.3
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Joerg Roedel
maintainerPATCH v7 5/12 memory: Add NVIDIA Tegra memory controller support
Quoted 14 lines · Thierry Reding
From: Thierry Reding <[email protected]>
The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it.
Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements.
This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead.
Quoted 7 lines
Signed-off-by Thierry Reding <[email protected]>---
Hi Joerg,As I mentioned in the cover-letter, I would like to take this whole series through the Tegra tree to simplify dependency handling. Can I have your Acked-by on this patch?
Sure!
Quoted 9 lines
drivers/iommu/Kconfig | 12 +- drivers/iommu/tegra-smmu.c | 1601 ++++++++++-------------------- drivers/memory/Kconfig | 12 +- drivers/memory/Makefile | 3 +- drivers/memory/tegra/Kconfig | 7 + drivers/memory/tegra/Makefile | 7 + drivers/memory/tegra/mc.c | 301 ++++++ drivers/memory/tegra/mc.h | 53 + drivers/memory/tegra/tegra114.c | 948 ++++++++++++++++++
Quoted 8 lines
drivers/memory/tegra/tegra124.c | 995 +++++++++++++++++++ drivers/memory/tegra/tegra30.c | 970 ++++++++++++++++++ drivers/memory/tegra30-mc.c | 377 ------- include/dt-bindings/memory/tegra114-mc.h | 25 + include/dt-bindings/memory/tegra124-mc.h | 31 + include/dt-bindings/memory/tegra30-mc.h | 24 + include/soc/tegra/mc.h | 107 ++ 16 files changed, 3992 insertions(+), 1481 deletions(-)
PATCH v7 6/12 ARM: tegra: Add memory controller support for Tegra30
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
Collapses the old memory-controller and IOMMU device tree nodes into a single node to more accurately describe the hardware.
While this is an incompatible change there are no users of the IOMMU on Tegra, even though a driver has existed for some time.
--- arch/arm/boot/dts/tegra30.dtsi | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-)
arch/arm/boot/dts/tegra30.dtsi +6 -14
@@ -615,23 +615,15 @@ clock-names = "pclk", "clk32k_in"; }; - memory-controller at 7000f000 { + mc: memory-controller at 7000f000 { compatible = "nvidia,tegra30-mc"; - reg = <0x7000f000 0x010 - 0x7000f03c 0x1b4 - 0x7000f200 0x028 - 0x7000f284 0x17c>; + reg = <0x7000f000 0x400>; + clocks = <&tegra_car TEGRA30_CLK_MC>; + clock-names = "mc"; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - }; - iommu at 7000f010 { - compatible = "nvidia,tegra30-smmu"; - reg = <0x7000f010 0x02c - 0x7000f1f0 0x010 - 0x7000f228 0x05c>; - nvidia,#asids = <4>; /* # of ASIDs */ - dma-window = <0 0x40000000>; /* IOVA start & length */ - nvidia,ahb = <&ahb>; + #iommu-cells = <1>; }; fuse at 7000f800 {
Signature · 1 line
2.1.3
PATCH v7 7/12 ARM: tegra: Add memory controller support for Tegra114
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
Add the device tree node for the memory controller found on Tegra114 SoCs. The memory controller integrates an IOMMU (called SMMU) as well as various knobs to tweak memory accesses by the various clients.
The old IOMMU device tree node is collapsed into the memory controller node to more accurately describe the hardware. While this change is incompatible, the IOMMU driver has never had any users so the change is not going to cause any breakage.
--- arch/arm/boot/dts/tegra114.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
arch/arm/boot/dts/tegra114.dtsi +9 -9
@@ -498,15 +498,15 @@ reset-names = "fuse"; }; - iommu at 70019010 { - compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; - reg = <0x70019010 0x02c - 0x700191f0 0x010 - 0x70019228 0x074>; - nvidia,#asids = <4>; - dma-window = <0 0x40000000>; - nvidia,swgroups = <0x18659fe>; - nvidia,ahb = <&ahb>; + mc: memory-controller at 70019000 { + compatible = "nvidia,tegra114-mc"; + reg = <0x70019000 0x1000>; + clocks = <&tegra_car TEGRA114_CLK_MC>; + clock-names = "mc"; + + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + + #iommu-cells = <1>; }; ahub at 70080000 {
Signature · 1 line
2.1.3
PATCH v7 8/12 ARM: tegra: Add memory controller support for Tegra124
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
Add the memory controller and wire up the interrupt that is used to report errors. Provide a reference to the memory controller clock and mark the device as being an IOMMU by adding an #iommu-cells property.
--- arch/arm/boot/dts/tegra124.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
arch/arm/boot/dts/tegra124.dtsi +11 -0
@@ -553,6 +553,17 @@ reset-names = "fuse"; }; + mc: memory-controller at 0,70019000 { + compatible = "nvidia,tegra124-mc"; + reg = <0x0 0x70019000 0x0 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_MC>; + clock-names = "mc"; + + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + + #iommu-cells = <1>; + }; + sata at 0,70020000 { compatible = "nvidia,tegra124-ahci";
Signature · 1 line
2.1.3
PATCH v7 9/12 ARM: tegra: Enable IOMMU for display controllers on Tegra30
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
Add iommus properties to the device tree nodes for the two display controllers found on Tegra30. This will allow the display controllers to map physically non-contiguous buffers to I/O virtual contiguous address spaces so that they can be used for scan-out.
--- arch/arm/boot/dts/tegra30.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/boot/dts/tegra30.dtsi +5 -0
@@ -1,5 +1,6 @@ #include <dt-bindings/clock/tegra30-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/memory/tegra30-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -166,6 +167,8 @@ resets = <&tegra_car 27>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,head = <0>; rgb {
@@ -183,6 +186,8 @@ resets = <&tegra_car 26>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,head = <1>; rgb {
Signature · 1 line
2.1.3
PATCH v7 10/12 ARM: tegra: Enable IOMMU for display controllers on Tegra114
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
Add iommus properties to the device tree nodes for the two display controllers found on Tegra114. This will allow the display controllers to map physically non-contiguous buffers to I/O virtual contiguous address spaces so that they can be used for scan-out.
--- arch/arm/boot/dts/tegra114.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/boot/dts/tegra114.dtsi +5 -0
@@ -1,5 +1,6 @@ #include <dt-bindings/clock/tegra114-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/memory/tegra114-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -50,6 +51,8 @@ resets = <&tegra_car 27>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,head = <0>; rgb {
@@ -67,6 +70,8 @@ resets = <&tegra_car 26>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,head = <1>; rgb {
Signature · 1 line
2.1.3
PATCH v7 11/12 ARM: tegra: Enable IOMMU for display controllers on Tegra124
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
Add iommus properties to the device tree nodes for the two display controllers found on Tegra124. This will allow the display controllers to map physically non-contiguous buffers to I/O virtual contiguous address spaces so that they can be used for scan-out.
--- arch/arm/boot/dts/tegra124.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/boot/dts/tegra124.dtsi +5 -0
@@ -1,5 +1,6 @@ #include <dt-bindings/clock/tegra124-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/memory/tegra124-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -103,6 +104,8 @@ resets = <&tegra_car 27>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,head = <0>; };
@@ -116,6 +119,8 @@ resets = <&tegra_car 26>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,head = <1>; };
Signature · 1 line
2.1.3
PATCH v7 12/12 memory: tegra: Add Tegra132 support
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
The memory controller on Tegra132 is very similar to the one found on Tegra124. But the Denver CPUs don't have an outer cache, so dcache maintenance is done slightly differently.
---
Changes in v7:
- update help text
drivers/iommu/Kconfig | 2 +- drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 3 +++ drivers/memory/tegra/mc.h | 4 ++++ drivers/memory/tegra/tegra124.c | 33 +++++++++++++++++++++++++++++++++ 5 files changed, 42 insertions(+), 1 deletion(-)
drivers/iommu/Kconfig +1 -1
@@ -183,7 +183,7 @@ config TEGRA_IOMMU_SMMU select IOMMU_API help This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra - SoCs (Tegra30 up to Tegra124). + SoCs (Tegra30 up to Tegra132). config EXYNOS_IOMMU bool "Exynos IOMMU Support"
drivers/memory/tegra/Makefile +1 -0
@@ -3,5 +3,6 @@ tegra-mc-y := mc.o tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o +tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
drivers/memory/tegra/mc.c +3 -0
@@ -58,6 +58,9 @@ static const struct of_device_id tegra_mc_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_124_SOC { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, #endif +#ifdef CONFIG_ARCH_TEGRA_132_SOC + { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, +#endif { } }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
drivers/memory/tegra/mc.h +4 -0
@@ -50,4 +50,8 @@ extern const struct tegra_mc_soc tegra114_mc_soc;extern const struct tegra_mc_soc tegra124_mc_soc;#endif +#ifdef CONFIG_ARCH_TEGRA_132_SOC +extern const struct tegra_mc_soc tegra132_mc_soc; +#endif +#endif /* MEMORY_TEGRA_MC_H */
drivers/memory/tegra/tegra124.c +33 -0
@@ -993,3 +993,36 @@ const struct tegra_mc_soc tegra124_mc_soc = { .smmu = &tegra124_smmu_soc, };#endif /* CONFIG_ARCH_TEGRA_124_SOC */ + +#ifdef CONFIG_ARCH_TEGRA_132_SOC +static void tegra132_flush_dcache (struct page *page,unsigned long offset, +size_t size) +{ +void *virt =page_address (page) + offset; + +__flush_dcache_area (virt, size); +} + +static const struct tegra_smmu_ops tegra132_smmu_ops = { + .flush_dcache = tegra132_flush_dcache, +}; + +static const struct tegra_smmu_soc tegra132_smmu_soc = { + .clients = tegra124_mc_clients, + .num_clients =ARRAY_SIZE (tegra124_mc_clients), + .swgroups = tegra124_swgroups, + .num_swgroups =ARRAY_SIZE (tegra124_swgroups), + .supports_round_robin_arbitration = true, + .supports_request_limit = true, + .num_asids =128 , + .ops = &tegra132_smmu_ops, +}; + +const struct tegra_mc_soc tegra132_mc_soc = { + .clients = tegra124_mc_clients, + .num_clients =ARRAY_SIZE (tegra124_mc_clients), + .num_address_bits =34 , + .atom_size =32 , + .smmu = &tegra132_smmu_soc, +}; +#endif /* CONFIG_ARCH_TEGRA_132_SOC */
Signature · 1 line
2.1.3
v7 cover NVIDIA Tegra memory controller and IOMMU support
In reply to Thierry RedingQuoted 11 lines · On Thursday 13 November 2014 10:32:25 Thierry Reding wrote:
From: Thierry Reding <[email protected]>
This is the sixth installment in the Tegra IOMMU and memory controller support series. This version addresses the final outstanding comments from Olof about using proper
Kconfigsymbols to track the dependencies. It also splits up the driver into one part that implements the memory controller only and a second part that implements the SMMU. This plays nicely with the newKconfigoptions introduced.Patch 1 is a preparatory patch that exposes the memory controller clock.
Quoted 7 lines
Patches 2 and 3 is a pair of precursory patches needed to make this all work on 64-bit ARM in the future.
The device tree binding for the Tegra memory controller is added in patch 4 and patch 5 is the bulk of the series that move the existing memory controller and IOMMU drivers into the new unified driver that supports Tegra30, Tegra114 and Tegra124.
I just noticed that patch 5 has never made it into my inbox in any of the submissions. Did it get filtered by the mailing list?
Arnd
v7 cover NVIDIA Tegra memory controller and IOMMU support
Quoted 15 lines · Arnd Bergmann
Quoted 14 lines · On Thursday 13 November 2014 10:32:25 Thierry Reding wrote:
From: Thierry Reding <[email protected]>
This is the sixth installment in the Tegra IOMMU and memory controller support series. This version addresses the final outstanding comments from Olof about using proper
Kconfigsymbols to track the dependencies. It also splits up the driver into one part that implements the memory controller only and a second part that implements the SMMU. This plays nicely with the newKconfigoptions introduced.Patch 1 is a preparatory patch that exposes the memory controller clock.
Patches 2 and 3 is a pair of precursory patches needed to make this all work on 64-bit ARM in the future.
Quoted 7 lines
Quoted 4 lines
The device tree binding for the Tegra memory controller is added in patch 4 and patch 5 is the bulk of the series that move the existing memory controller and IOMMU drivers into the new unified driver that supports Tegra30, Tegra114 and Tegra124.
I just noticed that patch 5 has never made it into my inbox in any of the submissions. Did it get filtered by the mailing list?
I have received patch 5 just fine through linux-tegra. The patch is rather long though, so something filtering it wouldn't be that surprising.
Quoted 2 lines
Arnd
Mikko
v7 cover NVIDIA Tegra memory controller and IOMMU support
In reply to Arnd BergmannQuoted 15 lines · Arnd Bergmann
Quoted 14 lines · On Thursday 13 November 2014 10:32:25 Thierry Reding wrote:
From: Thierry Reding <[email protected]>
This is the sixth installment in the Tegra IOMMU and memory controller support series. This version addresses the final outstanding comments from Olof about using proper
Kconfigsymbols to track the dependencies. It also splits up the driver into one part that implements the memory controller only and a second part that implements the SMMU. This plays nicely with the newKconfigoptions introduced.Patch 1 is a preparatory patch that exposes the memory controller clock.
Patches 2 and 3 is a pair of precursory patches needed to make this all work on 64-bit ARM in the future.
Quoted 7 lines
Quoted 4 lines
The device tree binding for the Tegra memory controller is added in patch 4 and patch 5 is the bulk of the series that move the existing memory controller and IOMMU drivers into the new unified driver that supports Tegra30, Tegra114 and Tegra124.
I just noticed that patch 5 has never made it into my inbox in any of the submissions. Did it get filtered by the mailing list?
Yes, linux-arm-kernel says it needs moderator approval. Do you want me to bounce it to you directly?
Thierry
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