arm: socfpga: set skew settings for ethernet phy
PATCH v2 1/1 arm: socfpga: set skew settings for ethernet phy
From: Dinh Nguyen <[email protected]>
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware.
---
v2: Added comments on why it is necessary for setting the skew values.
--- board/altera/socfpga/socfpga_cyclone5.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
board/altera/socfpga/socfpga_cyclone5.c +16 -0
@@ -8,7 +8,9 @@#include <asm/arch/reset_manager.h> #include <asm/io.h> +#include <micrel.h> #include <netdev.h> +#include <phy.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -39,3 +41,17 @@ int board_init(void)return 0 ; } + +int board_phy_config (struct phy_device *phydev) +{ +/* +* These skew settings for the KSZ9021 ethernet phy is required for ethernet +* to work reliably on most flavors of cyclone5 boards. +*/ +ksz9021_phy_extended_write (phydev,MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW , +0x0 ); +ksz9021_phy_extended_write (phydev,MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW , +0x0 ); +ksz9021_phy_extended_write (phydev,MII_KSZ9021_EXT_RGMII_CLOCK_SKEW , +0xf0f0 ); +}
Signature · 1 line
2.0.3
PATCH v2 1/1 arm: socfpga: set skew settings for ethernet phy
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware.
Is it to need similar settings for all ksz9021 phys? Should this go to drivers/ as I suggested with a patch?
Thanks,
Pavel
Quoted 45 lines
Signed-off-by Dinh Nguyen <[email protected]>Cc Vince Bridgers <[email protected]>Cc Pavel Machek <[email protected]>Cc Marek Vasut <[email protected]>Cc Tom Rini <[email protected]>Cc Albert Aribaud <[email protected]>Cc Wolfgang Denk <[email protected]>---
v2: Added comments on why it is necessary for setting the skew values.--- board/altera/socfpga/socfpga_cyclone5.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)board/altera/socfpga/socfpga_cyclone5.c +16
-0@@ -8,7 +8,9 @@#include <asm/arch/reset_manager.h> #include <asm/io.h> +#include <micrel.h> #include <netdev.h> +#include <phy.h> DECLARE_GLOBAL_DATA_PTR ;@@ -39,3 +41,17 @@ int board_init(void)return 0 ; } + +int board_phy_config (struct phy_device *phydev) +{ +/* +* These skew settings for the KSZ9021 ethernet phy is required for ethernet +* to work reliably on most flavors of cyclone5 boards. +*/ +ksz9021_phy_extended_write (phydev,MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW , +0x0 ); +ksz9021_phy_extended_write (phydev,MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW , +0x0 ); +ksz9021_phy_extended_write (phydev,MII_KSZ9021_EXT_RGMII_CLOCK_SKEW , +0xf0f0 ); +}
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH v2 1/1 arm: socfpga: set skew settings for ethernet phy
Quoted 9 lines · Pavel Machek
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware.
Is it to need similar settings for all ksz9021 phys? Should this go to
drivers/as I suggested with a patch?
This is board specific, but with the driver model, this should be moved into the PHY driver and the values should be passed via platform data or DT.
I will apply this now, since it fixes real issue.
Best regards,
Marek Vasut
PATCH v2 1/1 arm: socfpga: set skew settings for ethernet phy
Quoted 7 lines · Marek Vasut
Quoted 6 lines · Pavel Machek
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware.
Quoted 8 lines
Quoted 3 lines
Is it to need similar settings for all ksz9021 phys? Should this go to
drivers/as I suggested with a patch?This is board specific, but with the driver model, this should be moved into the PHY driver and the values should be passed via platform data or DT.
I will apply this now, since it fixes real issue.
Hmm, could you apply the patch I posted, instead? It has configuration in socfpga_config.h -- "platform data".
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH v2 1/1 arm: socfpga: set skew settings for ethernet phy
Quoted 11 lines · Pavel Machek
Quoted 10 lines · Marek Vasut
Quoted 8 lines · Pavel Machek
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware.
Is it to need similar settings for all ksz9021 phys? Should this go to
drivers/as I suggested with a patch?
Quoted 8 lines
Quoted 5 lines
This is board specific, but with the driver model, this should be moved into the PHY driver and the values should be passed via platform data or DT.
I will apply this now, since it fixes real issue.
Hmm, could you apply the patch I posted, instead? It has configuration in
socfpga_config.h-- "platform data".
Hi!
The patch you provided (if we're referring to the same patch, Message-ID:
<20141113120956.GB30779@amd>) breaks every board which uses the Micrel PHY, doesn't it ? The problem for all other boards would be the new CONFIG_* options which are added into the Micrel driver by that patch. Furthermore, the patch doesn't even apply, it was decided that the patch was an RFC, wasn't it ? Please correct me if I'm wrong.
The way forward here would be for you to prepare a patch for the Micrel PHY driver, submit that one (make sure to CC Joe, the network custodian) and in the next step clean up the writes into PHY configuration from both the SoCFPGA CV and from Nitrogen 6x support (I recall I saw the same thing done for that board).
Oh, and btw., the new CONFIG_* options should be documented somewhere, so please keep that in mind. Otherwise, the amount of various CONFIG_* options become an unmanagable mess.
Thanks!
Best regards,
Marek Vasut
PATCH v2 1/1 arm: socfpga: set skew settings for ethernet phy
Quoted 21 lines · Marek Vasut
Quoted 11 lines · Pavel Machek
Quoted 10 lines · Marek Vasut
Quoted 8 lines · Pavel Machek
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware.
Is it to need similar settings for all ksz9021 phys? Should this go to
drivers/as I suggested with a patch?Quoted 8 lines
Quoted 5 lines
This is board specific, but with the driver model, this should be moved into the PHY driver and the values should be passed via platform data or DT.
I will apply this now, since it fixes real issue.
Hmm, could you apply the patch I posted, instead? It has configuration in
socfpga_config.h-- "platform data".
Quoted 8 lines
Hi!
The patch you provided (if we're referring to the same patch, Message-ID:
<20141113120956.GB30779@amd>) breaks every board which uses the Micrel PHY, doesn't it ? The problem for all other boards would be the new CONFIG_* options which are added into the Micrel driver by that patch. Furthermore, the patch doesn't even apply, it was decided that the patch was an RFC, wasn't it ? Please correct me if I'm wrong.
The purpose of that mail was to show that there's better way, so that someone (you) would not apply bandaid when something close to real fix is available.
I overlooked the "breaks compilation" part, but I'm sure it could have been solved with strategicaly placed #ifdef. Notice original patch submission in
PATCH v2 1/1 arm: socfpga: set skew settings for ethernet phy
Quoted 31 lines · Pavel Machek
Quoted 21 lines · Marek Vasut
Quoted 11 lines · Pavel Machek
Quoted 10 lines · Marek Vasut
Quoted 8 lines · Pavel Machek
Quoted 4 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware.
Is it to need similar settings for all ksz9021 phys? Should this go to
drivers/as I suggested with a patch?Quoted 8 lines
Quoted 5 lines
This is board specific, but with the driver model, this should be moved into the PHY driver and the values should be passed via platform data or DT.
I will apply this now, since it fixes real issue.
Hmm, could you apply the patch I posted, instead? It has configuration in
socfpga_config.h-- "platform data".Quoted 8 lines
Hi!
The patch you provided (if we're referring to the same patch, Message-ID:
<20141113120956.GB30779@amd>) breaks every board which uses the Micrel PHY, doesn't it ? The problem for all other boards would be the new CONFIG_* options which are added into the Micrel driver by that patch. Furthermore, the patch doesn't even apply, it was decided that the patch was an RFC, wasn't it ? Please correct me if I'm wrong.
Quoted 3 lines
The purpose of that mail was to show that there's better way, so that someone (you) would not apply bandaid when something close to real fix is available.
I had to pick from two options -- apply a patch which solves a real problem now and which follows approach already implemented for a different board in mainline -- or wait until an RFC patch is done discussing and makes it into mainline.
I decided to solve a real problem now and in case a proper fix/cleanup arrives afterward, I will only be happy about that.
Quoted 4 lines
I overlooked the "breaks compilation" part, but I'm sure it could have been solved with strategicaly placed #ifdef. Notice original patch submission in
Quoted 8 lines
From pavel at denx.de Sat Oct 25 13:27:52 2014
Date: Sat, 25 Oct 2014 13:27:52 +0200
From: Pavel Machek <[email protected]>
Subject: [patch] net: micrel: configure skew values for
Message-ID: <20141025112752.GA19599@amd>it is cleaner then <20141113120956.GB30779@amd> version. I don't think I received any reply there.
Sorry, I missed the new version. I'll comment on it separatelly.
Quoted 2 lines
But the patch you have just merged would interfere with my approach, and makes it unneccessary, so I'll let you solve it.
In fact, the Micrel PHY patch changes only the Micrel driver. This patch changes only the SoCFPGA CV board. They are two completely orthogonal patches.
The Micrel PHY patch can just be followed by a cleanup patch which removes the explicitly PHY setup function from both the MX6 Nitrogen 6x and SoCFPGA boards. I don't see any problem with such cleanup, do you ?
Best regards,
Marek Vasut
Marek Vasut
AppliedPATCH v2 1/1 arm: socfpga: set skew settings for ethernet phy
In reply to dinguyen at opensource.altera.comQuoted 12 lines · dinguyen at opensource.altera.com
From: Dinh Nguyen <[email protected]>
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware.
Signed-off-by Dinh Nguyen <[email protected]>Cc Vince Bridgers <[email protected]>Cc Pavel Machek <[email protected]>Cc Marek Vasut <[email protected]>Cc Tom Rini <[email protected]>Cc Albert Aribaud <[email protected]>Cc Wolfgang Denk <[email protected]>
Quoted 2 lines
---
v2: Added comments on why it is necessary for setting the skew values.
Applied, thanks!
Best regards,
Marek Vasut