clk: sun6i: Unify AHB1 clock and fix rate calculation

Currently sunxi_divs_clk_setup assumes the number of child clocks to be the same as the number of clock-output-names, and a maximum of SUNXI_DIVS_MAX_QTY child clocks.

On sun6i, PLL6 only has 1 child clock, but the parent would be used as well, thereby also having it's own clock-output-names entry. This results in an extra bogus clock being registered.

This patch adds an entry for the number of child clocks alongside the data structures for them.

Signed-off-by Chen-Yu Tsai <[email protected]>

Some clock modules on the A31 use PLL6x2 as one of their inputs. This patch changes the PLL6 implementation for A31 to a divs clock, i.e. clock with multiple outputs that have different dividers. The first output will be the normal PLL6 output, and the second will be PLL6x2.

This patch fixes the PLL6 N factor in the clock driver, and removes any /2 dividers in the PLL6 factors clock part. The N factor counts from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.

Signed-off-by Chen-Yu Tsai <[email protected]>

PLL6 on sun6i has multiple outputs, just like the other sunxi platforms.

Signed-off-by Chen-Yu Tsai <[email protected]>

This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
This patch produces a warning on of_io_request_and_map complaining about dropping the const modifier. I have a separate patch for fixing of_io_request_and_map.

---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +-
 drivers/clk/sunxi/clk-sunxi.c                     | 208 ++++++++++++++++++++++
 2 files changed, 209 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/sunxi.txt +1 -1

index 67b2b99..9dc4f55 100644
@@ -26,7 +26,7 @@ Required properties:
 	"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
 	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
 	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
-	"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
 	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
 	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80

drivers/clk/sunxi/clk-sunxi.c +0 -0

index 5702025..2bb769f 100644

Hi,

Quoted 31 lines · Chen-Yu Tsai

This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
This patch produces a warning on of_io_request_and_map complaining about dropping the const modifier. I have a separate patch for fixing of_io_request_and_map.

---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +-
 drivers/clk/sunxi/clk-sunxi.c                     | 208 ++++++++++++++++++++++
 2 files changed, 209 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/sunxi.txt +1 -1

index 67b2b99..9dc4f55 100644
@@ -26,7 +26,7 @@ Required properties:
      "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
      "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
      "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
-     "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+     "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
      "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
      "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
      "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80

drivers/clk/sunxi/clk-sunxi.c +0 -1

index 5702025..2bb769f 100644
--- a/drivers/clk/sunxi/clk-sunxi.c

drivers/clk/sunxi/clk-sunxi.c line 23

Quoted 6 lines

+++ b/drivers/clk/sunxi/clk-sunxi.c

drivers/clk/sunxi/clk-sunxi.c +1 -0

@@ -20,6 +20,7 @@
 #include <linux/of_address.h>
 #include <linux/reset-controller.h>
 #include <linux/spinlock.h>
+#include <linux/log2.h>

Why is this needed?

drivers/clk/sunxi/clk-sunxi.c static void __init sun9i_init_clocks(struct device_node *node) · line 1240

Quoted 10 lines

drivers/clk/sunxi/clk-sunxi.c +4 -0

 #include "clk-factors.h"
 

@@ -1233,3 +1234,210 @@ static void __init sun9i_init_clocks(struct device_node *node)
      sunxi_init_clocks(NULL, 0);
 }
 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
+
+/**
+ * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
+ */

Why is that added to the A80 clock file ?

Hi,

Quoted 34 lines · Maxime Ripard

Hi,

Quoted 31 lines · Chen-Yu Tsai

This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
This patch produces a warning on of_io_request_and_map complaining about dropping the const modifier. I have a separate patch for fixing of_io_request_and_map.

---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +-
 drivers/clk/sunxi/clk-sunxi.c                     | 208 ++++++++++++++++++++++
 2 files changed, 209 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/sunxi.txt +1 -1

index 67b2b99..9dc4f55 100644
@@ -26,7 +26,7 @@ Required properties:
      "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
      "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
      "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
-     "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+     "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
      "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
      "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
      "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80

drivers/clk/sunxi/clk-sunxi.c +0 -1

index 5702025..2bb769f 100644
--- a/drivers/clk/sunxi/clk-sunxi.c

Quoted 9 lines

drivers/clk/sunxi/clk-sunxi.c line 23

Quoted 6 lines

+++ b/drivers/clk/sunxi/clk-sunxi.c

drivers/clk/sunxi/clk-sunxi.c +1 -0

@@ -20,6 +20,7 @@
 #include <linux/of_address.h>
 #include <linux/reset-controller.h>
 #include <linux/spinlock.h>
+#include <linux/log2.h>

Why is this needed?

For __roundup_pow_of_two.

Quoted 12 lines

drivers/clk/sunxi/clk-sunxi.c static void __init sun9i_init_clocks(struct device_node *node) · line 1240

Quoted 10 lines

drivers/clk/sunxi/clk-sunxi.c +4 -0

 #include "clk-factors.h"
 

@@ -1233,3 +1234,210 @@ static void __init sun9i_init_clocks(struct device_node *node)
      sunxi_init_clocks(NULL, 0);
 }
 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
+
+/**
+ * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
+ */

Why is that added to the A80 clock file ?

This is the clk-sunxi.c file.

Quoted 63 lines · Chen-Yu Tsai

Hi,

Quoted 34 lines · Maxime Ripard

Hi,

Quoted 31 lines · Chen-Yu Tsai

This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
This patch produces a warning on of_io_request_and_map complaining about dropping the const modifier. I have a separate patch for fixing of_io_request_and_map.

---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +-
 drivers/clk/sunxi/clk-sunxi.c                     | 208 ++++++++++++++++++++++
 2 files changed, 209 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/sunxi.txt +1 -1

index 67b2b99..9dc4f55 100644
@@ -26,7 +26,7 @@ Required properties:
      "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
      "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
      "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
-     "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+     "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
      "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
      "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
      "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80

drivers/clk/sunxi/clk-sunxi.c +0 -1

index 5702025..2bb769f 100644
--- a/drivers/clk/sunxi/clk-sunxi.c

Quoted 9 lines

drivers/clk/sunxi/clk-sunxi.c line 23

Quoted 6 lines

+++ b/drivers/clk/sunxi/clk-sunxi.c

drivers/clk/sunxi/clk-sunxi.c +1 -0

@@ -20,6 +20,7 @@
 #include <linux/of_address.h>
 #include <linux/reset-controller.h>
 #include <linux/spinlock.h>
+#include <linux/log2.h>

Why is this needed?

For __roundup_pow_of_two.

Quoted 12 lines

drivers/clk/sunxi/clk-sunxi.c static void __init sun9i_init_clocks(struct device_node *node) · line 1240

Quoted 10 lines

drivers/clk/sunxi/clk-sunxi.c +4 -0

 #include "clk-factors.h"
 

@@ -1233,3 +1234,210 @@ static void __init sun9i_init_clocks(struct device_node *node)
      sunxi_init_clocks(NULL, 0);
 }
 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
+
+/**
+ * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
+ */

Why is that added to the A80 clock file ?

Quoted 1 line

This is the clk-sunxi.c file.

Hmmm, right, this was a brainfart on my side.

This is an odd place to put it though. All the other clocks are defined *before* the clock protection code, and you're defining it after.

Plus, I'd really like to stop introducing new clocks to clk-sunxi.c unless there's some strong reason to do so.

Quoted 64 lines · Maxime Ripard

Quoted 63 lines · Chen-Yu Tsai

Hi,

Quoted 34 lines · Maxime Ripard

Hi,

Quoted 31 lines · Chen-Yu Tsai

This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
This patch produces a warning on of_io_request_and_map complaining about dropping the const modifier. I have a separate patch for fixing of_io_request_and_map.

---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +-
 drivers/clk/sunxi/clk-sunxi.c                     | 208 ++++++++++++++++++++++
 2 files changed, 209 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/sunxi.txt +1 -1

index 67b2b99..9dc4f55 100644
@@ -26,7 +26,7 @@ Required properties:
      "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
      "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
      "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
-     "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+     "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
      "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
      "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
      "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80

drivers/clk/sunxi/clk-sunxi.c +0 -1

index 5702025..2bb769f 100644
--- a/drivers/clk/sunxi/clk-sunxi.c

Quoted 9 lines

drivers/clk/sunxi/clk-sunxi.c line 23

Quoted 6 lines

+++ b/drivers/clk/sunxi/clk-sunxi.c

drivers/clk/sunxi/clk-sunxi.c +1 -0

@@ -20,6 +20,7 @@
 #include <linux/of_address.h>
 #include <linux/reset-controller.h>
 #include <linux/spinlock.h>
+#include <linux/log2.h>

Why is this needed?

For __roundup_pow_of_two.

Quoted 12 lines

drivers/clk/sunxi/clk-sunxi.c static void __init sun9i_init_clocks(struct device_node *node) · line 1240

Quoted 10 lines

drivers/clk/sunxi/clk-sunxi.c +4 -0

 #include "clk-factors.h"
 

@@ -1233,3 +1234,210 @@ static void __init sun9i_init_clocks(struct device_node *node)
      sunxi_init_clocks(NULL, 0);
 }
 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
+
+/**
+ * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
+ */

Why is that added to the A80 clock file ?

Quoted 7 lines

Quoted 1 line

This is the clk-sunxi.c file.

Hmmm, right, this was a brainfart on my side.

This is an odd place to put it though. All the other clocks are defined *before* the clock protection code, and you're defining it after.

I agree it's a bit odd. The driver is pretty much independent of the other code, with the only dependency being it shares a spinlock with the apb1 div clock (same register).

Maybe I should put it at the very top then? Just after the spinlock.