clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT mux
PATCH 1/1 clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT mux
A CLK_MUX_INDEX_BIT mux has one bit per parent, but the sun7i-a20-gmac-clk has 2 bits selecting between 3 possible parents using values of 0, 1, 2, which makes it a regular mux which should not have CLK_MUX_INDEX_BIT set in its flag.
However we do not support parent 1 (an external clock), so use a table to select parent 0 or 2, which are the 2 parents we support.
Note this has not been causing any issues sofar, because we start with a parent setting of parent 0, and only ever re-parent to parent 2 (for which we use an index of 1 as we skip parent 1) and with CLK_MUX_INDEX_BIT set we write a value of 2 for index 1.
Tested on both a cubietruck (which uses rgmii mode) as well as a cs908 (an a31s board which uses mii mode).
--- drivers/clk/sunxi/clk-a20-gmac.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/clk/sunxi/clk-a20-gmac.c +6 -1
@@ -53,6 +53,11 @@ static DEFINE_SPINLOCK(gmac_lock);#define SUN7I_A20_GMAC_MASK 0x3#define SUN7I_A20_GMAC_PARENTS 2 +static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS ] = { +0x00 ,/* Select mii_phy_tx_clk */ +0x02 ,/* Select gmac_int_tx_clk */ +}; +static void __init sun7i_a20_gmac_clk_setup (struct device_node *node) {struct clk *clk;
@@ -90,7 +95,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node) gate->lock = &gmac_lock; mux->reg = reg; mux->mask =SUN7I_A20_GMAC_MASK ; - mux->flags =CLK_MUX_INDEX_BIT ; + mux->table = sun7i_a20_gmac_mux_table; mux->lock = &gmac_lock; clk = clk_register_composite(NULL, clk_name,
Signature · 1 line
2.1.0
Maxime Ripard
AppliedPATCH 1/1 clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT mux
Quoted 13 lines · Hans de Goede
A
CLK_MUX_INDEX_BITmux has one bit per parent, but the sun7i-a20-gmac-clk has 2 bits selecting between 3 possible parents using values of 0, 1, 2, which makes it a regular mux which should not haveCLK_MUX_INDEX_BITset in its flag.However we do not support parent 1 (an external clock), so use a table to select parent 0 or 2, which are the 2 parents we support.
Note this has not been causing any issues sofar, because we start with a parent setting of parent 0, and only ever re-parent to parent 2 (for which we use an index of 1 as we skip parent 1) and with
CLK_MUX_INDEX_BITset we write a value of 2 for index 1.
Quoted 4 lines
Tested on both a cubietruck (which uses rgmii mode) as well as a cs908 (an a31s board which uses mii mode).
Signed-off-by Hans de Goede <[email protected]>
Applied, thanks.
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20141116/52e0c7d9/attachment-0001.sig>
PATCH 1/1 clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT mux
In reply to Hans de GoedeHi,
Quoted 5 lines · Hans de Goede
A
CLK_MUX_INDEX_BITmux has one bit per parent, but the sun7i-a20-gmac-clk has 2 bits selecting between 3 possible parents using values of 0, 1, 2, which makes it a regular mux which should not haveCLK_MUX_INDEX_BITset in its flag.
Quoted 7 lines
However we do not support parent 1 (an external clock), so use a table to select parent 0 or 2, which are the 2 parents we support.
Note this has not been causing any issues sofar, because we start with a parent setting of parent 0, and only ever re-parent to parent 2 (for which we use an index of 1 as we skip parent 1) and with
CLK_MUX_INDEX_BITset we write a value of 2 for index 1.
We never use parent 1, and some hardware doesn't even have it. So back then I went for CLK_MUX_INDEX_BIT to simplify it. Guess it's not the best way to do it.
Quoted 36 lines
Tested on both a cubietruck (which uses rgmii mode) as well as a cs908 (an a31s board which uses mii mode).
Signed-off-by Hans de Goede <[email protected]>--- drivers/clk/sunxi/clk-a20-gmac.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)drivers/clk/sunxi/clk-a20-gmac.c +6
-2@@ -53,6 +53,11 @@ static DEFINE_SPINLOCK(gmac_lock);#define SUN7I_A20_GMAC_MASK 0x3#define SUN7I_A20_GMAC_PARENTS 2 +static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS ] = { +0x00 ,/* Select mii_phy_tx_clk */ +0x02 ,/* Select gmac_int_tx_clk */ +}; +static void __init sun7i_a20_gmac_clk_setup (struct device_node *node) {struct clk *clk;@@ -90,7 +95,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node) gate->lock = &gmac_lock; mux->reg = reg; mux->mask =SUN7I_A20_GMAC_MASK ; - mux->flags =CLK_MUX_INDEX_BIT ; + mux->table = sun7i_a20_gmac_mux_table; mux->lock = &gmac_lock; clk = clk_register_composite(NULL, clk_name, --2.1.0