ARM: shmobile: sh73a0 legacy: Add missing INTCA0 clock

PATCH New Geert Uytterhoeven 3 participants 8 messages Nov 19, 2014 – Nov 28, 2014

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Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +2 more subsystems

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Geert Uytterhoeven

author maintainer

2014-11-19 15:26 UTC #0 lore raw

cover ARM: shmobile: sh73a0 legacy: Add missing INTCA0 clock

Hi Simon, Magnus,

This patch series adds the missing INTCA0 clock on sh73a0 SoCs, for both legacy/reference and multi-platform builds.

The INTCA0 clock drives the irqpin controller modules. Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM.

The first patch can be applied now.
The second patch depends on the series "[PATCH v5 0/6] sh73a0 common clock framework implementation".

Thanks!

Geert Uytterhoeven (2):
ARM: shmobile: sh73a0 legacy: Add missing INTCA0 clock for irqpin
module
ARM: shmobile: sh73a0 dtsi: Add missing INTCA0 clock for irqpin module

 arch/arm/boot/dts/sh73a0.dtsi            | 15 +++++++++++++++
 arch/arm/mach-shmobile/clock-sh73a0.c    | 10 ++++++++++
 include/dt-bindings/clock/sh73a0-clock.h |  3 +++
 3 files changed, 28 insertions(+)

Signature · 12 lines

1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

Geert Uytterhoeven

author maintainer

2014-11-19 15:26 UTC #1 lore raw

PATCH 1/2 ARM: shmobile: sh73a0 legacy/reference: Add missing INTCA0 clock for irqpin module

This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM.

Signed-off-by Geert Uytterhoeven <[email protected]>

---
 arch/arm/mach-shmobile/clock-sh73a0.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

arch/arm/mach-shmobile/clock-sh73a0.c +10 -0

index 6b4c1f313cc987c1..3855fb024fdbb1ca 100644
@@ -553,6 +553,7 @@ enum { MSTP001,
 	MSTP314, MSTP313, MSTP312, MSTP311,
 	MSTP304, MSTP303, MSTP302, MSTP301, MSTP300,
 	MSTP411, MSTP410, MSTP403,
+	MSTP508,
 	MSTP_NR };
 
 #define MSTP(_parent, _reg, _bit, _flags) \

@@ -597,6 +598,7 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
 	[MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
 	[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+	[MSTP508] = MSTP(&div4_clks[DIV4_HP], SMSTPCR5, 8, 0), /* INTCA0 */
 };
 
 /* The lookups structure below includes duplicate entries for some clocks

@@ -677,6 +679,14 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
 	CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */
 	CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+	CLKDEV_DEV_ID("renesas_intc_irqpin.0",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("e6900000.irqpin",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("renesas_intc_irqpin.1",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("e6900004.irqpin",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("renesas_intc_irqpin.2",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("e6900008.irqpin",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("renesas_intc_irqpin.3",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("e690000c.irqpin",	&mstp_clks[MSTP508]), /* INTCA0 */
 
 	/* ICK */
 	CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),

Signature · 1 line

1.9.1

Simon Horman

2014-11-25 02:44 UTC #2 lore raw

PATCH 1/2 ARM: shmobile: sh73a0 legacy/reference: Add missing INTCA0 clock for irqpin module

Quoted 6 lines · Geert Uytterhoeven

This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM.
Signed-off-by Geert Uytterhoeven <[email protected]>

Hi Geert,

should this be considered a fix?

If so could you cook up some text describing which patch introduced this problem in which kernel version.

Quoted 42 lines

---
 arch/arm/mach-shmobile/clock-sh73a0.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

arch/arm/mach-shmobile/clock-sh73a0.c +10 -0

index 6b4c1f313cc987c1..3855fb024fdbb1ca 100644
@@ -553,6 +553,7 @@ enum { MSTP001,
 	MSTP314, MSTP313, MSTP312, MSTP311,
 	MSTP304, MSTP303, MSTP302, MSTP301, MSTP300,
 	MSTP411, MSTP410, MSTP403,
+	MSTP508,
 	MSTP_NR };
 
 #define MSTP(_parent, _reg, _bit, _flags) \

@@ -597,6 +598,7 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
 	[MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
 	[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+	[MSTP508] = MSTP(&div4_clks[DIV4_HP], SMSTPCR5, 8, 0), /* INTCA0 */
 };
 
 /* The lookups structure below includes duplicate entries for some clocks

@@ -677,6 +679,14 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
 	CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */
 	CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+	CLKDEV_DEV_ID("renesas_intc_irqpin.0",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("e6900000.irqpin",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("renesas_intc_irqpin.1",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("e6900004.irqpin",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("renesas_intc_irqpin.2",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("e6900008.irqpin",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("renesas_intc_irqpin.3",	&mstp_clks[MSTP508]), /* INTCA0 */
+	CLKDEV_DEV_ID("e690000c.irqpin",	&mstp_clks[MSTP508]), /* INTCA0 */
 
 	/* ICK */
 	CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),

Signature · 1 line

1.9.1

Geert Uytterhoeven

2014-11-25 09:31 UTC #3 lore raw

PATCH 1/2 ARM: shmobile: sh73a0 legacy/reference: Add missing INTCA0 clock for irqpin module

Hi Simon,

Quoted 11 lines · Simon Horman

Quoted 6 lines · Geert Uytterhoeven
This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM.
Signed-off-by Geert Uytterhoeven <[email protected]>
Hi Geert,
should this be considered a fix?

In some sense this is a fix. But I don't think anyone is suffering from it. Just poor guys like me who disable all MSTP clocks in early boot code, to find more missing clock declarations and more drivers that don't manage their clocks ;-)

Quoted 2 lines

If so could you cook up some text describing which patch introduced this problem in which kernel version.

I guess that would be:

commit 341eb5465f67437ad37ef2f6302b581beda4614a

Author: Magnus Damm <[email protected]>
Date:   Tue Feb 26 12:01:09 2013 +0900

ARM: shmobile: INTC External IRQ pin driver on sh73a0

But I don't think it's worth adding that, or do you plan to backport this to LTSI?

Note that you'd also have to backport the following to make this work:

commit705bc96c2c15313c0677607f6e81800f4d2b4534

Author: Geert Uytterhoeven <[email protected]>
Date:   Fri Sep 12 15:15:18 2014 +0200

irqchip: renesas-intc-irqpin: Add minimal runtime PM support

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Geert Uytterhoeven

2014-11-25 10:16 UTC #4 lore raw

PATCH 1/2 ARM: shmobile: sh73a0 legacy/reference: Add missing INTCA0 clock for irqpin module

Quoted 23 lines · Geert Uytterhoeven

Quoted 11 lines · Simon Horman
Quoted 6 lines · Geert Uytterhoeven
This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM.
Signed-off-by Geert Uytterhoeven <[email protected]>
Hi Geert,
should this be considered a fix?
In some sense this is a fix. But I don't think anyone is suffering from it. Just poor guys like me who disable all MSTP clocks in early boot code, to find more missing clock declarations and more drivers that don't manage their clocks ;-)
Quoted 2 lines
If so could you cook up some text describing which patch introduced this problem in which kernel version.
I guess that would be:

Quoted 8 lines

commit 341eb5465f67437ad37ef2f6302b581beda4614a
Author: Magnus Damm <[email protected]>
Date:   Tue Feb 26 12:01:09 2013 +0900
ARM: shmobile: INTC External IRQ pin driver on sh73a0
But I don't think it's worth adding that, or do you plan to backport this to LTSI?

Seeing the similar fix for r8a7740 has landed in backports, I now assume you will ;-)

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Simon Horman

2014-11-26 01:31 UTC #5 lore raw

PATCH 1/2 ARM: shmobile: sh73a0 legacy/reference: Add missing INTCA0 clock for irqpin module

Quoted 25 lines · Geert Uytterhoeven

Quoted 23 lines · Geert Uytterhoeven
Quoted 11 lines · Simon Horman
Quoted 6 lines · Geert Uytterhoeven
This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM.
Signed-off-by Geert Uytterhoeven <[email protected]>
Hi Geert,
should this be considered a fix?
In some sense this is a fix. But I don't think anyone is suffering from it. Just poor guys like me who disable all MSTP clocks in early boot code, to find more missing clock declarations and more drivers that don't manage their clocks ;-)
Quoted 2 lines
If so could you cook up some text describing which patch introduced this problem in which kernel version.
I guess that would be:

Quoted 8 lines

Quoted 8 lines
commit 341eb5465f67437ad37ef2f6302b581beda4614a
Author: Magnus Damm <[email protected]>
Date:   Tue Feb 26 12:01:09 2013 +0900
ARM: shmobile: INTC External IRQ pin driver on sh73a0
But I don't think it's worth adding that, or do you plan to backport this to LTSI?

Thanks. My main motivation for asking is that Olof asked about some recent patches that looked like fixes. So I am trying to be a bit better at breaking out fixes and documenting them appropriately.

Quoted 2 lines

Seeing the similar fix for r8a7740 has landed in backports, I now assume you will ;-)

Yes, I plan to backport this at some point.

Simon Horman

2014-11-28 00:44 UTC #6 lore raw

PATCH 1/2 ARM: shmobile: sh73a0 legacy/reference: Add missing INTCA0 clock for irqpin module

Hi Geert,

Quoted 35 lines · Simon Horman

Quoted 25 lines · Geert Uytterhoeven
Quoted 23 lines · Geert Uytterhoeven
Quoted 11 lines · Simon Horman
Quoted 6 lines · Geert Uytterhoeven
This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM.
Signed-off-by Geert Uytterhoeven <[email protected]>
Hi Geert,
should this be considered a fix?
In some sense this is a fix. But I don't think anyone is suffering from it. Just poor guys like me who disable all MSTP clocks in early boot code, to find more missing clock declarations and more drivers that don't manage their clocks ;-)
Quoted 2 lines
If so could you cook up some text describing which patch introduced this problem in which kernel version.
I guess that would be:
Quoted 8 lines
Quoted 8 lines
commit 341eb5465f67437ad37ef2f6302b581beda4614a
Author: Magnus Damm <[email protected]>
Date:   Tue Feb 26 12:01:09 2013 +0900
ARM: shmobile: INTC External IRQ pin driver on sh73a0
But I don't think it's worth adding that, or do you plan to backport this to LTSI?

Quoted 8 lines

Thanks. My main motivation for asking is that Olof asked about some recent patches that looked like fixes. So I am trying to be a bit better at breaking out fixes and documenting them appropriately.
Quoted 2 lines
Seeing the similar fix for r8a7740 has landed in backports, I now assume you will ;-)
Yes, I plan to backport this at some point.

Thanks for all your effort with this change.
After all our discussion of fixes I have decided
just to classify it as a regular change and have queued it up for v3.20.

I expect the discussion earlier in this thread will be useful when explaining things to the arm-soc maintainers, so thanks for that material.

Geert Uytterhoeven

author maintainer

2014-11-19 15:27 UTC #7 lore raw

PATCH 2/2 ARM: shmobile: sh73a0 dtsi: Add missing INTCA0 clock for irqpin module

In reply to Geert Uytterhoeven

Signed-off-by Geert Uytterhoeven <[email protected]>

Cc devicetree at vger.kernel.org

---
This depends on the series "[PATCH v5 0/6] sh73a0 common clock framework implementation".

---
 arch/arm/boot/dts/sh73a0.dtsi            | 15 +++++++++++++++
 include/dt-bindings/clock/sh73a0-clock.h |  3 +++
 2 files changed, 18 insertions(+)

arch/arm/boot/dts/sh73a0.dtsi +15 -0

index 0853a6fe2209a48a..c7ab55e55e23f8cb 100644
@@ -78,6 +78,7 @@
 			      0 6 IRQ_TYPE_LEVEL_HIGH
 			      0 7 IRQ_TYPE_LEVEL_HIGH
 			      0 8 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 	};
 
 	irqpin1: irqpin at e6900004 {

@@ -97,6 +98,7 @@
 			      0 14 IRQ_TYPE_LEVEL_HIGH
 			      0 15 IRQ_TYPE_LEVEL_HIGH
 			      0 16 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 		control-parent;
 	};

@@ -117,6 +119,7 @@
 			      0 22 IRQ_TYPE_LEVEL_HIGH
 			      0 23 IRQ_TYPE_LEVEL_HIGH
 			      0 24 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 	};
 
 	irqpin3: irqpin at e690000c {

@@ -136,6 +139,7 @@
 			      0 30 IRQ_TYPE_LEVEL_HIGH
 			      0 31 IRQ_TYPE_LEVEL_HIGH
 			      0 32 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 	};
 
 	i2c0: i2c at e6820000 {

@@ -705,5 +709,16 @@
 			clock-output-names =
 				"iic3", "iic4", "keysc";
 		};
+		mstp5_clks: mstp5_clks at e6150144 {
+			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0xe6150144 4>, <0xe615003c 4>;
+			clocks = <&cpg_clocks SH73A0_CLK_HP>;
+			#clock-cells = <1>;
+			clock-indices = <
+				SH73A0_CLK_INTCA0
+			>;
+			clock-output-names =
+				"intca0";
+		};
 	};
 };

include/dt-bindings/clock/sh73a0-clock.h +3 -0

index 1dd3eb2b7d902afd..53369568c24c5dc6 100644
@@ -76,4 +76,7 @@
 #define SH73A0_CLK_IIC4		10
 #define SH73A0_CLK_KEYSC	3
 
+/* MSTP5 */
+#define SH73A0_CLK_INTCA0	8
+
 #endif

Signature · 1 line

1.9.1