clk: sun6i: Unify AHB1 clock and fix rate calculation

PATCH Superseded Chen-Yu Tsai 2 participants 10 messages Nov 23, 2014 – Nov 25, 2014

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Device tree bindings Common clk Arm/Allwinner sunXi SoC support Arm/Allwinner SoC Clock Support

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Chen-Yu Tsai

author

2014-11-23 04:33 UTC #0 lore raw

v4 cover clk: sun6i: Unify AHB1 clock and fix rate calculation

Hi everyone,

This is v4 of the sun6i AHB1 clock unification series. This series unifies the mux and divider parts of the AHB1 clock found on sun6i and sun8i, while also adding support for the pre-divider on the PLL6 input.

The rate calculation logic must factor in which parent it is using to calculate the rate, to decide whether to use the pre-divider or not. This is beyond the original factors clk design in sunxi. To avoid feature bloat, this is implemented as a seperate composite clk.

The new clock driver is registered with a separate OF_CLK_DECLARE. As it shares its register with the APB1 div clock, thus shares the same spinlock, it cannot reside in a separate file.

This series also fixes up the PLL6 clock. Those patches were merged and are included for completeness.

Changes since v3:

- Moved AHB1 clock driver to the front of clk-sunxi.c

Changes since v2:

- Rebased onto the following patches

clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driver
ARM: dts: sunxi: Use sun4i-a10-apb1-clk for sun6i/sun8i apb2 clocks.
ARM: dts: sunxi: unify APB1 clock
clk: sunxi: unify APB1 clock
ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller

- Dropped

ARM: dts: sun6i: Add required ahb1 clock parent and rates for dma controller

as it is superseded by the re-parent patch from above.

- Expand clock bindings to include output names for PLL6

- Use of_io_request_and_map

- Drop ahb1 rate setting in DTS

- Whitespace and comment style cleanups

Changes since v1:

- Dropped "clk: sunxi: Add post clk divider for factor clocks"

- Added "clk: sunxi: Specify number of child clocks for divs clocks"

- Reworked the PLL6 clock into a divs clock with 2 outputs. This matches the style of PLL6 on the other sunxi platforms.

- Dropped "dmaengine: sun6i: Remove obsolete clk muxing code". Already merged.

The contents of this series are as follows:

Patch 1 makes the number of outputs on divs clocks configurable.

Patch 2 changes PLL6 into a divs clock with 2 outputs, 1 the normal PLL6 and 1 at double the clock rate. This patch also fixes rate calculation error, due to one of the factor values starting from 1, instead of 0.

Patch 3 updates the DT with the new multiple output PLL6.

Patch 4 adds the unified AHB1 clock driver.

Patch 5 and 6 unify the AHB1 clock nodes on sun6i and sun8i respectively.

Cheers
ChenYu

Chen-Yu Tsai (6):
clk: sunxi: Specify number of child clocks for divs clocks
clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
ARM: sun6i: DT: Add PLL6 multiple outputs
clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
ARM: dts: sun6i: Unify ahb1 clock nodes
ARM: dts: sun8i: Unify ahb1 clock nodes

 Documentation/devicetree/bindings/clock/sunxi.txt |  21 +-
 arch/arm/boot/dts/sun6i-a31.dtsi                  |  40 ++--
 arch/arm/boot/dts/sun8i-a23.dtsi                  |  12 +-
 drivers/clk/sunxi/clk-sunxi.c                     | 247 ++++++++++++++++++++--
 4 files changed, 269 insertions(+), 51 deletions(-)

Signature · 1 line

2.1.3

Chen-Yu Tsai

author

2014-11-23 04:33 UTC #1 lore raw

PATCH v4 1/6 clk: sunxi: Specify number of child clocks for divs clocks

Currently sunxi_divs_clk_setup assumes the number of child clocks to be the same as the number of clock-output-names, and a maximum of SUNXI_DIVS_MAX_QTY child clocks.

On sun6i, PLL6 only has 1 child clock, but the parent would be used as well, thereby also having it's own clock-output-names entry. This results in an extra bogus clock being registered.

This patch adds an entry for the number of child clocks alongside the data structures for them.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 drivers/clk/sunxi/clk-sunxi.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

drivers/clk/sunxi/clk-sunxi.c +9 -2

index 46d98e3..d469493 100644
@@ -906,6 +906,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
 
 struct divs_data {
 	const struct factors_data *factors; /* data for the factor clock */
+	int ndivs; /* number of children */
 	struct {
 		u8 fixed; /* is it a fixed divisor? if not... */
 		struct clk_div_table *table; /* is it a table based divisor? */

@@ -925,6 +926,7 @@ static struct clk_div_table pll6_sata_tbl[] = {
 
 static const struct divs_data pll5_divs_data __initconst = {
 	.factors = &sun4i_pll5_data,
+	.ndivs = 2,
 	.div = {
 		{ .shift = 0, .pow = 0, }, /* M, DDR */
 		{ .shift = 16, .pow = 1, }, /* P, other */

@@ -933,6 +935,7 @@ static const struct divs_data pll5_divs_data __initconst = {
 
 static const struct divs_data pll6_divs_data __initconst = {
 	.factors = &sun4i_pll6_data,
+	.ndivs = 2,
 	.div = {
 		{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
 		{ .fixed = 2 }, /* P, other */

@@ -963,7 +966,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 	struct clk_fixed_factor *fix_factor;
 	struct clk_divider *divider;
 	void __iomem *reg;
-	int i = 0;
+	int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
 	int flags, clkflags;
 
 	/* Set up factor clock that we will be dividing */

@@ -986,7 +989,11 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 	 * our RAM clock! */
 	clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
 
-	for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
+	/* if number of children known, use it */
+	if (data->ndivs)
+		ndivs = data->ndivs;
+
+	for (i = 0; i < ndivs; i++) {
 		if (of_property_read_string_index(node, "clock-output-names",
 						  i, &clk_name) != 0)
 			break;

Signature · 1 line

2.1.3

Chen-Yu Tsai

author

2014-11-23 04:33 UTC #2 lore raw

PATCH v4 2/6 clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output

In reply to Chen-Yu Tsai

Some clock modules on the A31 use PLL6x2 as one of their inputs. This patch changes the PLL6 implementation for A31 to a divs clock, i.e. clock with multiple outputs that have different dividers. The first output will be the normal PLL6 output, and the second will be PLL6x2.

This patch fixes the PLL6 N factor in the clock driver, and removes any /2 dividers in the PLL6 factors clock part. The N factor counts from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 Documentation/devicetree/bindings/clock/sunxi.txt | 19 +++++++++++++--
 drivers/clk/sunxi/clk-sunxi.c                     | 28 +++++++++++++----------
 2 files changed, 33 insertions(+), 14 deletions(-)

Documentation/devicetree/bindings/clock/sunxi.txt +17 -2

index d199f91..67b2b99 100644
@@ -71,8 +71,9 @@ Required properties for all clocks:
 	multiplexed clocks, the list order must match the hardware
 	programming order.
 - #clock-cells : from common clock binding; shall be set to 0 except for
-	"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
-	"allwinner,sun4i-pll6-clk" where it shall be set to 1
+	the following compatibles where it shall be set to 1:
+	"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
+	"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
 - clock-output-names : shall be the corresponding names of the outputs.
 	If the clock module only has one output, the name shall be the
 	module name.

@@ -87,6 +88,12 @@ Clock consumers should specify the desired clocks they use with a
 "clocks" phandle cell. Consumers that are using a gated clock should
 provide an additional ID in their clock property. This ID is the
 offset of the bit controlling this particular gate in the register.
+For the other clocks with "#clock-cells" = 1, the additional ID shall
+refer to the index of the output.
+
+For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
+is the normal PLL6 output, or "pll6". The second output is rate doubled
+PLL6, or "pll6x2".
 
 For example:

@@ -114,6 +121,14 @@ pll5: clk at 01c20020 {
 	clock-output-names = "pll5_ddr", "pll5_other";
 };
 
+pll6: clk at 01c20028 {
+	#clock-cells = <1>;
+	compatible = "allwinner,sun6i-a31-pll6-clk";
+	reg = <0x01c20028 0x4>;
+	clocks = <&osc24M>;
+	clock-output-names = "pll6", "pll6x2";
+};
+
 cpu: cpu at 01c20054 {
 	#clock-cells = <0>;
 	compatible = "allwinner,sun4i-a10-cpu-clk";

drivers/clk/sunxi/clk-sunxi.c +16 ~~-12~~

index d469493..5702025 100644
@@ -245,9 +245,9 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
 }
 
 /**
- * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
- * PLL6 rate is calculated as follows
- * rate = parent_rate * n * (k + 1) / 2
+ * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
+ * PLL6x2 rate is calculated as follows
+ * rate = parent_rate * (n + 1) * (k + 1)
  * parent_rate is always 24Mhz
  */

@@ -256,13 +256,7 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
 {
 	u8 div;
 
-	/*
-	 * We always have 24MHz / 2, so we can just say that our
-	 * parent clock is 12MHz.
-	 */
-	parent_rate = parent_rate / 2;
-
-	/* Normalize value to a parent_rate multiple (24M / 2) */
+	/* Normalize value to a parent_rate multiple (24M) */
 	div = *freq / parent_rate;
 	*freq = parent_rate * div;

@@ -274,7 +268,7 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
 	if (*k > 3)
 		*k = 3;
 
-	*n = DIV_ROUND_UP(div, (*k+1));
+	*n = DIV_ROUND_UP(div, (*k+1)) - 1;
 }
 
 /**

@@ -445,6 +439,7 @@ static struct clk_factors_config sun6i_a31_pll6_config = {
 	.nwidth = 5,
 	.kshift = 4,
 	.kwidth = 2,
+	.n_start = 1,
 };
 
 static struct clk_factors_config sun4i_apb1_config = {

@@ -504,6 +499,7 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
 	.enable = 31,
 	.table = &sun6i_a31_pll6_config,
 	.getter = sun6i_a31_get_pll6_factors,
+	.name = "pll6x2",
 };
 
 static const struct factors_data sun4i_apb1_data __initconst = {

@@ -942,6 +938,14 @@ static const struct divs_data pll6_divs_data __initconst = {
 	}
 };
 
+static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
+	.factors = &sun6i_a31_pll6_data,
+	.ndivs = 1,
+	.div = {
+		{ .fixed = 2 }, /* normal output */
+	}
+};
+
 /**
  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
  *

@@ -1082,7 +1086,6 @@ static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 	{.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
 	{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
-	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 	{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
 	{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
 	{}

@@ -1101,6 +1104,7 @@ static const struct of_device_id clk_div_match[] __initconst = {
 static const struct of_device_id clk_divs_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
 	{.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
+	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
 	{}
 };

Signature · 1 line

2.1.3

Chen-Yu Tsai

author

2014-11-23 04:33 UTC #3 lore raw

PATCH v4 3/6 ARM: sun6i: DT: Add PLL6 multiple outputs

In reply to Chen-Yu Tsai

PLL6 on sun6i has multiple outputs, just like the other sunxi platforms.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 arch/arm/boot/dts/sun6i-a31.dtsi | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

arch/arm/boot/dts/sun6i-a31.dtsi +14 ~~-14~~

index a674b0f..f1519a8 100644
@@ -132,11 +132,11 @@
 		};
 
 		pll6: clk at 01c20028 {
-			#clock-cells = <0>;
+			#clock-cells = <1>;
 			compatible = "allwinner,sun6i-a31-pll6-clk";
 			reg = <0x01c20028 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll6";
+			clock-output-names = "pll6", "pll6x2";
 		};
 
 		cpu: cpu at 01c20050 {

@@ -166,7 +166,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 			clock-output-names = "ahb1_mux";
 		};

@@ -221,7 +221,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-apb1-clk";
 			reg = <0x01c20058 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+			clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 			clock-output-names = "apb2";
 		};

@@ -240,7 +240,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6>;
+			clocks = <&osc24M>, <&pll6 0>;
 			clock-output-names = "mmc0";
 		};

@@ -248,7 +248,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6>;
+			clocks = <&osc24M>, <&pll6 0>;
 			clock-output-names = "mmc1";
 		};

@@ -256,7 +256,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6>;
+			clocks = <&osc24M>, <&pll6 0>;
 			clock-output-names = "mmc2";
 		};

@@ -264,7 +264,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c20094 0x4>;
-			clocks = <&osc24M>, <&pll6>;
+			clocks = <&osc24M>, <&pll6 0>;
 			clock-output-names = "mmc3";
 		};

@@ -272,7 +272,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200a0 0x4>;
-			clocks = <&osc24M>, <&pll6>;
+			clocks = <&osc24M>, <&pll6 0>;
 			clock-output-names = "spi0";
 		};

@@ -280,7 +280,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200a4 0x4>;
-			clocks = <&osc24M>, <&pll6>;
+			clocks = <&osc24M>, <&pll6 0>;
 			clock-output-names = "spi1";
 		};

@@ -288,7 +288,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200a8 0x4>;
-			clocks = <&osc24M>, <&pll6>;
+			clocks = <&osc24M>, <&pll6 0>;
 			clock-output-names = "spi2";
 		};

@@ -296,7 +296,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200ac 0x4>;
-			clocks = <&osc24M>, <&pll6>;
+			clocks = <&osc24M>, <&pll6 0>;
 			clock-output-names = "spi3";
 		};

@@ -356,7 +356,7 @@
 
 			/* DMA controller requires AHB1 clocked from PLL6 */
 			assigned-clocks = <&ahb1_mux>;
-			assigned-clock-parents = <&pll6>;
+			assigned-clock-parents = <&pll6 0>;
 		};
 
 		mmc0: mmc at 01c0f000 {

@@ -836,7 +836,7 @@
 			ar100: ar100_clk {
 				compatible = "allwinner,sun6i-a31-ar100-clk";
 				#clock-cells = <0>;
-				clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+				clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 				clock-output-names = "ar100";
 			};

Signature · 1 line

2.1.3

Chen-Yu Tsai

author

2014-11-23 04:33 UTC #4 lore raw

PATCH v4 4/6 clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

In reply to Chen-Yu Tsai

This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +-
 drivers/clk/sunxi/clk-sunxi.c                     | 208 ++++++++++++++++++++++
 2 files changed, 209 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/sunxi.txt +1 -1

index 67b2b99..9dc4f55 100644
@@ -26,7 +26,7 @@ Required properties:
 	"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
 	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
 	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
-	"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
 	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
 	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80

drivers/clk/sunxi/clk-sunxi.c +208 -0

219 lines not on this page · raw message

Signature · 1 line

2.1.3

Chen-Yu Tsai

author

2014-11-23 04:33 UTC #5 lore raw

PATCH v4 5/6 ARM: dts: sun6i: Unify ahb1 clock nodes

In reply to Chen-Yu Tsai

The clock driver has unified support for the ahb1 clock. Unify the clock nodes so it works.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 arch/arm/boot/dts/sun6i-a31.dtsi | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

arch/arm/boot/dts/sun6i-a31.dtsi +3 ~~-11~~

index f1519a8..17d746e 100644
@@ -162,19 +162,11 @@
 			clock-output-names = "axi";
 		};
 
-		ahb1_mux: ahb1_mux at 01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
-			clock-output-names = "ahb1_mux";
-		};
-
 		ahb1: ahb1 at 01c20054 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-ahb-clk";
+			compatible = "allwinner,sun6i-a31-ahb1-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&ahb1_mux>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 			clock-output-names = "ahb1";
 		};

@@ -355,7 +347,7 @@
 			#dma-cells = <1>;
 
 			/* DMA controller requires AHB1 clocked from PLL6 */
-			assigned-clocks = <&ahb1_mux>;
+			assigned-clocks = <&ahb1>;
 			assigned-clock-parents = <&pll6 0>;
 		};

Signature · 1 line

2.1.3

Chen-Yu Tsai

author

2014-11-23 04:33 UTC #6 lore raw

PATCH v4 6/6 ARM: dts: sun8i: Unify ahb1 clock nodes

In reply to Chen-Yu Tsai

The clock driver has unified support for the ahb1 clock. Unify the clock nodes so it works.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 arch/arm/boot/dts/sun8i-a23.dtsi | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

arch/arm/boot/dts/sun8i-a23.dtsi +2 ~~-10~~

index 0746cd1..726b613 100644
@@ -140,19 +140,11 @@
 			clock-output-names = "axi";
 		};
 
-		ahb1_mux: ahb1_mux_clk at 01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
-			clock-output-names = "ahb1_mux";
-		};
-
 		ahb1: ahb1_clk at 01c20054 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-ahb-clk";
+			compatible = "allwinner,sun6i-a31-ahb1-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&ahb1_mux>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 			clock-output-names = "ahb1";
 		};

Signature · 1 line

2.1.3

Maxime Ripard

2014-11-25 15:22 UTC #7 lore raw

v4 cover clk: sun6i: Unify AHB1 clock and fix rate calculation

In reply to Chen-Yu Tsai

Quoted 12 lines · Chen-Yu Tsai

Hi everyone,
This is v4 of the sun6i AHB1 clock unification series. This series unifies the mux and divider parts of the AHB1 clock found on sun6i and sun8i, while also adding support for the pre-divider on the PLL6 input.
The rate calculation logic must factor in which parent it is using to calculate the rate, to decide whether to use the pre-divider or not. This is beyond the original factors clk design in sunxi. To avoid feature bloat, this is implemented as a seperate composite clk.

Quoted 6 lines

The new clock driver is registered with a separate OF_CLK_DECLARE. As it shares its register with the APB1 div clock, thus shares the same spinlock, it cannot reside in a separate file.
This series also fixes up the PLL6 clock. Those patches were merged and are included for completeness.

Please don't do that. Now, I have no idea what should be merged, and what not.

Maxime

Signature · 10 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Chen-Yu Tsai

author

2014-11-25 15:38 UTC #8 lore raw

v4 cover clk: sun6i: Unify AHB1 clock and fix rate calculation

Quoted 17 lines · Maxime Ripard

Quoted 16 lines · Chen-Yu Tsai
Hi everyone,
This is v4 of the sun6i AHB1 clock unification series. This series unifies the mux and divider parts of the AHB1 clock found on sun6i and sun8i, while also adding support for the pre-divider on the PLL6 input.
The rate calculation logic must factor in which parent it is using to calculate the rate, to decide whether to use the pre-divider or not. This is beyond the original factors clk design in sunxi. To avoid feature bloat, this is implemented as a seperate composite clk.
The new clock driver is registered with a separate OF_CLK_DECLARE. As it shares its register with the APB1 div clock, thus shares the same spinlock, it cannot reside in a separate file.

Quoted 5 lines

Quoted 2 lines
This series also fixes up the PLL6 clock. Those patches were merged and are included for completeness.
Please don't do that. Now, I have no idea what should be merged, and what not.

The first 3 have been merged:

clk: sunxi: Specify number of child clocks for divs clocks
clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
ARM: sun6i: DT: Add PLL6 multiple outputs

The latter 3 have not:

clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
ARM: dts: sun6i: Unify ahb1 clock nodes
ARM: dts: sun8i: Unify ahb1 clock nodes

The dts patches should probably be taken through the clock tree, to avoid breaking arm-soc again? But they do depend on the third patch, which you've included in the arm-soc pull request.

I'll resend just the pending patches tomorrow.
Sorry for the confusion.

ChenYu

Maxime Ripard

2014-11-25 22:06 UTC #9 lore raw

v4 cover clk: sun6i: Unify AHB1 clock and fix rate calculation

Quoted 33 lines · Chen-Yu Tsai

Quoted 17 lines · Maxime Ripard
Quoted 16 lines · Chen-Yu Tsai
Hi everyone,
This is v4 of the sun6i AHB1 clock unification series. This series unifies the mux and divider parts of the AHB1 clock found on sun6i and sun8i, while also adding support for the pre-divider on the PLL6 input.
The rate calculation logic must factor in which parent it is using to calculate the rate, to decide whether to use the pre-divider or not. This is beyond the original factors clk design in sunxi. To avoid feature bloat, this is implemented as a seperate composite clk.
The new clock driver is registered with a separate OF_CLK_DECLARE. As it shares its register with the APB1 div clock, thus shares the same spinlock, it cannot reside in a separate file.
Quoted 5 lines
Quoted 2 lines
This series also fixes up the PLL6 clock. Those patches were merged and are included for completeness.
Please don't do that. Now, I have no idea what should be merged, and what not.
The first 3 have been merged:
clk: sunxi: Specify number of child clocks for divs clocks
clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
ARM: sun6i: DT: Add PLL6 multiple outputs
The latter 3 have not:

Quoted 7 lines

clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
ARM: dts: sun6i: Unify ahb1 clock nodes
ARM: dts: sun8i: Unify ahb1 clock nodes
The dts patches should probably be taken through the clock tree, to avoid breaking arm-soc again? But they do depend on the third patch, which you've included in the arm-soc pull request.

Ok, thanks for the clarification.

This will be aimed at 3.20 anyway, so it can go through both the clock or the arm-soc trees, and yeah, I'd lean toward the first given this pull request experience.

Maxime

Signature · 10 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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