cpuidle driver for QCOM SoCs: 8064, 8074, 8084

Follow the scm.c and move scm-boot files to drivers/soc/qcom. The guidance is to clean files out from mach-qcom and move to drivers/soc area.

Signed-off-by Lina Iyer <[email protected]>

Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up warm boot addresses in the Secure Monitor. Extend the SCM flags to support warm boot addresses for secondary cores.

We do not need to export the warmboot flags. Move them into the implementation file.

Signed-off-by Lina Iyer <[email protected]>

---
  drivers/soc/qcom/scm-boot.c | 31 +++++++++++++++++++++++++++++++
  include/soc/qcom/scm-boot.h |  3 +--
  2 files changed, 32 insertions(+), 2 deletions(-)

drivers/soc/qcom/scm-boot.c +17 -0

index 60ff7b4..0871659 100644
@@ -21,6 +21,23 @@
  #include <soc/qcom/scm.h>
  #include <soc/qcom/scm-boot.h>
 
+#define SCM_FLAG_WARMBOOT_CPU0		0x04
+#define SCM_FLAG_WARMBOOT_CPU1		0x02
+#define SCM_FLAG_WARMBOOT_CPU2		0x10
+#define SCM_FLAG_WARMBOOT_CPU3		0x40
+
+struct scm_warmboot {
+	int flag;
+	void *entry;
+};
+
+static struct scm_warmboot scm_flags[] = {
+	{ .flag = SCM_FLAG_WARMBOOT_CPU0 },
+	{ .flag = SCM_FLAG_WARMBOOT_CPU1 },
+	{ .flag = SCM_FLAG_WARMBOOT_CPU2 },
+	{ .flag = SCM_FLAG_WARMBOOT_CPU3 },
+};
+
  /*
   * Set the cold/warm boot address for one of the CPU cores.
   */

drivers/soc/qcom/scm-boot.c +7 -0

+
+	ret = scm_set_boot_addr(virt_to_phys(entry), scm_flags[cpu].flag);
+	if (!ret)
+		scm_flags[cpu].entry  = entry;
+
+	return ret;
+}

include/soc/qcom/scm-boot.h +1 -2

index 6aabb24..529f55a 100644
@@ -16,9 +16,8 @@
  #define SCM_FLAG_COLDBOOT_CPU1		0x01
  #define SCM_FLAG_COLDBOOT_CPU2		0x08
  #define SCM_FLAG_COLDBOOT_CPU3		0x20
-#define SCM_FLAG_WARMBOOT_CPU0		0x04
-#define SCM_FLAG_WARMBOOT_CPU1		0x02
 
  int scm_set_boot_addr(phys_addr_t addr, int flags);
+int scm_set_warm_boot_addr(void *entry, int cpu);
 
  #endif

drivers/soc/qcom/scm-boot.c int scm_set_boot_addr(phys_addr_t addr, int flags) · line 63

Quoted 11 lines · Lina Iyer

drivers/soc/qcom/scm-boot.c +7 -0

@@ -37,3 +54,17 @@ int scm_set_boot_addr(phys_addr_t addr, int flags)
 			&cmd, sizeof(cmd), NULL, 0);
 }
 EXPORT_SYMBOL(scm_set_boot_addr);
+
+int scm_set_warm_boot_addr(void *entry, int cpu)
+{
+	int ret;
+
+	if (entry == scm_flags[cpu].entry)
+		return 0;

Is the entry going to be different at some point? I wonder why we can't just call this function once when the SPM device probes to setup the entry point to cpu_resume()?

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

arch/arm/boot/dts/qcom-msm8974.dtsi +9 -1

@@ -144,7 +148,27 @@
  			};
  		};
 
-		saw_l2: regulator at f9012000 {
+		saw0: power-controller at f9089000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf9089000 0x1000>;
+		};
+
+		saw1: power-controller at f9099000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf9099000 0x1000>;
+		};

arch/arm/boot/dts/qcom-apq8084.dtsi +10 -1

@@ -144,7 +148,27 @@
  			};
  		};
 
-		saw_l2: regulator at f9012000 {
+		saw0: power-controller at f9089000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf9089000 0x1000>;
+		};
+
+		saw1: power-controller at f9099000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf9099000 0x1000>;
+		};
+

Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible binding string to configure SPM registers and allow the SPM to put the core in deeper idle states when the core is idle.

Signed-off-by Lina Iyer <[email protected]>

Add cpuidle driver interface to allow cpus to go into C-States. Use the cpuidle DT interface, common across ARM architectures, to provide the idle state information to the cpuidle framework.

Supported modes at this time are Standby and Standalone Power Collapse.

Signed-off-by Lina Iyer <[email protected]>

drivers/cpuidle/cpuidle-qcom.c new file +7 -0

+	return index;
+}
+
+static int qcom_cpu_spc(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index)
+{
+	lpm_ops->spc(NULL);

Quoted 7 lines · Lina Iyer

Add cpuidle driver interface to allow cpus to go into C-States. Use the cpuidle DT interface, common across ARM architectures, to provide the idle state information to the cpuidle framework.

Supported modes at this time are Standby and Standalone Power Collapse.

Signed-off-by Lina Iyer <[email protected]>

One nit and one comment below. Other than that:

Acked-by Daniel Lezcano <[email protected]>

[ ... ]

drivers/cpuidle/cpuidle-qcom.c line 27

Quoted 4 lines

drivers/cpuidle/cpuidle-qcom.c new file +4 -0

+static int qcom_cpu_stby(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index)
+{
+	lpm_ops->standby(NULL);

In my last comment I was referring about a check for entering successfully the idle state:

	if (lpm_ops->standby(NULL))
		return -1;

drivers/cpuidle/cpuidle-qcom.c line 37

Quoted 9 lines

drivers/cpuidle/cpuidle-qcom.c new file +9 -0

+	return index;
+}
+
+static int qcom_cpu_spc(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index)
+{
+	lpm_ops->spc(NULL);
+
+	return index;

Quoted 26 lines · Daniel Lezcano

Quoted 7 lines · Lina Iyer

Add cpuidle driver interface to allow cpus to go into C-States. Use the cpuidle DT interface, common across ARM architectures, to provide the idle state information to the cpuidle framework.

Supported modes at this time are Standby and Standalone Power Collapse.

Signed-off-by Lina Iyer <[email protected]>

One nit and one comment below. Other than that:

Acked-by Daniel Lezcano <[email protected]>

[ ... ]

drivers/cpuidle/cpuidle-qcom.c line 27

Quoted 4 lines

drivers/cpuidle/cpuidle-qcom.c new file +4 -0

+static int qcom_cpu_stby(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index)
+{
+	lpm_ops->standby(NULL);

In my last comment I was referring about a check for entering successfully the idle state:

	if (lpm_ops->standby(NULL))
		return -1;

Quoted 9 lines

drivers/cpuidle/cpuidle-qcom.c line 37

Quoted 9 lines

drivers/cpuidle/cpuidle-qcom.c new file +9 -0

+	return index;
+}
+
+static int qcom_cpu_spc(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index)
+{
+	lpm_ops->spc(NULL);
+
+	return index;

Similar to Daniel's comment above. if lpm_ops->spc() fails, do you want to fall back to standby.

Hmm, using the DT idle states, it doesn't look as straight forward as it used to be to fall back to a "safe state."

Add cpuidle driver interface to allow cpus to go into C-States. Use the

cpuidle DT interface, common across ARM architectures, to provide the idle state information to the cpuidle framework.

Supported modes at this time are Standby and Standalone Power Collapse.

Signed-off-by Lina Iyer <[email protected]>

---
 .../bindings/arm/msm/qcom,idle-state.txt           | 81 ++++++++++++++++++++++
 drivers/cpuidle/Kconfig.arm                        |  7 ++
 drivers/cpuidle/Makefile                           |  1 +
 drivers/cpuidle/cpuidle-qcom.c                     | 72 +++++++++++++++++++
 4 files changed, 161 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
 create mode 100644 drivers/cpuidle/cpuidle-qcom.c

Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt new file +81 -0

new file mode 100644
index 0000000..ae1b07f
@@ -0,0 +1,81 @@
+QCOM Idle States for cpuidle driver
+
+ARM provides idle-state node to define the cpuidle states, as defined in [1].
+cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
+states. Idle states have different enter/exit latency and residency values.
+The idle states supported by the QCOM SoC are defined as -
+
+    * Standby
+    * Retention
+    * Standalone Power Collapse (Standalone PC or SPC)
+    * Power Collapse (PC)
+
+Standby: Standby does a little more in addition to architectural clock gating.
+When the WFI instruction is executed the ARM core would gate its internal
+clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
+trigger to execute the SPM state machine. The SPM state machine waits for the
+interrupt to trigger the core back in to active. This triggers the cache
+hierarchy to enter standby states, when all cpus are idle. An interrupt brings
+the SPM state machine out of its wait, the next step is to ensure that the
+cache hierarchy is also out of standby, and then the cpu is allowed to resume
+execution.
+
+Retention: Retention is a low power state where the core is clock gated and
+the memory and the registers associated with the core are retained. The
+voltage may be reduced to the minimum value needed to keep the processor
+registers active. The SPM should be configured to execute the retention
+sequence and would wait for interrupt, before restoring the cpu to execution
+state. Retention may have a slightly higher latency than Standby.
+
+Standalone PC: A cpu can power down and warmboot if there is a sufficient time
+between the time it enters idle and the next known wake up. SPC mode is used
+to indicate a core entering a power down state without consulting any other
+cpu or the system resources. This helps save power only on that core.  The SPM
+sequence for this idle state is programmed to power down the supply to the
+core, wait for the interrupt, restore power to the core, and ensure the
+system state including cache hierarchy is ready before allowing core to
+resume. Applying power and resetting the core causes the core to warmboot
+back into Elevation Level (EL) which trampolines the control back to the
+kernel. Entering a power down state for the cpu, needs to be done by trapping
+into a EL. Failing to do so, would result in a crash enforced by the warm boot
+code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
+be flushed in s/w, before powering down the core.
+
+Power Collapse: This state is similar to the SPC mode, but distinguishes
+itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
+modes. In a hierarchical power domain SoC, this means L2 and other caches can
+be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
+voltages reduced, provided all cpus enter this state.  Since the span of low
+power modes possible at this state is vast, the exit latency and the residency
+of this low power mode would be considered high even though at a cpu level,
+this essentially is cpu power down. The SPM in this state also may handshake
+with the Resource power manager processor in the SoC to indicate a complete
+application processor subsystem shut down.
+
+The idle-state for QCOM SoCs are distinguished by the compatible property of
+the idle-states device node.
+The devicetree representation of the idle state should be -
+
+Required properties:
+
+- compatible: Must be one of -
+			"qcom,idle-state-stby",
+			"qcom,idle-state-ret",
+			"qcom,idle-state-spc",
+			"qcom,idle-state-pc",
+		and "arm,idle-state".
+
+Other required and optional properties are specified in [1].
+
+Example:
+
+	idle-states {
+		CPU_SPC: spc {
+			compatible = "qcom,idle-state-spc", "arm,idle-state";
+			entry-latency-us = <150>;
+			exit-latency-us = <200>;
+			min-residency-us = <2000>;
+		};
+	};
+
+[1]. Documentation/devicetree/bindings/arm/idle-states.txt

drivers/cpuidle/Kconfig.arm +7 -0

index 8c16ab2..e98993c 100644
@@ -63,3 +63,10 @@ config ARM_MVEBU_V7_CPUIDLE
 	depends on ARCH_MVEBU
 	help
 	  Select this to enable cpuidle on Armada 370, 38x and XP processors.
+
+config ARM_QCOM_CPUIDLE
+	bool "CPU Idle drivers for Qualcomm processors"
+	depends on ARCH_QCOM
+	select DT_IDLE_STATES
+	help
+	  Select this to enable cpuidle for QCOM processors

drivers/cpuidle/Makefile +1 -0

index 4d177b9..6c222d5 100644
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARM_ZYNQ_CPUIDLE)		+= cpuidle-zynq.o
 obj-$(CONFIG_ARM_U8500_CPUIDLE)         += cpuidle-ux500.o
 obj-$(CONFIG_ARM_AT91_CPUIDLE)          += cpuidle-at91.o
 obj-$(CONFIG_ARM_EXYNOS_CPUIDLE)        += cpuidle-exynos.o
+obj-$(CONFIG_ARM_QCOM_CPUIDLE)		+= cpuidle-qcom.o
 
 ###############################################################################
 # MIPS drivers

drivers/cpuidle/cpuidle-qcom.c new file +28 -0

new file mode 100644
index 0000000..1c1dcbc
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2014, Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <soc/qcom/pm.h>
+#include "dt_idle_states.h"
+
+static struct qcom_cpu_pm_ops *lpm_ops;
+
+static int qcom_cpu_stby(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index)
+{
+	lpm_ops->standby(NULL);
+

drivers/cpuidle/cpuidle-qcom.c new file +23 -0

+static struct cpuidle_driver qcom_cpuidle_driver = {
+	.name	= "qcom_cpuidle",
+};
+
+static const struct of_device_id qcom_idle_state_match[] = {
+	{ .compatible = "qcom,idle-state-stby", .data = qcom_cpu_stby},
+	{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
+	{ },
+};
+
+static int qcom_cpuidle_probe(struct platform_device *pdev)
+{
+	struct cpuidle_driver *drv = &qcom_cpuidle_driver;
+	int ret;
+
+	lpm_ops = pdev->dev.platform_data;
+
+	/* Probe for other states, including standby */
+	ret = dt_init_idle_driver(drv, qcom_idle_state_match, 0);
+	if (ret < 0)
+		return ret;
+
+	return cpuidle_register(drv, NULL);

Quoted 1 line · Lina Iyer

Add cpuidle driver interface to allow cpus to go into C-States. Use the

"idle states" please.

Acked-by Lorenzo Pieralisi <[email protected]>

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Add ARM common idle states device bindings for cpuidle support for APQ 8074/8974.

Support Standby and Standalone power collapse (power down that does not affect any SoC idle states) for each cpu.

Signed-off-by Lina Iyer <[email protected]>

Add ARM common idle states device bindings for cpuidle support for APQ 8084.

Support standby and standalone power collapse (power down that does not affect any SoC idle states) for each cpu.

Signed-off-by Lina Iyer <[email protected]>

Add ARM common idle state device bindings for cpuidle support for APQ 8064.

Support Standby and Standalone power collapse (power down that does not affect any SoC idle states) for each cpu.

Signed-off-by Lina Iyer <[email protected]>

arch/arm/boot/dts/qcom-apq8064.dtsi +8 -0

@@ -53,12 +56,30 @@
  			next-level-cache = <&L2>;
  			qcom,acc = <&acc3>;
  			qcom,saw = <&saw3>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
  		};
 
  		L2: l2-cache {
  			compatible = "cache";
  			cache-level = <2>;
  		};
+
+		idle-states {
+			CPU_STBY: standby {
+				compatible = "qcom,idle-state-stby", "arm,idle-state";
+				entry-latency-us = <1>;
+				exit-latency-us = <1>;
+				min-residency-us = <2>;

arch/arm/boot/dts/qcom-apq8064.dtsi +0 -0

  	};
 
  	cpu-pmu {

Changes since v9:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg11714.html ]
- Address review comments on v9
Dependent patchsets -

       https://lkml.org/lkml/2014/8/4/767
       http://www.spinics.net/lists/linux-arm-msm/msg10799.html
       http://www.spinics.net/lists/linux-arm-msm/msg10795.html

Changes since v8:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg11473.html ]
- Flatten out the file structure - merge pm.c into spm.c after discussions
- Add a new function to set warm boot address, in scm-boot.c
- Support for 8064 (New)
- Tested on 8074, 8084. 8064 was tested with a WIP tree
- Address review comments from v8
- Looking into possiblility of initializing the cpuidle device for a cpu, only when the corresponding spm device is probed successfully.

Changes since v7:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg11199.html ]
- Address review comments
- Tested on 8974 but not 8084
- WFI renamed to Standby
- Update commit text with original author and link to the downstream tree

Changes since v6:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg11012.html ]
- SPM device nodes merged with existing SAW DT nodes
- SPM register information is handled within the driver
- Clean up from using 'msm' to 'qcom'
- Shorten some enumerations as well
- Review comments from v6 addressed
- New: Support for 8084 SoC
- Not tested. I do not have a board with this SoC, but the SPM configuration should be identical for WFI and SPC

Changes since v5:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10559.html ]
- Merge spm-devices.c and spm.c into one file and one patch
- Simplify implementation of the driver.
- Update documentation mapping the DT properties with corresponding SPM register information.
- Removed scm-boot changes for quad core warmboot, its has been pulled in.

Changes since v4:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10327.html ]
- Update to the v8 of ARM generic idle states patches
- Use platform device model for cpuidle-qcom
- Clean up msm-pm.c to remove unnecessary include files and functions
- Update commit text and documentation for all idle states
- Remove scm-boot relocate patch from this series, submitted earlier [ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10518.html ]

Changes since v3:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10288.html ]
- Fix CONFIG_QCOM_PM Kconfig as bool
- More clean ups in spm.c and spm-devices.c
- Removed and re-organized data structures to make initialization simple
- Remove export of sequence flush functions
- Updated commit text
- Comments for use of barriers.
- Rebase on top of 3.17-rc1

Changes since v2:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10148.html ]
- Prune all the drivers to support basic WFI and power down cpuidle functionality. Remove debug code.
- Integrate KConfig changes into the drivers' patches.
- Use Lorenzo's ARM idle-states patches as the basis for reading cpuidle c-states from DT.
[ http://marc.info/?l=linux-pm&m=140794514812383&w=2 ]
- Incorporate review comments
- Rebase on top of 3.16

Changes since v1/RFC:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10065.html ]
- Remove hotplug from the patch series. Will submit it separately.
- Fix SPM drivers per the review comments
- Modify patch sequence to compile SPM drivers independent of msm-pm, so as to allow wfi() calls to use SPM even without SoC interface driver.

8074/8084/8064 like any ARM SoC can do architectural clock gating, that helps save on power, but not enough of leakage power. Leakage power of the SoC can be further reduced by turning off power to the core. To aid this, every core (cpu and L2) is accompanied by a Sub-system Power Manager (SPM), that can be configured to indicate the low power mode, the core would be put into and the SPM programs the peripheral h/w accordingly to enter low power and turn off the power rail to the core.

The idle invocation hierarchy -

CPUIDLE

       |
       cpuidle-qcom.c [CPUIdle driver]
       |
       ------> spm.c [SPM driver]
               |
               ------> scm-boot.c [SCM interface layer]
                       |
------------------------|--------------------------
(EL)                    Secure Monitor Code
                       |
                       |
                       wfi();
------------------------|--------------------------
(HW)                    [CPU] {clock gate}
                       |
                       -----> [SPM] {statemachine}

The patchset does the following -

- Introduce the SPM driver to control power to the core
- Add device bindings for 8974, 8084, 8064 CPU SPM devices
- Add cpuidle driver for QCOM cpus, using ARM generic idle state definitions.
- Add device bindings for 8974, 8084, 8064 idle-states - WFI and SPC

Thanks,
Lina

Lina Iyer (10):
qom: scm: Move scm-boot files to drivers/soc/qcom/ and
include/soc/qcom
qcom: scm: Add SCM warmboot support for quad core SoCs
qcom: spm: Add Subsystem Power Manager driver
arm: dts: qcom: Add power-controller device node for 8074 Krait CPUs
arm: dts: qcom: Add power-controller device node for 8084 Krait CPUs
arm: dts: qcom: Update power-controller device node for 8064 Krait
CPUs
qcom: cpuidle: Add cpuidle driver for QCOM cpus
arm: dts: qcom: Add idle states device nodes for 8074
arm: dts: qcom: Add idle states device nodes for 8084
arm: dts: qcom: Add idle state device nodes for 8064

.../bindings/arm/msm/qcom,idle-state.txt           |  81 +++++
.../devicetree/bindings/arm/msm/qcom,saw2.txt      |  31 +-
arch/arm/boot/dts/qcom-apq8064.dtsi                |  37 ++-
arch/arm/boot/dts/qcom-apq8084.dtsi                |  46 ++-
arch/arm/boot/dts/qcom-msm8974.dtsi                |  46 ++-
arch/arm/mach-qcom/Makefile                        |   1 -
arch/arm/mach-qcom/platsmp.c                       |   2 +-
drivers/cpuidle/Kconfig.arm                        |   7 +
drivers/cpuidle/Makefile                           |   1 +
drivers/cpuidle/cpuidle-qcom.c                     |  72 +++++
drivers/soc/qcom/Kconfig                           |   8 +
drivers/soc/qcom/Makefile                          |   3 +-
.../arm/mach-qcom => drivers/soc/qcom}/scm-boot.c  |  33 +-
drivers/soc/qcom/spm.c                             | 332 +++++++++++++++++++++
include/soc/qcom/pm.h                              |  31 ++
.../arm/mach-qcom => include/soc/qcom}/scm-boot.h  |   3 +-
16 files changed, 712 insertions(+), 22 deletions(-)

create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt create mode 100644 drivers/cpuidle/cpuidle-qcom.c
rename {arch/arm/mach-qcom => drivers/soc/qcom}/scm-boot.c (63%) create mode 100644 drivers/soc/qcom/spm.c
create mode 100644 include/soc/qcom/pm.h
rename {arch/arm/mach-qcom => include/soc/qcom}/scm-boot.h (91%)

Signature · 1 line

2.1.0