clk: sun6i: Unify AHB1 clock and fix rate calculation

Hi everyone,

This is a resend of v4 of the sun6i AHB1 clock unification series. This includes only the 3 patches not yet merged.

This series unifies the mux and divider parts of the AHB1 clock found on sun6i and sun8i, while also adding support for the pre-divider on the PLL6 input.

The rate calculation logic must factor in which parent it is using to calculate the rate, to decide whether to use the pre-divider or not. This is beyond the original factors clk design in sunxi. To avoid feature bloat, this is implemented as a separate composite clk.

The new clock driver is registered with a separate OF_CLK_DECLARE. As it shares its register with the APB1 div clock, thus shares the same spinlock, it cannot reside in a separate file.

The contents of this series are as follows:

Patch 1 adds the unified AHB1 clock driver.

Patch 2 and 3 unify the AHB1 clock nodes on sun6i and sun8i respectively.

Changes since v3:

- Moved AHB1 clock driver to the front of clk-sunxi.c

- Dropped the following patches that were merged already:

clk: sunxi: Specify number of child clocks for divs clocks
clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
ARM: sun6i: DT: Add PLL6 multiple outputs

Changes since v2:

- Rebased onto the following patches

clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driver
ARM: dts: sunxi: Use sun4i-a10-apb1-clk for sun6i/sun8i apb2 clocks.
ARM: dts: sunxi: unify APB1 clock
clk: sunxi: unify APB1 clock
ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller

- Dropped

ARM: dts: sun6i: Add required ahb1 clock parent and rates for dma controller

as it is superseded by the re-parent patch from above.

- Expand clock bindings to include output names for PLL6

- Use of_io_request_and_map

- Drop ahb1 rate setting in DTS

- Whitespace and comment style cleanups

Changes since v1:

- Dropped "clk: sunxi: Add post clk divider for factor clocks"

- Added "clk: sunxi: Specify number of child clocks for divs clocks"

- Reworked the PLL6 clock into a divs clock with 2 outputs. This matches the style of PLL6 on the other sunxi platforms.

- Dropped "dmaengine: sun6i: Remove obsolete clk muxing code". Already merged.

Cheers
ChenYu

Chen-Yu Tsai (3):
clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
ARM: dts: sun6i: Unify ahb1 clock nodes
ARM: dts: sun8i: Unify ahb1 clock nodes

 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +-
 arch/arm/boot/dts/sun6i-a31.dtsi                  |  14 +-
 arch/arm/boot/dts/sun8i-a23.dtsi                  |  12 +-
 drivers/clk/sunxi/clk-sunxi.c                     | 208 ++++++++++++++++++++++
 4 files changed, 214 insertions(+), 22 deletions(-)

2.1.3

This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation.

---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +-
 drivers/clk/sunxi/clk-sunxi.c                     | 208 ++++++++++++++++++++++
 2 files changed, 209 insertions(+), 1 deletion(-)

index 67b2b99..9dc4f55 100644
@@ -26,7 +26,7 @@ Required properties:
 	"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
 	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
 	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
-	"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
 	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
 	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80

2.1.3

The clock driver has unified support for the ahb1 clock. Unify the clock nodes so it works.

---
 arch/arm/boot/dts/sun6i-a31.dtsi | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

index f47156b..62d932e 100644
@@ -174,19 +174,11 @@
 			clock-output-names = "axi";
 		};
 
-		ahb1_mux: ahb1_mux at 01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
-			clock-output-names = "ahb1_mux";
-		};
-
 		ahb1: ahb1 at 01c20054 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-ahb-clk";
+			compatible = "allwinner,sun6i-a31-ahb1-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&ahb1_mux>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 			clock-output-names = "ahb1";
 		};
 

@@ -367,7 +359,7 @@
 			#dma-cells = <1>;
 
 			/* DMA controller requires AHB1 clocked from PLL6 */
-			assigned-clocks = <&ahb1_mux>;
+			assigned-clocks = <&ahb1>;
 			assigned-clock-parents = <&pll6 0>;
 		};
 

2.1.3

The clock driver has unified support for the ahb1 clock. Unify the clock nodes so it works.

---
 arch/arm/boot/dts/sun8i-a23.dtsi | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

index 0746cd1..726b613 100644
@@ -140,19 +140,11 @@
 			clock-output-names = "axi";
 		};
 
-		ahb1_mux: ahb1_mux_clk at 01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
-			clock-output-names = "ahb1_mux";
-		};
-
 		ahb1: ahb1_clk at 01c20054 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-ahb-clk";
+			compatible = "allwinner,sun6i-a31-ahb1-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&ahb1_mux>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 			clock-output-names = "ahb1";
 		};
 

2.1.3

Queued this for 3.20, thanks!
Maxime

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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