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sun6i / A31 ir receiver support

PATCH New Hans de Goede 3 participants 15 messages Nov 23, 2014 – Nov 27, 2014

Subsystems (7)
Device tree bindings Media (V4L/DVB) Common clk Multifunction devices (MFD) +3 more subsystems
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Hans de Goede

author
#0 lore raw

v2 cover sun6i / A31 ir receiver support

Hi All,

Here is v2 of my sun6i ir receiver support patch-set as with v1, this touches clk, mfd (for the prcm clks), dts and media/rc code.

Changes in v2:
-"clk: sunxi: Give sunxi_factors_register a registers parameter"
-Updated commit message to mention the removal of __init -Add error checking to calls of of_iomap
-"rc: sunxi-cir: Add support for an optional reset controller"
-Document resets property in devicetree bindings doc

Regards,

Hans

author
#1 lore raw

PATCH v2 1/9 clk: sunxi: Give sunxi_factors_register a registers parameter

Before this commit sunxi_factors_register uses of_iomap(node, 0) to get the clk registers. The sun6i prcm has factor clocks, for which we want to use sunxi_factors_register, but of_iomap(node, 0) does not work for the prcm factor clocks, because the prcm uses the mfd framework, so the registers are not part of the dt-node, instead they are added to the platform_device, as platform_device resources.

This commit makes getting the registers the callers duty, so that sunxi_factors_register can be used with mfd instantiated platform device too.

While at it also add error checking to the of_iomap calls.

This commit also drops the __init function from sunxi_factors_register since platform driver probe functions are not __init.

Signed-off-by Hans de Goede <[email protected]>
---
 drivers/clk/sunxi/clk-factors.c    | 10 ++++------
 drivers/clk/sunxi/clk-factors.h    |  7 ++++---
 drivers/clk/sunxi/clk-mod0.c       | 24 ++++++++++++++++++++++--
 drivers/clk/sunxi/clk-sun8i-mbus.c | 13 +++++++++++--
 drivers/clk/sunxi/clk-sunxi.c      | 11 ++++++++++-
 5 files changed, 51 insertions(+), 14 deletions(-)
drivers/clk/sunxi/clk-factors.c +4 -6
index f83ba09..fc4f4b5 100644
@@ -156,9 +156,10 @@ static const struct clk_ops clk_factors_ops = {
 	.set_rate = clk_factors_set_rate,
 };
 
-struct clk * __init sunxi_factors_register(struct device_node *node,
-					   const struct factors_data *data,
-					   spinlock_t *lock)
+struct clk *sunxi_factors_register(struct device_node *node,
+				   const struct factors_data *data,
+				   spinlock_t *lock,
+				   void __iomem *reg)
 {
 	struct clk *clk;
 	struct clk_factors *factors;

@@ -168,11 +169,8 @@ struct clk * __init sunxi_factors_register(struct device_node *node,
 	struct clk_hw *mux_hw = NULL;
 	const char *clk_name = node->name;
 	const char *parents[FACTORS_MAX_PARENTS];
-	void __iomem *reg;
 	int i = 0;
 
-	reg = of_iomap(node, 0);
-
 	/* if we have a mux, we will have >1 parents */
 	while (i < FACTORS_MAX_PARENTS &&
 	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
drivers/clk/sunxi/clk-factors.h +4 -3
index 9913840..1f5526d 100644
@@ -37,8 +37,9 @@ struct clk_factors {
 	spinlock_t *lock;
 };
 
-struct clk * __init sunxi_factors_register(struct device_node *node,
-					   const struct factors_data *data,
-					   spinlock_t *lock);
+struct clk *sunxi_factors_register(struct device_node *node,
+				   const struct factors_data *data,
+				   spinlock_t *lock,
+				   void __iomem *reg);
 
 #endif
drivers/clk/sunxi/clk-mod0.c +22 -2
index 4a56385..5fb1f7e 100644
@@ -78,7 +78,17 @@ static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);
 
 static void __init sun4i_a10_mod0_setup(struct device_node *node)
 {
-	sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun4i_a10_mod0_lock);
+	void __iomem *reg;
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("Could not get registers for mod0-clk: %s\n",
+		       node->name);
+		return;
+	}
+
+	sunxi_factors_register(node, &sun4i_a10_mod0_data,
+			       &sun4i_a10_mod0_lock, reg);
 }
 CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);
 

@@ -86,7 +96,17 @@ static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
 
 static void __init sun5i_a13_mbus_setup(struct device_node *node)
 {
-	struct clk *mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun5i_a13_mbus_lock);
+	struct clk *mbus;
+	void __iomem *reg;
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("Could not get registers for a13-mbus-clk\n");
+		return;
+	}
+
+	mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data,
+				      &sun5i_a13_mbus_lock, reg);
 
 	/* The MBUS clocks needs to be always enabled */
 	__clk_get(mbus);
drivers/clk/sunxi/clk-sun8i-mbus.c +11 -2
index 8e49b44..c0629ff 100644
@@ -68,8 +68,17 @@ static DEFINE_SPINLOCK(sun8i_a23_mbus_lock);
 
 static void __init sun8i_a23_mbus_setup(struct device_node *node)
 {
-	struct clk *mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data,
-						  &sun8i_a23_mbus_lock);
+	struct clk *mbus;
+	void __iomem *reg;
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("Could not get registers for a23-mbus-clk\n");
+		return;
+	}
+
+	mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data,
+				      &sun8i_a23_mbus_lock, reg);
 
 	/* The MBUS clocks needs to be always enabled */
 	__clk_get(mbus);
drivers/clk/sunxi/clk-sunxi.c +10 -1
index b1f66ad..6062a3e 100644
@@ -521,7 +521,16 @@ static const struct factors_data sun7i_a20_out_data __initconst = {
 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 						   const struct factors_data *data)
 {
-	return sunxi_factors_register(node, data, &clk_lock);
+	void __iomem *reg;
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("Could not get registers for factors-clk: %s\n",
+		       node->name);
+		return NULL;
+	}
+
+	return sunxi_factors_register(node, data, &clk_lock, reg);
 }
Signature · 1 line
2.1.0
Applied
#2 lore raw

PATCH v2 1/9 clk: sunxi: Give sunxi_factors_register a registers parameter

Quoted 10 lines · Hans de Goede

Before this commit sunxi_factors_register uses of_iomap(node, 0) to get the clk registers. The sun6i prcm has factor clocks, for which we want to use sunxi_factors_register, but of_iomap(node, 0) does not work for the prcm factor clocks, because the prcm uses the mfd framework, so the registers are not part of the dt-node, instead they are added to the platform_device, as platform_device resources.

This commit makes getting the registers the callers duty, so that sunxi_factors_register can be used with mfd instantiated platform device too.

Quoted 6 lines

While at it also add error checking to the of_iomap calls.

This commit also drops the __init function from sunxi_factors_register since platform driver probe functions are not __init.

Signed-off-by Hans de Goede <[email protected]>

Queued for 3.20, thanks!

Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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author
#3 lore raw

PATCH v2 2/9 clk: sunxi: Make sun4i_a10_mod0_data available outside of clk-mod0.c

In reply to Hans de Goede

The sun6i prcm has mod0 compatible clocks, these need a separate driver because the prcm uses the mfd framework, but we do want to re-use the standard mod0 clk handling from clk-mod0.c for this, export sun4i_a10_mod0_data, so that the prcm mod0 clk driver can use this.

Signed-off-by Hans de Goede <[email protected]>
---
 drivers/clk/sunxi/clk-mod0.c | 2 +-
 drivers/clk/sunxi/clk-mod0.h | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi/clk-mod0.h
drivers/clk/sunxi/clk-mod0.c +1 -1
index 5fb1f7e..7c06d42 100644
@@ -67,7 +67,7 @@ static struct clk_factors_config sun4i_a10_mod0_config = {
 	.pwidth = 2,
 };
 
-static const struct factors_data sun4i_a10_mod0_data __initconst = {
+const struct factors_data sun4i_a10_mod0_data = {
 	.enable = 31,
 	.mux = 24,
 	.table = &sun4i_a10_mod0_config,
drivers/clk/sunxi/clk-mod0.h new file +8 -0
new file mode 100644
index 0000000..49aa9ab
@@ -0,0 +1,8 @@
+#ifndef __MACH_SUNXI_CLK_MOD0_H
+#define __MACH_SUNXI_CLK_MOD0_H
+
+#include "clk-factors.h"
+
+extern const struct factors_data sun4i_a10_mod0_data;
+
+#endif
Signature · 1 line
2.1.0
author
#4 lore raw

PATCH v2 3/9 clk: sunxi: Add prcm mod0 clock driver

In reply to Hans de Goede

Add a driver for mod0 clocks found in the prcm. Currently there is only one mod0 clocks in the prcm, the ir clock.

Signed-off-by Hans de Goede <[email protected]>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile                        |  2 +-
 drivers/clk/sunxi/clk-sun6i-prcm-mod0.c           | 63 +++++++++++++++++++++++
 drivers/mfd/sun6i-prcm.c                          | 14 +++++
 4 files changed, 79 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi/clk-sun6i-prcm-mod0.c
Documentation/devicetree/bindings/clock/sunxi.txt +1 -0
index ed116df..342c75a 100644
@@ -56,6 +56,7 @@ Required properties:
 	"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
 	"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
 	"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
+	"allwinner,sun6i-a31-ir-clk" - for the ir clock on A31
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
drivers/clk/sunxi/Makefile +1 -1
index 7ddc2b5..daf8b1c 100644
@@ -10,4 +10,4 @@ obj-y += clk-sun8i-mbus.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
 	clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
-	clk-sun8i-apb0.o
+	clk-sun8i-apb0.o clk-sun6i-prcm-mod0.o
drivers/clk/sunxi/clk-sun6i-prcm-mod0.c new file +63 -0

63 lines not on this page · raw message

drivers/mfd/sun6i-prcm.c +14 -0
index 283ab8d..ff1254f 100644
@@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
 	},
 };
 
+static const struct resource sun6i_a31_ir_clk_res[] = {
+	{
+		.start = 0x54,
+		.end = 0x57,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
 static const struct resource sun6i_a31_apb0_rstc_res[] = {
 	{
 		.start = 0xb0,

@@ -69,6 +77,12 @@ static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
 		.resources = sun6i_a31_apb0_gates_clk_res,
 	},
 	{
+		.name = "sun6i-a31-ir-clk",
+		.of_compatible = "allwinner,sun6i-a31-ir-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
+		.resources = sun6i_a31_ir_clk_res,
+	},
+	{
 		.name = "sun6i-a31-apb0-clock-reset",
 		.of_compatible = "allwinner,sun6i-a31-clock-reset",
 		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
Signature · 1 line
2.1.0
#5 lore raw

PATCH v2 3/9 clk: sunxi: Add prcm mod0 clock driver

Quoted 11 lines · Hans de Goede

Add a driver for mod0 clocks found in the prcm. Currently there is only one mod0 clocks in the prcm, the ir clock.

Signed-off-by Hans de Goede <[email protected]>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile                        |  2 +-
 drivers/clk/sunxi/clk-sun6i-prcm-mod0.c           | 63 +++++++++++++++++++++++
 drivers/mfd/sun6i-prcm.c                          | 14 +++++
 4 files changed, 79 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi/clk-sun6i-prcm-mod0.c

[...]

Quoted 5 lines
drivers/mfd/sun6i-prcm.c +0 -0
index 283ab8d..ff1254f 100644

drivers/mfd/sun6i-prcm.c static const struct resource sun6i_a31_apb0_gates_clk_res[] = { · line 50

Quoted 10 lines
drivers/mfd/sun6i-prcm.c +7 -0
@@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
 	},
 };
 
+static const struct resource sun6i_a31_ir_clk_res[] = {
+	{
+		.start = 0x54,
+		.end = 0x57,
+		.flags = IORESOURCE_MEM,
+	},
+};

I'm not overly keen on these magic numbers (and yes, I'm well aware that I SoB'ed the patch which started them off).

It's not a show stopper, although I'd prefer if they were fixed with a subsequent patch.

Acked-by Lee Jones <[email protected]>
Signature · 4 lines
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
author
#6 lore raw

PATCH v2 3/9 clk: sunxi: Add prcm mod0 clock driver

Hi,

Quoted 35 lines · Lee Jones
Quoted 11 lines · Hans de Goede

Add a driver for mod0 clocks found in the prcm. Currently there is only one mod0 clocks in the prcm, the ir clock.

Signed-off-by Hans de Goede <[email protected]>
---
  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
  drivers/clk/sunxi/Makefile                        |  2 +-
  drivers/clk/sunxi/clk-sun6i-prcm-mod0.c           | 63 +++++++++++++++++++++++
  drivers/mfd/sun6i-prcm.c                          | 14 +++++
  4 files changed, 79 insertions(+), 1 deletion(-)

create mode 100644 drivers/clk/sunxi/clk-sun6i-prcm-mod0.c

[...]

Quoted 5 lines
drivers/mfd/sun6i-prcm.c +0 -0
index 283ab8d..ff1254f 100644

drivers/mfd/sun6i-prcm.c static const struct resource sun6i_a31_apb0_gates_clk_res[] = { · line 50

Quoted 10 lines
drivers/mfd/sun6i-prcm.c +7 -0
@@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
  	},
  };
 
+static const struct resource sun6i_a31_ir_clk_res[] = {
+	{
+		.start = 0x54,
+		.end = 0x57,
+		.flags = IORESOURCE_MEM,
+	},
+};

I'm not overly keen on these magic numbers (and yes, I'm well aware that I SoB'ed the patch which started them off).

Quoted 2 lines

It's not a show stopper, although I'd prefer if they were fixed with a subsequent patch.

These are offsets of the relevant registers inside the prcm register block, if not done this way, then how should they be done ?

Regards,

Hans

#7 lore raw

PATCH v2 3/9 clk: sunxi: Add prcm mod0 clock driver

Quoted 38 lines · Hans de Goede

Hi,

Quoted 35 lines · Lee Jones
Quoted 11 lines · Hans de Goede

Add a driver for mod0 clocks found in the prcm. Currently there is only one mod0 clocks in the prcm, the ir clock.

Signed-off-by Hans de Goede <[email protected]>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile                        |  2 +-
 drivers/clk/sunxi/clk-sun6i-prcm-mod0.c           | 63 +++++++++++++++++++++++
 drivers/mfd/sun6i-prcm.c                          | 14 +++++
 4 files changed, 79 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi/clk-sun6i-prcm-mod0.c

[...]

Quoted 5 lines
drivers/mfd/sun6i-prcm.c +0 -0
index 283ab8d..ff1254f 100644

drivers/mfd/sun6i-prcm.c static const struct resource sun6i_a31_apb0_gates_clk_res[] = { · line 50

Quoted 10 lines
drivers/mfd/sun6i-prcm.c +7 -0
@@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
 	},
 };
 
+static const struct resource sun6i_a31_ir_clk_res[] = {
+	{
+		.start = 0x54,
+		.end = 0x57,
+		.flags = IORESOURCE_MEM,
+	},
+};

I'm not overly keen on these magic numbers (and yes, I'm well aware that I SoB'ed the patch which started them off).

Quoted 5 lines
Quoted 2 lines

It's not a show stopper, although I'd prefer if they were fixed with a subsequent patch.

These are offsets of the relevant registers inside the prcm register block, if not done this way, then how should they be done ?

I like these kinds of things to be defined. No implementation changes are necessary.

Signature · 4 lines
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
author
#8 lore raw

PATCH v2 4/9 rc: sunxi-cir: Add support for an optional reset controller

In reply to Hans de Goede

On sun6i the cir block is attached to the reset controller, add support for de-asserting the reset if a reset controller is specified in dt.

Signed-off-by Hans de Goede <[email protected]>
Acked-by Mauro Carvalho Chehab <[email protected]>
Acked-by Maxime Ripard <[email protected]>
---
 .../devicetree/bindings/media/sunxi-ir.txt         |  2 ++
 drivers/media/rc/sunxi-cir.c                       | 25 ++++++++++++++++++++--
 2 files changed, 25 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/media/sunxi-ir.txt +2 -0
index 23dd5ad..6b70b9b 100644
@@ -10,6 +10,7 @@ Required properties:
 
 Optional properties:
 - linux,rc-map-name : Remote control map name.
+- resets : phandle + reset specifier pair
 
 Example:
 

@@ -17,6 +18,7 @@ ir0: ir at 01c21800 {
 	compatible = "allwinner,sun4i-a10-ir";
 	clocks = <&apb0_gates 6>, <&ir0_clk>;
 	clock-names = "apb", "ir";
+	resets = <&apb0_rst 1>;
 	interrupts = <0 5 1>;
 	reg = <0x01C21800 0x40>;
 	linux,rc-map-name = "rc-rc6-mce";
drivers/media/rc/sunxi-cir.c +23 -2
index bcee8e1..895fb65 100644
@@ -23,6 +23,7 @@
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/of_platform.h>
+#include <linux/reset.h>
 #include <media/rc-core.h>
 
 #define SUNXI_IR_DEV "sunxi-ir"

@@ -95,6 +96,7 @@ struct sunxi_ir {
 	int             irq;
 	struct clk      *clk;
 	struct clk      *apb_clk;
+	struct reset_control *rst;
 	const char      *map_name;
 };
 

@@ -166,15 +168,29 @@ static int sunxi_ir_probe(struct platform_device *pdev)
 		return PTR_ERR(ir->clk);
 	}
 
+	/* Reset (optional) */
+	ir->rst = devm_reset_control_get_optional(dev, NULL);
+	if (IS_ERR(ir->rst)) {
+		ret = PTR_ERR(ir->rst);
+		if (ret == -EPROBE_DEFER)
+			return ret;
+		ir->rst = NULL;
+	} else {
+		ret = reset_control_deassert(ir->rst);
+		if (ret)
+			return ret;
+	}
+
 	ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
 	if (ret) {
 		dev_err(dev, "set ir base clock failed!\n");
-		return ret;
+		goto exit_reset_assert;
 	}
 
 	if (clk_prepare_enable(ir->apb_clk)) {
 		dev_err(dev, "try to enable apb_ir_clk failed\n");
-		return -EINVAL;
+		ret = -EINVAL;
+		goto exit_reset_assert;
 	}
 
 	if (clk_prepare_enable(ir->clk)) {

@@ -271,6 +287,9 @@ exit_clkdisable_clk:
 	clk_disable_unprepare(ir->clk);
 exit_clkdisable_apb_clk:
 	clk_disable_unprepare(ir->apb_clk);
+exit_reset_assert:
+	if (ir->rst)
+		reset_control_assert(ir->rst);
 
 	return ret;
 }

@@ -282,6 +301,8 @@ static int sunxi_ir_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(ir->clk);
 	clk_disable_unprepare(ir->apb_clk);
+	if (ir->rst)
+		reset_control_assert(ir->rst);
 
 	spin_lock_irqsave(&ir->ir_lock, flags);
 	/* disable IR IRQ */
Signature · 1 line
2.1.0
author
#9 lore raw

PATCH v2 5/9 rc: sunxi-cir: Add support for the larger fifo found on sun5i and sun6i

In reply to Hans de Goede

Add support for the larger fifo found on sun5i and sun6i, having a separate compatible for the ir found on sun5i & sun6i also is useful if we ever want to add ir transmit support, because the sun5i & sun6i version do not have transmit support.

Note this commits also adds checking for the end-of-packet interrupt flag (which was already enabled), as the fifo-data-available interrupt flag only gets set when the trigger-level is exceeded. So far we've been getting away with not doing this because of the low trigger-level, but this is something which we should have done since day one.

Signed-off-by Hans de Goede <[email protected]>
Acked-by Mauro Carvalho Chehab <[email protected]>
Acked-by Maxime Ripard <[email protected]>
---
 .../devicetree/bindings/media/sunxi-ir.txt          |  2 +-
 drivers/media/rc/sunxi-cir.c                        | 21 ++++++++++++---------
 2 files changed, 13 insertions(+), 10 deletions(-)
Documentation/devicetree/bindings/media/sunxi-ir.txt +1 -1
index 6b70b9b..1811a06 100644
@@ -1,7 +1,7 @@
 Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
 
 Required properties:
-- compatible	    : should be "allwinner,sun4i-a10-ir";
+- compatible	    : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
 - clocks	    : list of clock specifiers, corresponding to
 		      entries in clock-names property;
 - clock-names	    : should contain "apb" and "ir" entries;
drivers/media/rc/sunxi-cir.c +12 -9
index 895fb65..559b0e3 100644
@@ -56,12 +56,12 @@
 #define REG_RXINT_RAI_EN		BIT(4)
 
 /* Rx FIFO available byte level */
-#define REG_RXINT_RAL(val)    (((val) << 8) & (GENMASK(11, 8)))
+#define REG_RXINT_RAL(val)    ((val) << 8)
 
 /* Rx Interrupt Status */
 #define SUNXI_IR_RXSTA_REG    0x30
 /* RX FIFO Get Available Counter */
-#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (GENMASK(5, 0)))
+#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
 /* Clear all interrupt status value */
 #define REG_RXSTA_CLEARALL    0xff
 

@@ -72,10 +72,6 @@
 /* CIR_REG register idle threshold */
 #define REG_CIR_ITHR(val)    (((val) << 8) & (GENMASK(15, 8)))
 
-/* Hardware supported fifo size */
-#define SUNXI_IR_FIFO_SIZE    16
-/* How many messages in FIFO trigger IRQ */
-#define TRIGGER_LEVEL         8
 /* Required frequency for IR0 or IR1 clock in CIR mode */
 #define SUNXI_IR_BASE_CLK     8000000
 /* Frequency after IR internal divider  */

@@ -94,6 +90,7 @@ struct sunxi_ir {
 	struct rc_dev   *rc;
 	void __iomem    *base;
 	int             irq;
+	int		fifo_size;
 	struct clk      *clk;
 	struct clk      *apb_clk;
 	struct reset_control *rst;

@@ -115,11 +112,11 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
 	/* clean all pending statuses */
 	writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
 
-	if (status & REG_RXINT_RAI_EN) {
+	if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
 		/* How many messages in fifo */
 		rc  = REG_RXSTA_GET_AC(status);
 		/* Sanity check */
-		rc = rc > SUNXI_IR_FIFO_SIZE ? SUNXI_IR_FIFO_SIZE : rc;
+		rc = rc > ir->fifo_size ? ir->fifo_size : rc;
 		/* If we have data */
 		for (cnt = 0; cnt < rc; cnt++) {
 			/* for each bit in fifo */

@@ -156,6 +153,11 @@ static int sunxi_ir_probe(struct platform_device *pdev)
 	if (!ir)
 		return -ENOMEM;
 
+	if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
+		ir->fifo_size = 64;
+	else
+		ir->fifo_size = 16;
+
 	/* Clock */
 	ir->apb_clk = devm_clk_get(dev, "apb");
 	if (IS_ERR(ir->apb_clk)) {

@@ -271,7 +273,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
 	 * level
 	 */
 	writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
-	       REG_RXINT_RAI_EN | REG_RXINT_RAL(TRIGGER_LEVEL - 1),
+	       REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
 	       ir->base + SUNXI_IR_RXINT_REG);
 
 	/* Enable IR Module */

@@ -319,6 +321,7 @@ static int sunxi_ir_remove(struct platform_device *pdev)
 
 static const struct of_device_id sunxi_ir_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-ir", },
+	{ .compatible = "allwinner,sun5i-a13-ir", },
 	{},
 };
Signature · 1 line
2.1.0
author
#10 lore raw

PATCH v2 6/9 ARM: dts: sun6i: Add ir_clk node

In reply to Hans de Goede

Add an ir_clk sub-node to the prcm node.

Signed-off-by Hans de Goede <[email protected]>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm/boot/dts/sun6i-a31.dtsi +7 -0
index a01b215..4aa628b 100644
@@ -882,6 +882,13 @@
 						"apb0_i2c";
 			};
 
+			ir_clk: ir_clk {
+				#clock-cells = <0>;
+				compatible = "allwinner,sun6i-a31-ir-clk";
+				clocks = <&osc32k>, <&osc24M>;
+				clock-output-names = "ir";
+			};
+
 			apb0_rst: apb0_rst {
 				compatible = "allwinner,sun6i-a31-clock-reset";
 				#reset-cells = <1>;
Signature · 1 line
2.1.0
author
#11 lore raw

PATCH v2 7/9 ARM: dts: sun6i: Add ir node

In reply to Hans de Goede

Add a node for the ir receiver found on the A31.

Signed-off-by Hans de Goede <[email protected]>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)
arch/arm/boot/dts/sun6i-a31.dtsi +10 -0
index 4aa628b..d33e758 100644
@@ -900,6 +900,16 @@
 			reg = <0x01f01c00 0x300>;
 		};
 
+		ir at 01f02000 {
+			compatible = "allwinner,sun5i-a13-ir";
+			clocks = <&apb0_gates 1>, <&ir_clk>;
+			clock-names = "apb", "ir";
+			resets = <&apb0_rst 1>;
+			interrupts = <0 37 4>;
+			reg = <0x01f02000 0x40>;
+			status = "disabled";
+		};
+
 		r_pio: pinctrl at 01f02c00 {
 			compatible = "allwinner,sun6i-a31-r-pinctrl";
 			reg = <0x01f02c00 0x400>;
Signature · 1 line
2.1.0
author
#12 lore raw

PATCH v2 8/9 ARM: dts: sun6i: Add pinmux settings for the ir pins

In reply to Hans de Goede

Add pinmux settings for the ir receive pin of the A31.

Signed-off-by Hans de Goede <[email protected]>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm/boot/dts/sun6i-a31.dtsi +7 -0
index d33e758..90b7537 100644
@@ -922,6 +922,13 @@
 			#interrupt-cells = <2>;
 			#size-cells = <0>;
 			#gpio-cells = <3>;
+
+			ir_pins_a: ir at 0 {
+				allwinner,pins = "PL4";
+				allwinner,function = "s_ir";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
 		};
 	};
 };
Signature · 1 line
2.1.0
Applied
#13 lore raw

PATCH v2 8/9 ARM: dts: sun6i: Add pinmux settings for the ir pins

Quoted 3 lines · Hans de Goede

Add pinmux settings for the ir receive pin of the A31.

Signed-off-by Hans de Goede <[email protected]>

Applied, thanks!

Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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author
#14 lore raw

PATCH v2 9/9 ARM: dts: sun6i: Enable ir receiver on the Mele M9

In reply to Hans de Goede

The Mele M9 has an ir receiver, enable it.

Signed-off-by Hans de Goede <[email protected]>
---
 arch/arm/boot/dts/sun6i-a31-m9.dts | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm/boot/dts/sun6i-a31-m9.dts +6 -0
index 4202c64..94ddf9c 100644
@@ -83,6 +83,12 @@
 				reg = <1>;
 			};
 		};
+
+		ir at 01f02000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&ir_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {
Signature · 1 line
2.1.0