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nvme: 64kB page size fixes

PATCH Applied Anton Blanchard 5 participants 5 messages Nov 27, 2014 – Dec 9, 2014

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Anton Blanchard

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#0 lore raw

PATCH 1/1 nvme: 64kB page size fixes

Initialise our maximum page size capability to 64kB and increase the page_size variable from 16 to 32 bits.

Signed-off-by Anton Blanchard <[email protected]>

--

hw/block/nvme.c +1 -0
index 1327658..aa1ed98 100644
@@ -811,6 +811,7 @@ static int nvme_init(PCIDevice *pci_dev)
     NVME_CAP_SET_AMS(n->bar.cap, 1);
     NVME_CAP_SET_TO(n->bar.cap, 0xf);
     NVME_CAP_SET_CSS(n->bar.cap, 1);
+    NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
 
     n->bar.vs = 0x00010001;
     n->bar.intmc = n->bar.intms = 0;
hw/block/nvme.h +1 -1
index 993c511..b6ccb65 100644
@@ -688,7 +688,7 @@ typedef struct NvmeCtrl {
     NvmeBar      bar;
     BlockConf    conf;
 
-    uint16_t    page_size;
+    uint32_t    page_size;
     uint16_t    page_bits;
     uint16_t    max_prp_ents;
     uint16_t    cqe_size;
Applied
#2 lore raw

Am 02.12.2014 um 16:04 hat Stefan Hajnoczi geschrieben:

Quoted 12 lines · Anton Blanchard
Quoted 5 lines

Initialise our maximum page size capability to 64kB and increase the page_size variable from 16 to 32 bits.

Signed-off-by Anton Blanchard <[email protected]>

--

Covered in NVM Express 1.1 specification "3.1.1 Offset 00h: CAP - Controller Capabilities".
http://www.nvmexpress.org/wp-content/uploads/NVM-Express-1_1.pdf

Reviewed-by Stefan Hajnoczi <[email protected]>

Thanks, applied to block-next.

Kevin

#3 lore raw
In reply to Anton Blanchard
Quoted 25 lines · Anton Blanchard

Initialise our maximum page size capability to 64kB and increase the page_size variable from 16 to 32 bits.

Signed-off-by Anton Blanchard <[email protected]>

--

hw/block/nvme.c +1 -0
index 1327658..aa1ed98 100644
@@ -811,6 +811,7 @@ static int nvme_init(PCIDevice *pci_dev)
     NVME_CAP_SET_AMS(n->bar.cap, 1);
     NVME_CAP_SET_TO(n->bar.cap, 0xf);
     NVME_CAP_SET_CSS(n->bar.cap, 1);
+    NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
 
     n->bar.vs = 0x00010001;
     n->bar.intmc = n->bar.intms = 0;
hw/block/nvme.h +0 -0
index 993c511..b6ccb65 100644

hw/block/nvme.h typedef struct NvmeCtrl { · line 694

Quoted 8 lines
hw/block/nvme.h +1 -1
@@ -688,7 +688,7 @@ typedef struct NvmeCtrl {
     NvmeBar      bar;
     BlockConf    conf;
 
-    uint16_t    page_size;
+    uint32_t    page_size;
     uint16_t    page_bits;
     uint16_t    max_prp_ents;
     uint16_t    cqe_size;

This should probably be a property of the device instead. If you want to change the default, you need to preserve a backwards-compatible value for pre-2.3 machine types (-M pc-i440fx-2.2, -M pc-i440fx-2.1 etc.).

Paolo

#4 lore raw
Quoted 29 lines · Paolo Bonzini
Quoted 26 lines · Anton Blanchard

Initialise our maximum page size capability to 64kB and increase the page_size variable from 16 to 32 bits.

Signed-off-by Anton Blanchard <[email protected]>

--

hw/block/nvme.c +1 -0
index 1327658..aa1ed98 100644
@@ -811,6 +811,7 @@ static int nvme_init(PCIDevice *pci_dev)
     NVME_CAP_SET_AMS(n->bar.cap, 1);
     NVME_CAP_SET_TO(n->bar.cap, 0xf);
     NVME_CAP_SET_CSS(n->bar.cap, 1);
+    NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
 
     n->bar.vs = 0x00010001;
     n->bar.intmc = n->bar.intms = 0;
hw/block/nvme.h +0 -0
index 993c511..b6ccb65 100644
@@ -688,7 +688,7 @@ typedef struct NvmeCtrl {
     NvmeBar      bar;
     BlockConf    conf;
Quoted 11 lines

hw/block/nvme.h typedef struct NvmeCtrl { · line 694

Quoted 7 lines
hw/block/nvme.h +1 -1
-    uint16_t    page_size;
+    uint32_t    page_size;
     uint16_t    page_bits;
     uint16_t    max_prp_ents;
     uint16_t    cqe_size;

This should probably be a property of the device instead. If you want to change the default, you need to preserve a backwards-compatible value for pre-2.3 machine types (-M pc-i440fx-2.2, -M pc-i440fx-2.1 etc.).

Hi Anton,
Any update on this?

Paolo has a point that changing this value would make a guest-visible hardware change. Therefore older machine types, which users might rely on, should continue to show the old value.

This is especially important with live migration because hardware should not change underneath the guest due to migration.

Stefan