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ARM: shmobile: koelsch: Fix QSPI mode of SPI-Flash into mode3

PATCH New Simon Horman 3 participants 3 messages Dec 9, 2014 – Dec 10, 2014

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#0 lore raw

PATCH 1/1 ARM: shmobile: koelsch: Fix QSPI mode of SPI-Flash into mode3

From: Hisashi Nakamura <[email protected]>

In order to change into mode3, CPOL and CPHA bit of SPCMD register of QSPI is changed. Mode3 can avoid intermediate voltage.

[horms: Updated changelog and re-ordered properties]

---

Based on the renesas-devel-20141208-v3.18 tag of my renesas tree

* Changes by Simon Horman as suggested by Geert Uytterhoeven
- Changed name from
"ARM: shmobile: koelsch: Fix SPI mode of SPI-Flash into mode3" to "ARM: shmobile: koelsch: Fix QSPI mode of SPI-Flash into mode3"
- Updated changelog to refer to QSPI instead of MSIOF
- Grouped spi-* properties

---
 arch/arm/boot/dts/r8a7791-koelsch.dts | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/boot/dts/r8a7791-koelsch.dts +2 -0
index 6938377..a9a6e37 100644
@@ -444,6 +444,8 @@
 		spi-max-frequency = <30000000>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
+		spi-cpha;
+		spi-cpol;
 		m25p,fast-read;
 
 		partition at 0 {
Signature · 1 line
2.1.3
#1 lore raw

PATCH 1/1 ARM: shmobile: koelsch: Fix QSPI mode of SPI-Flash into mode3

Quoted 8 lines · Simon Horman

From: Hisashi Nakamura <[email protected]>

In order to change into mode3, CPOL and CPHA bit of SPCMD register of QSPI is changed. Mode3 can avoid intermediate voltage.

[horms: Updated changelog and re-ordered properties]

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#2 lore raw

PATCH 1/1 ARM: shmobile: koelsch: Fix QSPI mode of SPI-Flash into mode3

Quoted 11 lines · Geert Uytterhoeven
Quoted 8 lines · Simon Horman

From: Hisashi Nakamura <[email protected]>

In order to change into mode3, CPOL and CPHA bit of SPCMD register of QSPI is changed. Mode3 can avoid intermediate voltage.

[horms: Updated changelog and re-ordered properties]

Thanks, I have queued this up.