QEMU lapic tsc deadline advancement

Add machine option and QMP commands to configure TSC deadline timer advancement.

Signed-off-by Marcelo Tosatti <[email protected]>

---
 monitor.c         |   15 ++++++++++
 qapi-schema.json  |   29 +++++++++++++++++++
 qmp-commands.hx   |   48 ++++++++++++++++++++++++++++++++
 target-i386/kvm.c |   80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 vl.c              |    4 ++
 5 files changed, 176 insertions(+)

Index: qemu.tscdeadline/qapi-schema.json
===================================================================

qapi-schema.json +19 -0

@@ -3515,3 +3515,32 @@
 # Since: 2.1
 ##
 { 'command': 'rtc-reset-reinjection' }
+
+##
+# @set-lapic-tscdeadline-advance
+#
+# This command sets the TSC deadline timer advancement.
+# This value will be subtracted from the expiration time
+# of the high resolution timer which emulates
+# TSC deadline timer.
+#
+# Useful to achieve low timer latencies.
+#
+# Only supported by KVM acceleration.
+#
+# Since: 2.3
+##
+{ 'command': 'set-lapic-tscdeadline-advance',
+  'data': { 'advance':'int' }
+}
+

qapi-schema.json +37 -0

+    lapic_tscdeadline_advance.advance_ns = advance;
+
+    return ret;
+}
+
 int kvm_arch_init(KVMState *s)
 {
     uint64_t identity_base = 0xfffbc000;
     uint64_t shadow_mem;
     int ret;
     struct utsname utsname;
+    uint32_t lapic_advance_ns;
 
     ret = kvm_get_supported_msrs(s);
     if (ret < 0) {

@@ -894,9 +919,40 @@ int kvm_arch_init(KVMState *s)
             return ret;
         }
     }
+
+    lapic_advance_ns = qemu_opt_get_number(qemu_get_machine_opts(),
+                                           "lapic-tscdeadline-advance",
+                                           0);
+    if (lapic_advance_ns) {
+        ret = kvm_set_lapic_tscdeadline(s, lapic_advance_ns);
+        if (ret) {
+            fprintf(stderr, "Set tscdeadline advance failed: %s\n",
+                    strerror(-ret));
+            return ret;
+        }
+    }
+
+
     return 0;
 }
 
+int64_t qmp_get_lapic_tscdeadline_advance(Error **errp)
+{
+    return lapic_tscdeadline_advance.advance_ns;
+}
+
+void qmp_set_lapic_tscdeadline_advance(int64_t advance, Error **errp)
+{
+    KVMState *s = kvm_state;
+    int ret;
+
+    ret = kvm_set_lapic_tscdeadline(s, advance);
+    if (ret) {
+        error_setg_errno(errp, ret, "set lapic tscdeadline failed");
+        return;
+    }
+}
+
 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 {
     lhs->selector = rhs->selector;

Index: qemu.tscdeadline/monitor.c
===================================================================

monitor.c +15 -0

@@ -5447,3 +5447,18 @@ void qmp_rtc_reset_reinjection(Error **e
     error_set(errp, QERR_FEATURE_DISABLED, "rtc-reset-reinjection");
 }
 #endif
+
+#if !defined (TARGET_I386) || !defined (CONFIG_KVM)
+int64_t qmp_get_lapic_tscdeadline_advance(Error **errp)
+{
+    error_set(errp, QERR_FEATURE_DISABLED, "get-lapic-tscdeadline-advance");
+
+    return 0;
+}
+
+void qmp_set_lapic_tscdeadline_advance(int64_t advance, Error **errp)
+{
+    error_set(errp, QERR_FEATURE_DISABLED, "set-lapic-tscdeadline-advance");
+}
+#endif
+

Index: qemu.tscdeadline/include/hw/boards.h
===================================================================

include/hw/boards.h +1 -0

@@ -133,6 +133,7 @@ struct MachineState {
     bool usb;
     char *firmware;
     bool iommu;
+    int lapi_tscdeadline_advance;
 
     ram_addr_t ram_size;
     ram_addr_t maxram_size;

Index: qemu.tscdeadline/qemu-options.hx
===================================================================

qemu-options.hx +4 -1

@@ -37,7 +37,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_mach
     "                kvm_shadow_mem=size of KVM shadow MMU\n"
     "                dump-guest-core=on|off include guest memory in a core dump (default=on)\n"
     "                mem-merge=on|off controls memory merge support (default: on)\n"
-    "                iommu=on|off controls emulated Intel IOMMU (VT-d) support (default=off)\n",
+    "                iommu=on|off controls emulated Intel IOMMU (VT-d) support (default=off)\n"
+    "                lapic-tscdeadline-advance=value controls LAPIC tscdeadline timer advancement (default=0)\n",
     QEMU_ARCH_ALL)
 STEXI
 @item -machine [type=]@var{name}[,prop=@var{value}[,...]]

@@ -66,6 +67,8 @@ the host, de-duplicates identical memory
 (enabled by default).
 @item iommu=on|off
 Enables or disables emulated Intel IOMMU (VT-d) support. The default is off.
+@item lapic-tscdeadline-advance=value
+Defines the advancement of LAPIC TSC deadline timer, in nanoseconds.
 @end table
 ETEXI
 

Index: qemu.tscdeadline/hw/core/machine.c
===================================================================

hw/core/machine.c +33 -0

@@ -72,6 +72,35 @@ static void machine_set_kvm_shadow_mem(O
     ms->kvm_shadow_mem = value;
 }
 
+static void machine_get_lapic_tscdeadline_advance(Object *obj, Visitor *v,
+                                                  void *opaque,
+                                                  const char *name,
+                                                  Error **errp)
+{
+    MachineState *ms = MACHINE(obj);
+    int64_t value = ms->kvm_shadow_mem;
+
+    visit_type_int(v, &value, name, errp);
+}
+
+static void machine_set_lapic_tscdeadline_advance(Object *obj, Visitor *v,
+                                                  void *opaque,
+                                                  const char *name,
+                                                  Error **errp)
+{
+    MachineState *ms = MACHINE(obj);
+    Error *error = NULL;
+    int64_t value;
+
+    visit_type_int(v, &value, name, &error);
+    if (error) {
+        error_propagate(errp, error);
+        return;
+    }
+
+    ms->lapi_tscdeadline_advance = value;
+}
+
 static char *machine_get_kernel(Object *obj, Error **errp)
 {
     MachineState *ms = MACHINE(obj);

@@ -299,6 +328,10 @@ static void machine_initfn(Object *obj)
                         machine_get_kvm_shadow_mem,
                         machine_set_kvm_shadow_mem,
                         NULL, NULL, NULL);
+    object_property_add(obj, "lapic-tscdeadline-advance", "int",
+                        machine_get_lapic_tscdeadline_advance,
+                        machine_set_lapic_tscdeadline_advance,
+                        NULL, NULL, NULL);
     object_property_add_str(obj, "kernel",
                             machine_get_kernel, machine_set_kernel, NULL);
     object_property_add_str(obj, "initrd",

Quoted 45 lines · Marcelo Tosatti

Add machine option and QMP commands to configure TSC deadline timer advancement.

Signed-off-by Marcelo Tosatti <[email protected]>

---
 monitor.c         |   15 ++++++++++
 qapi-schema.json  |   29 +++++++++++++++++++
 qmp-commands.hx   |   48 ++++++++++++++++++++++++++++++++
 target-i386/kvm.c |   80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 vl.c              |    4 ++
 5 files changed, 176 insertions(+)

Index: qemu.tscdeadline/qapi-schema.json
===================================================================

qapi-schema.json +24 -0

@@ -3515,3 +3515,32 @@
 # Since: 2.1
 ##
 { 'command': 'rtc-reset-reinjection' }
+
+##
+# @set-lapic-tscdeadline-advance
+#
+# This command sets the TSC deadline timer advancement.
+# This value will be subtracted from the expiration time
+# of the high resolution timer which emulates
+# TSC deadline timer.
+#
+# Useful to achieve low timer latencies.
+#
+# Only supported by KVM acceleration.
+#
+# Since: 2.3
+##
+{ 'command': 'set-lapic-tscdeadline-advance',
+  'data': { 'advance':'int' }
+}
+
+##
+# @get-lapic-tscdeadline-advance
+#
+# This command gets the TSC deadline timer advancement.
+#

qapi-schema.json line 3546

Quoted 5 lines

qapi-schema.json +5 -0

+# Only supported by KVM acceleration.
+#
+# Since: 2.3
+##
+{ 'command': 'get-lapic-tscdeadline-advance', 'returns': 'int' }

Please add an object property to the x86 CPU object. It can then be configured with "-global" on the command line.

qapi-schema.json

Quoted 5 lines

qapi-schema.json +4 -0

+    ret = kvm_vm_ioctl(s, KVM_SET_TSCDEADLINE_ADVANCE, &adv);
+    if (ret < 0) {
+        return ret;
+    }

Please use KVM_GET/SET_ONE_REG instead of introducing a new set of ioctls.

Paolo

Quoted 2 lines

Please add an object property to the x86 CPU object. It can then be configured with "-global" on the command line.

Don't want to allow individual values for different CPUs. It is a per-VM property.

Quoted 3 lines · Marcelo Tosatti

Quoted 2 lines

Please add an object property to the x86 CPU object. It can then be configured with "-global" on the command line.

Quoted 2 lines

Don't want to allow individual values for different CPUs. It is a per-VM property.

Why? It can cause busy waiting, it would make sense to make it stricter for realtime CPUs and leave 0 for non-realtime CPUs.

Paolo

Quoted 9 lines · Paolo Bonzini

Quoted 5 lines · Marcelo Tosatti

Quoted 2 lines

Please add an object property to the x86 CPU object. It can then be configured with "-global" on the command line.

Don't want to allow individual values for different CPUs. It is a per-VM property.

Quoted 4 lines

Why? It can cause busy waiting, it would make sense to make it stricter for realtime CPUs and leave 0 for non-realtime CPUs.

Paolo

HW timer behaviour should be consistent across CPUs, IMO.

Quoted 15 lines · Marcelo Tosatti

Quoted 13 lines · Paolo Bonzini

Quoted 5 lines · Marcelo Tosatti

Quoted 2 lines

Please add an object property to the x86 CPU object. It can then be configured with "-global" on the command line.

Don't want to allow individual values for different CPUs. It is a per-VM property.

Why? It can cause busy waiting, it would make sense to make it stricter for realtime CPUs and leave 0 for non-realtime CPUs.

Paolo

Quoted 1 line

HW timer behaviour should be consistent across CPUs, IMO.

It's not going to be anyway. Cache line bounces, frequency scaling, presence of higher-priority RT tasks, etc. can cause different response for one CPU over the others.

Paolo

Quoted 16 lines · Paolo Bonzini

Quoted 13 lines · Marcelo Tosatti

Quoted 11 lines · Paolo Bonzini

Quoted 5 lines · Marcelo Tosatti

Quoted 2 lines

Please add an object property to the x86 CPU object. It can then be configured with "-global" on the command line.

Don't want to allow individual values for different CPUs. It is a per-VM property.

Why? It can cause busy waiting, it would make sense to make it stricter for realtime CPUs and leave 0 for non-realtime CPUs.

Quoted 5 lines

Quoted 1 line

HW timer behaviour should be consistent across CPUs, IMO.

It's not going to be anyway. Cache line bounces, frequency scaling, presence of higher-priority RT tasks, etc. can cause different response for one CPU over the others.

OK i'll change it to per-CPU.

Well, my preferred choice would be automatic adjustment with a module parameter. If we need manual tuning, per-CPU would be my choice, but automatic is nicer anyway. :)

2014-12-10 18:55+0100, Paolo Bonzini:

Quoted 3 lines

Well, my preferred choice would be automatic adjustment with a module parameter. If we need manual tuning, per-CPU would be my choice, but automatic is nicer anyway. :)

I agree with Paolo, and think it would be better not to touch QEMU ... it makes little sense to migrate this value and it is probably going to be quite similar on every CPU, so a writeable module parameter is a better starting point. (We can always turn it into a nightmare later.)

Add machine option and QMP commands to configure TSC deadline timer advancement.

Signed-off-by Marcelo Tosatti <[email protected]>

---