drm/i915/chv: Use timeout mode for RC6 on chv
Subsystems (2)
PATCH 1/4 drm/i915/chv: Use timeout mode for RC6 on chv
From: Deepak S <[email protected]>
Higher RC6 residency is observed using timeout mode instead of EI mode. It's Recommended to use TO Method for RC6.
--- drivers/gpu/drm/i915/intel_pm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/intel_pm.c +3 -2
@@ -4689,7 +4689,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -I915_WRITE (GEN6_RC6_THRESHOLD ,50000 );/* 50/125ms per EI */ +/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL,
@@ -4703,7 +4704,7 @@ static void cherryview_enable_rps(struct drm_device *dev)/* 3: Enable RC6 */ if ((intel_enable_rc6 (dev) &INTEL_RC6_ENABLE ) && (pcbr >>VLV_PCBR_ADDR_SHIFT )) - rc6_mode =GEN6_RC_CTL_EI_MODE (1 ); + rc6_mode =GEN7_RC_CTL_TO_MODE ;I915_WRITE (GEN6_RC_CONTROL , rc6_mode);
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PATCH 2/4 drm/i915/chv: Populate total EU count on Cherryview
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Based upon a patch from Jeff, but reworked to only store eu_total and avoid sending info to userspace
--- drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 3 files changed, 23 insertions(+)
drivers/gpu/drm/i915/i915_dma.c +11 -0
@@ -598,6 +598,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes =0 ; } } + +if (IS_CHERRYVIEW (dev)) { +u32 fuse, mask_eu; + + fuse =I915_READ (CHV_FUSE_GT ); + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | +CHV_FGT_EU_DIS_SS0_R1_MASK | +CHV_FGT_EU_DIS_SS1_R0_MASK | +CHV_FGT_EU_DIS_SS1_R1_MASK ); + info->eu_total =16 -hweight32 (mask_eu); + } }/**
drivers/gpu/drm/i915/i915_drv.h +1 -0
@@ -624,6 +624,7 @@ struct intel_device_info {int trans_offsets[I915_MAX_TRANSCODERS ];int palette_offsets[I915_MAX_PIPES ];int cursor_offsets[I915_MAX_PIPES ]; +unsigned int eu_total; };#undef DEFINE_FLAG
drivers/gpu/drm/i915/i915_reg.h +11 -0
@@ -1466,6 +1466,17 @@ enum punit_power_well {#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT 0x182168 +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf<<CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf<<CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf<<CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf<<CHV_FGT_EU_DIS_SS1_R1_SHIFT) +#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Jani Nikula
maintainerRe: [PATCH 2/4] drm/i915/chv: Populate total EU count on Cherryview
Quoted 57 lines · On Fri, 12 Dec 2014, [email protected] wrote:
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Based upon a patch from Jeff, but reworked to only store
eu_totaland avoid sending info to userspaceSigned-off-by Deepak S <[email protected]>Signed-off-by Jeff McGee <[email protected]>--- drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 3 files changed, 23 insertions(+)drivers/gpu/drm/i915/i915_dma.c +11
-0@@ -598,6 +598,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes =0 ; } } + +if (IS_CHERRYVIEW (dev)) { +u32 fuse, mask_eu; + + fuse =I915_READ (CHV_FUSE_GT ); + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | +CHV_FGT_EU_DIS_SS0_R1_MASK | +CHV_FGT_EU_DIS_SS1_R0_MASK | +CHV_FGT_EU_DIS_SS1_R1_MASK ); + info->eu_total =16 -hweight32 (mask_eu); + } }/** drivers/gpu/drm/i915/i915_drv.h +1
-0@@ -624,6 +624,7 @@ struct intel_device_info {int trans_offsets[I915_MAX_TRANSCODERS ];int palette_offsets[I915_MAX_PIPES ];int cursor_offsets[I915_MAX_PIPES ]; +unsigned int eu_total; };#undef DEFINE_FLAGdrivers/gpu/drm/i915/i915_reg.h +0
-0
drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 1470
Quoted 5 lines
drivers/gpu/drm/i915/i915_reg.h +2
-0@@ -1466,6 +1466,17 @@ enum punit_power_well {#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT 0x182168
Should this be (VLV_DISPLAY_BASE + 0x2168)?
drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 1478
Quoted 8 lines
drivers/gpu/drm/i915/i915_reg.h +8
-0+#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf<<CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf<<CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf<<CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf<<CHV_FGT_EU_DIS_SS1_R1_SHIFT)
Please add spaces both sides of "<<" if you end up sending a v2.
Quoted 11 lines
drivers/gpu/drm/i915/i915_reg.h +1
-0+#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)Signature · 6 lines
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Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 2/4] drm/i915/chv: Populate total EU count on Cherryview
Quoted 65 lines · Jani Nikula
Quoted 57 lines · On Fri, 12 Dec 2014, [email protected] wrote:
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Based upon a patch from Jeff, but reworked to only store
eu_totaland avoid sending info to userspaceSigned-off-by Deepak S <[email protected]>Signed-off-by Jeff McGee <[email protected]>--- drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 3 files changed, 23 insertions(+)drivers/gpu/drm/i915/i915_dma.c +11
-0@@ -598,6 +598,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes =0 ; } } + +if (IS_CHERRYVIEW (dev)) { +u32 fuse, mask_eu; + + fuse =I915_READ (CHV_FUSE_GT ); + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | +CHV_FGT_EU_DIS_SS0_R1_MASK | +CHV_FGT_EU_DIS_SS1_R0_MASK | +CHV_FGT_EU_DIS_SS1_R1_MASK ); + info->eu_total =16 -hweight32 (mask_eu); + } }/** drivers/gpu/drm/i915/i915_drv.h +1
-0@@ -624,6 +624,7 @@ struct intel_device_info {int trans_offsets[I915_MAX_TRANSCODERS ];int palette_offsets[I915_MAX_PIPES ];int cursor_offsets[I915_MAX_PIPES ]; +unsigned int eu_total; };#undef DEFINE_FLAGdrivers/gpu/drm/i915/i915_reg.h +0
-0drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 1470
Quoted 5 lines
drivers/gpu/drm/i915/i915_reg.h +2
-0@@ -1466,6 +1466,17 @@ enum punit_power_well {#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT 0x182168Should this be (
VLV_DISPLAY_BASE+0x2168)?
Quoted 9 lines
drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 1478
Quoted 8 lines
drivers/gpu/drm/i915/i915_reg.h +8
-0+#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf<<CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf<<CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf<<CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf<<CHV_FGT_EU_DIS_SS1_R1_SHIFT)Please add spaces both sides of "<<" if you end up sending a v2.
Thanks for review.
I will address both the comment and send v2
Quoted 11 lines
Quoted 11 lines
drivers/gpu/drm/i915/i915_reg.h +1
-0+#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)Signature · 6 lines
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PATCH v2 1/1 drm/i915/chv: Populate total EU count on Cherryview
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Based upon a patch from Jeff, but reworked to only store eu_total and avoid sending info to userspace
v2: Format register definitions (Jani)
--- drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 3 files changed, 23 insertions(+)
drivers/gpu/drm/i915/i915_dma.c +11 -0
@@ -598,6 +598,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes =0 ; } } + +if (IS_CHERRYVIEW (dev)) { +u32 fuse, mask_eu; + + fuse =I915_READ (CHV_FUSE_GT ); + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | +CHV_FGT_EU_DIS_SS0_R1_MASK | +CHV_FGT_EU_DIS_SS1_R0_MASK | +CHV_FGT_EU_DIS_SS1_R1_MASK ); + info->eu_total =16 -hweight32 (mask_eu); + } }/**
drivers/gpu/drm/i915/i915_drv.h +1 -0
@@ -624,6 +624,7 @@ struct intel_device_info {int trans_offsets[I915_MAX_TRANSCODERS ];int palette_offsets[I915_MAX_PIPES ];int cursor_offsets[I915_MAX_PIPES ]; +unsigned int eu_total; };#undef DEFINE_FLAG
drivers/gpu/drm/i915/i915_reg.h +11 -0
@@ -1466,6 +1466,17 @@ enum punit_power_well {#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) +#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
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PATCH 3/4 drm/i915: New offset for reading frequencies on CHV.
In reply to [email protected]From: Deepak S <[email protected]>
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run.
--- drivers/gpu/drm/i915/i915_drv.h | 4 +-- drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++ drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_sideband.c | 4 +-- 4 files changed, 61 insertions(+), 11 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +2 -2
@@ -3016,8 +3016,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *valint sandybridge_pcode_write (struct drm_i915_private *dev_priv,u32 mbox,u32 val);/* intel_sideband.c */ -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr); -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val); +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr); +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val);u32 vlv_nc_read (struct drm_i915_private *dev_priv,u8 addr);u32 vlv_gpio_nc_read (struct drm_i915_private *dev_priv,u32 reg);void vlv_gpio_nc_write (struct drm_i915_private *dev_priv,u32 reg,u32 val);
drivers/gpu/drm/i915/i915_reg.h +12 -0
@@ -602,6 +602,18 @@ enum punit_power_well {#define PUNIT_FUSE_BUS2 0xf6/* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5/* bits 55:48 */ +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 +#define FB_GFX_FMAX_AT_VMAX_FUSE_MASK 0xff +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 + +#define FB_GFX_GUAR_FREQ_FUSE_MASK 0xff + +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 +#define FB_GFX_FMIN_AT_VMIN_FUSE_MASK 0xff +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 +#define PUNIT_GPU_STATUS_REG 0xdb#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
drivers/gpu/drm/i915/intel_pm.c +45 -7
76 lines not on this page · raw message
drivers/gpu/drm/i915/intel_sideband.c +2 -2
@@ -75,7 +75,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,return 0 ; } -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr) +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr) {u32 val =0 ;
@@ -89,7 +89,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)return val; } -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val) +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val) {WARN_ON (!mutex_is_locked (&dev_priv->rps.hw_lock));
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 3/4] drm/i915: New offset for reading frequencies on CHV.
Quoted 34 lines · On Fri, Dec 12, 2014 at 02:18:15PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run.
Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/i915_drv.h | 4 +-- drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++ drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_sideband.c | 4 +-- 4 files changed, 61 insertions(+), 11 deletions(-)drivers/gpu/drm/i915/i915_drv.h +2
-2@@ -3016,8 +3016,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *valint sandybridge_pcode_write (struct drm_i915_private *dev_priv,u32 mbox,u32 val);/* intel_sideband.c */ -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr); -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val); +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr); +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val);u32 vlv_nc_read (struct drm_i915_private *dev_priv,u8 addr);u32 vlv_gpio_nc_read (struct drm_i915_private *dev_priv,u32 reg);void vlv_gpio_nc_write (struct drm_i915_private *dev_priv,u32 reg,u32 val);drivers/gpu/drm/i915/i915_reg.h +0
-0
drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 610
Quoted 9 lines
drivers/gpu/drm/i915/i915_reg.h +6
-0@@ -602,6 +602,18 @@ enum punit_power_well {#define PUNIT_FUSE_BUS2 0xf6/* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5/* bits 55:48 */ +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 +#define FB_GFX_FMAX_AT_VMAX_FUSE_MASK 0xff +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 +
This blank line makes me think FB_GFX_GUAR_FREQ_FUSE_MASK isn't part of this register. So best not leave such blank line here.
I have 0x3c3c3c28 in this register, which matches what I get using the old method.
drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 615
Quoted 5 lines
drivers/gpu/drm/i915/i915_reg.h +5
-0+#define FB_GFX_GUAR_FREQ_FUSE_MASK 0xff + +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 +#define FB_GFX_FMIN_AT_VMIN_FUSE_MASK 0xff +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
I have 0x69841428 here. The low 8 bits look like another freq value. What is it?
I have no docs for this stuff so can't really review apart from looking at what my hardware reports.
Actually, since all the values are 8 bits maybe it would be neater to just
#define FB_GFX_FREQ_FUSE_MASK 0xff
and use that everywhere instead of having three different definitions for the same 0xff value.
Quoted 10 lines
drivers/gpu/drm/i915/i915_reg.h +1
-0+#define PUNIT_GPU_STATUS_REG 0xdb#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xffdrivers/gpu/drm/i915/intel_pm.c +0
-0@@ -4346,11 +4346,29 @@ void gen6_update_ring_freq(struct drm_device *dev)
drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4353
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +3
-3static int cherryview_rps_max_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev; +struct intel_device_info *info;u32 val, rp0; - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; - + info = (struct intel_device_info *)&dev_priv->info;
Pointless cast. Also the assignment could be done when declaring info, and we usually use INTEL_INFO() to get at it.
drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4355
Quoted 2 lines
drivers/gpu/drm/i915/intel_pm.c +2
-0+ +if (dev->pdev->revision >=0x20 ) {
Do we really need this check? I would think it would be up to the Punit firmware version rather the stepping. My BSW has PCI rev 0x15, but with the latest BIOS both fuse registers already contain correct looking information.
drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4365
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +10
-0+ val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + +if (info->eu_total ==8 )/* (2 * 4) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT ); +else if (info->eu_total ==12 )/* (2 * 6) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT ); +else if (info->eu_total ==16 )/* (2 * 8) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT ); +else /* Setting (2 * 8) Min RP0 for any other combination */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT );
'switch (INTEL_INFO(dev)->eu_total)' perhaps?
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +6
-0+ rp0 = (rp0 &FB_GFX_FMAX_AT_VMAX_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK ; + }return rp0; }
drivers/gpu/drm/i915/intel_pm.c static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) · line 4391
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +3
-2@@ -4366,20 +4384,40 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)static int cherryview_rps_guar_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev; +struct intel_device_info *info;u32 val, rp1; - val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); - rp1 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; + info = (struct intel_device_info *)&dev_priv->info;
Unused here.
Quoted 9 lines
drivers/gpu/drm/i915/intel_pm.c +7
-0+if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + rp1 = (val &FB_GFX_GUAR_FREQ_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); + rp1 = ((val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK );
drivers/gpu/drm/i915/intel_pm.c static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) · line 4409
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +4
-0+ }return rp1; }static int cherryview_rps_min_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev; +struct intel_device_info *info;u32 val, rpn; + info = (struct intel_device_info *)&dev_priv->info;
Unused.
Quoted 21 lines
drivers/gpu/drm/i915/intel_pm.c +10
-2+ +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMIN_AT_VMIN_FUSE ); + rpn = ((val >>FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT ) & +FB_GFX_FMIN_AT_VMIN_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rpn = ((val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ); + } - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rpn = (val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) &PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ;return rpn; }drivers/gpu/drm/i915/intel_sideband.c +0
-0
drivers/gpu/drm/i915/intel_sideband.c static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, · line 78
Quoted 5 lines
drivers/gpu/drm/i915/intel_sideband.c +1
-1@@ -75,7 +75,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,return 0 ; } -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr) +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr)
Good thing you had to pass a constant. Otherwise this could have caused quite a bit of head scratching for you ;)
Quoted 14 lines
drivers/gpu/drm/i915/intel_sideband.c +1
-1{u32 val =0 ;@@ -89,7 +89,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)return val; } -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val) +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val) {WARN_ON (!mutex_is_locked (&dev_priv->rps.hw_lock));Signature · 1 line
1.9.1
Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Jani Nikula
maintainerRe: [PATCH 3/4] drm/i915: New offset for reading frequencies on CHV.
Quoted 184 lines · Ville Syrjälä
Quoted 34 lines · On Fri, Dec 12, 2014 at 02:18:15PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run.
Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/i915_drv.h | 4 +-- drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++ drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_sideband.c | 4 +-- 4 files changed, 61 insertions(+), 11 deletions(-)drivers/gpu/drm/i915/i915_drv.h +2
-2@@ -3016,8 +3016,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *valint sandybridge_pcode_write (struct drm_i915_private *dev_priv,u32 mbox,u32 val);/* intel_sideband.c */ -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr); -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val); +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr); +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val);u32 vlv_nc_read (struct drm_i915_private *dev_priv,u8 addr);u32 vlv_gpio_nc_read (struct drm_i915_private *dev_priv,u32 reg);void vlv_gpio_nc_write (struct drm_i915_private *dev_priv,u32 reg,u32 val);drivers/gpu/drm/i915/i915_reg.h +0
-0drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 610
Quoted 9 lines
drivers/gpu/drm/i915/i915_reg.h +6
-0@@ -602,6 +602,18 @@ enum punit_power_well {#define PUNIT_FUSE_BUS2 0xf6/* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5/* bits 55:48 */ +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 +#define FB_GFX_FMAX_AT_VMAX_FUSE_MASK 0xff +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 +This blank line makes me think
FB_GFX_GUAR_FREQ_FUSE_MASKisn't part of this register. So best not leave such blank line here.I have
0x3c3c3c28in this register, which matches what I get using the old method.drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 615
Quoted 5 lines
drivers/gpu/drm/i915/i915_reg.h +5
-0+#define FB_GFX_GUAR_FREQ_FUSE_MASK 0xff + +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 +#define FB_GFX_FMIN_AT_VMIN_FUSE_MASK 0xff +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8I have
0x69841428here. The low 8 bits look like another freq value. What is it?I have no docs for this stuff so can't really review apart from looking at what my hardware reports.
Actually, since all the values are 8 bits maybe it would be neater to just
#defineFB_GFX_FREQ_FUSE_MASK0xff
and use that everywhere instead of having three different definitions for the same0xffvalue.Quoted 10 lines
drivers/gpu/drm/i915/i915_reg.h +1
-0+#define PUNIT_GPU_STATUS_REG 0xdb#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xffdrivers/gpu/drm/i915/intel_pm.c +0
-0@@ -4346,11 +4346,29 @@ void gen6_update_ring_freq(struct drm_device *dev)drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4353
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +3
-3static int cherryview_rps_max_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev; +struct intel_device_info *info;u32 val, rp0; - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; - + info = (struct intel_device_info *)&dev_priv->info;Pointless cast. Also the assignment could be done when declaring info, and we usually use
INTEL_INFO()to get at it.drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4355
Quoted 2 lines
drivers/gpu/drm/i915/intel_pm.c +2
-0+ +if (dev->pdev->revision >=0x20 ) {Do we really need this check? I would think it would be up to the Punit firmware version rather the stepping. My BSW has PCI rev
0x15, but with the latest BIOS both fuse registers already contain correct looking information.drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4365
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +10
-0+ val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + +if (info->eu_total ==8 )/* (2 * 4) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT ); +else if (info->eu_total ==12 )/* (2 * 6) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT ); +else if (info->eu_total ==16 )/* (2 * 8) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT ); +else /* Setting (2 * 8) Min RP0 for any other combination */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT );'switch (INTEL_INFO(dev)->eu_total)' perhaps?
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +6
-0+ rp0 = (rp0 &FB_GFX_FMAX_AT_VMAX_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK ; + }return rp0; }drivers/gpu/drm/i915/intel_pm.c static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) · line 4391
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +3
-2@@ -4366,20 +4384,40 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)static int cherryview_rps_guar_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev; +struct intel_device_info *info;u32 val, rp1; - val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); - rp1 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; + info = (struct intel_device_info *)&dev_priv->info;Unused here.
Quoted 9 lines
drivers/gpu/drm/i915/intel_pm.c +7
-0+if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + rp1 = (val &FB_GFX_GUAR_FREQ_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); + rp1 = ((val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK );drivers/gpu/drm/i915/intel_pm.c static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) · line 4409
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +4
-0+ }return rp1; }static int cherryview_rps_min_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev; +struct intel_device_info *info;u32 val, rpn; + info = (struct intel_device_info *)&dev_priv->info;Unused.
Quoted 24 lines
drivers/gpu/drm/i915/intel_pm.c +10
-2+ +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMIN_AT_VMIN_FUSE ); + rpn = ((val >>FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT ) & +FB_GFX_FMIN_AT_VMIN_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rpn = ((val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ); + } - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rpn = (val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) &PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ;return rpn; }drivers/gpu/drm/i915/intel_sideband.c +0
-0@@ -75,7 +75,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,return 0 ; }
Quoted 5 lines
drivers/gpu/drm/i915/intel_sideband.c static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, · line 78
Quoted 2 lines
drivers/gpu/drm/i915/intel_sideband.c +1
-1-u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr) +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr)Good thing you had to pass a constant. Otherwise this could have caused quite a bit of head scratching for you ;)
This is the kind of thing that really should be a separate fix. If, for any reason, we need to revert the rest, we'll still want this.
BR,
Jani.
Quoted 23 lines
Quoted 15 lines
drivers/gpu/drm/i915/intel_sideband.c +1
-1{u32 val =0 ;@@ -89,7 +89,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)return val; } -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val) +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val) {WARN_ON (!mutex_is_locked (&dev_priv->rps.hw_lock));Signature · 1 line
1.9.1Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 3/4] drm/i915: New offset for reading frequencies on CHV.
Quoted 181 lines · Jani Nikula
Quoted 176 lines · Ville Syrjälä
Quoted 34 lines · On Fri, Dec 12, 2014 at 02:18:15PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run.
Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/i915_drv.h | 4 +-- drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++ drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_sideband.c | 4 +-- 4 files changed, 61 insertions(+), 11 deletions(-)drivers/gpu/drm/i915/i915_drv.h +2
-2@@ -3016,8 +3016,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *valint sandybridge_pcode_write (struct drm_i915_private *dev_priv,u32 mbox,u32 val);/* intel_sideband.c */ -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr); -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val); +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr); +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val);u32 vlv_nc_read (struct drm_i915_private *dev_priv,u8 addr);u32 vlv_gpio_nc_read (struct drm_i915_private *dev_priv,u32 reg);void vlv_gpio_nc_write (struct drm_i915_private *dev_priv,u32 reg,u32 val);drivers/gpu/drm/i915/i915_reg.h +0
-0drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 610
Quoted 9 lines
drivers/gpu/drm/i915/i915_reg.h +6
-0@@ -602,6 +602,18 @@ enum punit_power_well {#define PUNIT_FUSE_BUS2 0xf6/* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5/* bits 55:48 */ +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 +#define FB_GFX_FMAX_AT_VMAX_FUSE_MASK 0xff +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 +This blank line makes me think
FB_GFX_GUAR_FREQ_FUSE_MASKisn't part of this register. So best not leave such blank line here.I have
0x3c3c3c28in this register, which matches what I get using the old method.drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 615
Quoted 5 lines
drivers/gpu/drm/i915/i915_reg.h +5
-0+#define FB_GFX_GUAR_FREQ_FUSE_MASK 0xff + +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 +#define FB_GFX_FMIN_AT_VMIN_FUSE_MASK 0xff +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8I have
0x69841428here. The low 8 bits look like another freq value. What is it?I have no docs for this stuff so can't really review apart from looking at what my hardware reports.
Actually, since all the values are 8 bits maybe it would be neater to just
#defineFB_GFX_FREQ_FUSE_MASK0xff
and use that everywhere instead of having three different definitions for the same0xffvalue.Quoted 10 lines
drivers/gpu/drm/i915/i915_reg.h +1
-0+#define PUNIT_GPU_STATUS_REG 0xdb#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xffdrivers/gpu/drm/i915/intel_pm.c +0
-0@@ -4346,11 +4346,29 @@ void gen6_update_ring_freq(struct drm_device *dev)drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4353
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +3
-3static int cherryview_rps_max_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev; +struct intel_device_info *info;u32 val, rp0; - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; - + info = (struct intel_device_info *)&dev_priv->info;Pointless cast. Also the assignment could be done when declaring info, and we usually use
INTEL_INFO()to get at it.drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4355
Quoted 2 lines
drivers/gpu/drm/i915/intel_pm.c +2
-0+ +if (dev->pdev->revision >=0x20 ) {Do we really need this check? I would think it would be up to the Punit firmware version rather the stepping. My BSW has PCI rev
0x15, but with the latest BIOS both fuse registers already contain correct looking information.drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4365
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +10
-0+ val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + +if (info->eu_total ==8 )/* (2 * 4) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT ); +else if (info->eu_total ==12 )/* (2 * 6) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT ); +else if (info->eu_total ==16 )/* (2 * 8) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT ); +else /* Setting (2 * 8) Min RP0 for any other combination */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT );'switch (INTEL_INFO(dev)->eu_total)' perhaps?
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +6
-0+ rp0 = (rp0 &FB_GFX_FMAX_AT_VMAX_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK ; + }return rp0; }drivers/gpu/drm/i915/intel_pm.c static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) · line 4391
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +3
-2@@ -4366,20 +4384,40 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)static int cherryview_rps_guar_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev; +struct intel_device_info *info;u32 val, rp1; - val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); - rp1 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; + info = (struct intel_device_info *)&dev_priv->info;Unused here.
Quoted 8 lines
drivers/gpu/drm/i915/intel_pm.c +7
-0+if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + rp1 = (val &FB_GFX_GUAR_FREQ_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); + rp1 = ((val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK );drivers/gpu/drm/i915/intel_pm.c static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) · line 4409
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +4
-0+ }return rp1; }static int cherryview_rps_min_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev; +struct intel_device_info *info;u32 val, rpn; + info = (struct intel_device_info *)&dev_priv->info;Unused.
Quoted 24 lines
drivers/gpu/drm/i915/intel_pm.c +10
-2+ +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMIN_AT_VMIN_FUSE ); + rpn = ((val >>FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT ) & +FB_GFX_FMIN_AT_VMIN_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rpn = ((val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ); + } - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rpn = (val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) &PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ;return rpn; }drivers/gpu/drm/i915/intel_sideband.c +0
-0@@ -75,7 +75,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,return 0 ; }Quoted 4 lines
drivers/gpu/drm/i915/intel_sideband.c static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, · line 78
Quoted 2 lines
drivers/gpu/drm/i915/intel_sideband.c +1
-1-u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr) +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr)Good thing you had to pass a constant. Otherwise this could have caused quite a bit of head scratching for you ;)
Quoted 5 lines
This is the kind of thing that really should be a separate fix. If, for any reason, we need to revert the rest, we'll still want this.
BR,
Jani.
Agreed, Better to have a separate patch :)
Quoted 12 lines
Quoted 12 lines
Quoted 12 lines
drivers/gpu/drm/i915/intel_sideband.c +1
-1{u32 val =0 ;@@ -89,7 +89,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)return val; } -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val) +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val) {WARN_ON (!mutex_is_locked (&dev_priv->rps.hw_lock));
Quoted 9 lines
Quoted 9 lines
Quoted 2 lines
Signature · 1 line
1.9.1Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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v2 cover Use new turbo offset for chv production system
From: Deepak S <[email protected]>
CHV/BSW production system has new turbo offset to read different freq. This series adds the support.
Deepak S (3):
drm/i915/chv: Populate total EU count on Cherryview drm/i915: Increase the range of sideband address. drm/i915: New offset for reading frequencies on CHV.
drivers/gpu/drm/i915/i915_dma.c | 11 ++++++++ drivers/gpu/drm/i915/i915_drv.h | 5 ++-- drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 53 +++++++++++++++++++++++++++++------ drivers/gpu/drm/i915/intel_sideband.c | 4 +-- 5 files changed, 81 insertions(+), 12 deletions(-)
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v2 1/3 drm/i915/chv: Populate total EU count on Cherryview
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Based upon a patch from Jeff, but reworked to only store eu_total and avoid sending info to userspace
v2: Format register definitions (Jani)
--- drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 3 files changed, 23 insertions(+)
drivers/gpu/drm/i915/i915_dma.c +11 -0
@@ -601,6 +601,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes =0 ; } } + +if (IS_CHERRYVIEW (dev)) { +u32 fuse, mask_eu; + + fuse =I915_READ (CHV_FUSE_GT ); + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | +CHV_FGT_EU_DIS_SS0_R1_MASK | +CHV_FGT_EU_DIS_SS1_R0_MASK | +CHV_FGT_EU_DIS_SS1_R1_MASK ); + info->eu_total =16 -hweight32 (mask_eu); + } }/**
drivers/gpu/drm/i915/i915_drv.h +1 -0
@@ -653,6 +653,7 @@ struct intel_device_info {int trans_offsets[I915_MAX_TRANSCODERS ];int palette_offsets[I915_MAX_PIPES ];int cursor_offsets[I915_MAX_PIPES ]; +unsigned int eu_total; };#undef DEFINE_FLAG
drivers/gpu/drm/i915/i915_reg.h +11 -0
@@ -1471,6 +1471,17 @@ enum punit_power_well {#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) +#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
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Re: [PATCH v2 1/3] drm/i915/chv: Populate total EU count on Cherryview
Quoted 79 lines · On Fri, Jan 16, 2015 at 08:42:16PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Based upon a patch from Jeff, but reworked to only store
eu_totaland avoid sending info to userspacev2: Format register definitions (Jani)
Signed-off-by Deepak S <[email protected]>Signed-off-by Jeff McGee <[email protected]>--- drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 3 files changed, 23 insertions(+)drivers/gpu/drm/i915/i915_dma.c +11
-0@@ -601,6 +601,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes =0 ; } } + +if (IS_CHERRYVIEW (dev)) { +u32 fuse, mask_eu; + + fuse =I915_READ (CHV_FUSE_GT ); + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | +CHV_FGT_EU_DIS_SS0_R1_MASK | +CHV_FGT_EU_DIS_SS1_R0_MASK | +CHV_FGT_EU_DIS_SS1_R1_MASK ); + info->eu_total =16 -hweight32 (mask_eu); + } }/** drivers/gpu/drm/i915/i915_drv.h +1
-0@@ -653,6 +653,7 @@ struct intel_device_info {int trans_offsets[I915_MAX_TRANSCODERS ];int palette_offsets[I915_MAX_PIPES ];int cursor_offsets[I915_MAX_PIPES ]; +unsigned int eu_total; };#undef DEFINE_FLAGdrivers/gpu/drm/i915/i915_reg.h +11
-0@@ -1471,6 +1471,17 @@ enum punit_power_well {#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) +#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)Signature · 1 line
1.9.1
Looks good to me. I'm trying to get the full version of this upstreamed, but this version is likely to be accepted first. I'll rebase the user space export portions on it if needed.
-Jeff
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Re: [PATCH v2 1/3] drm/i915/chv: Populate total EU count on Cherryview
In reply to [email protected]Quoted 7 lines · On Fri, Jan 16, 2015 at 08:42:16PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Quoted 7 lines
Based upon a patch from Jeff, but reworked to only store
eu_totaland avoid sending info to userspacev2: Format register definitions (Jani)
Signed-off-by Deepak S <[email protected]>Signed-off-by Jeff McGee <[email protected]>
Quoted 64 lines
--- drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 3 files changed, 23 insertions(+)drivers/gpu/drm/i915/i915_dma.c +11
-0@@ -601,6 +601,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes =0 ; } } + +if (IS_CHERRYVIEW (dev)) { +u32 fuse, mask_eu; + + fuse =I915_READ (CHV_FUSE_GT ); + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | +CHV_FGT_EU_DIS_SS0_R1_MASK | +CHV_FGT_EU_DIS_SS1_R0_MASK | +CHV_FGT_EU_DIS_SS1_R1_MASK ); + info->eu_total =16 -hweight32 (mask_eu); + } }/** drivers/gpu/drm/i915/i915_drv.h +1
-0@@ -653,6 +653,7 @@ struct intel_device_info {int trans_offsets[I915_MAX_TRANSCODERS ];int palette_offsets[I915_MAX_PIPES ];int cursor_offsets[I915_MAX_PIPES ]; +unsigned int eu_total; };#undef DEFINE_FLAGdrivers/gpu/drm/i915/i915_reg.h +11
-0@@ -1471,6 +1471,17 @@ enum punit_power_well {#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) +#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)Signature · 1 line
1.9.1
Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2 1/3] drm/i915/chv: Populate total EU count on Cherryview
In reply to [email protected]Quoted 7 lines · On Fri, Jan 16, 2015 at 08:42:16PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Quoted 7 lines
Based upon a patch from Jeff, but reworked to only store
eu_totaland avoid sending info to userspacev2: Format register definitions (Jani)
Signed-off-by Deepak S <[email protected]>Signed-off-by Jeff McGee <[email protected]>
This isn't really how sob works. The last line _must_ be the person who last touched the patch, otherwise you're doing it wrong. Since this patch doesn't seem to be from Jeff I've dropped his sobline and converted to an ack.
Really if you just want to acknowledge people who have contributed to a patch (e.g. you've based your patch on some version of theirs) do that in the commit message + Cc:
-Daniel
Quoted 65 lines
--- drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 3 files changed, 23 insertions(+)drivers/gpu/drm/i915/i915_dma.c +11
-0@@ -601,6 +601,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes =0 ; } } + +if (IS_CHERRYVIEW (dev)) { +u32 fuse, mask_eu; + + fuse =I915_READ (CHV_FUSE_GT ); + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | +CHV_FGT_EU_DIS_SS0_R1_MASK | +CHV_FGT_EU_DIS_SS1_R0_MASK | +CHV_FGT_EU_DIS_SS1_R1_MASK ); + info->eu_total =16 -hweight32 (mask_eu); + } }/** drivers/gpu/drm/i915/i915_drv.h +1
-0@@ -653,6 +653,7 @@ struct intel_device_info {int trans_offsets[I915_MAX_TRANSCODERS ];int palette_offsets[I915_MAX_PIPES ];int cursor_offsets[I915_MAX_PIPES ]; +unsigned int eu_total; };#undef DEFINE_FLAGdrivers/gpu/drm/i915/i915_reg.h +11
-0@@ -1471,6 +1471,17 @@ enum punit_power_well {#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) +#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)Signature · 1 line
1.9.1
Signature · 7 lines
Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2 1/3] drm/i915/chv: Populate total EU count on Cherryview
Quoted 20 lines · Daniel Vetter
Quoted 7 lines · On Fri, Jan 16, 2015 at 08:42:16PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Quoted 7 lines
Based upon a patch from Jeff, but reworked to only store
eu_totaland avoid sending info to userspacev2: Format register definitions (Jani)
Signed-off-by Deepak S <[email protected]>Signed-off-by Jeff McGee <[email protected]>This isn't really how sob works. The last line _must_ be the person who last touched the patch, otherwise you're doing it wrong. Since this patch doesn't seem to be from Jeff I've dropped his sobline and converted to an ack.
Quoted 4 lines
Really if you just want to acknowledge people who have contributed to a patch (e.g. you've based your patch on some version of theirs) do that in the commit message + Cc:
-Daniel
Oh Sorry. I was not aware of this. I will follow the guidelines in future patch submission.
Quoted 57 lines
Quoted 57 lines
--- drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 3 files changed, 23 insertions(+)drivers/gpu/drm/i915/i915_dma.c +11
-0@@ -601,6 +601,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes =0 ; } } + +if (IS_CHERRYVIEW (dev)) { +u32 fuse, mask_eu; + + fuse =I915_READ (CHV_FUSE_GT ); + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | +CHV_FGT_EU_DIS_SS0_R1_MASK | +CHV_FGT_EU_DIS_SS1_R0_MASK | +CHV_FGT_EU_DIS_SS1_R1_MASK ); + info->eu_total =16 -hweight32 (mask_eu); + } }/** drivers/gpu/drm/i915/i915_drv.h +1
-0@@ -653,6 +653,7 @@ struct intel_device_info {int trans_offsets[I915_MAX_TRANSCODERS ];int palette_offsets[I915_MAX_PIPES ];int cursor_offsets[I915_MAX_PIPES ]; +unsigned int eu_total; };#undef DEFINE_FLAGdrivers/gpu/drm/i915/i915_reg.h +9
-0@@ -1471,6 +1471,17 @@ enum punit_power_well {#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
Quoted 8 lines
Quoted 8 lines
drivers/gpu/drm/i915/i915_reg.h +2
-0+#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) +#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)Signature · 1 line
1.9.1
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Re: [PATCH v2 1/3] drm/i915/chv: Populate total EU count on Cherryview
Quoted 22 lines · Deepak S
Quoted 20 lines · Daniel Vetter
Quoted 7 lines · On Fri, Jan 16, 2015 at 08:42:16PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0
Quoted 7 lines
Based upon a patch from Jeff, but reworked to only store
eu_totaland avoid sending info to userspacev2: Format register definitions (Jani)
Signed-off-by Deepak S <[email protected]>Signed-off-by Jeff McGee <[email protected]>This isn't really how sob works. The last line _must_ be the person who last touched the patch, otherwise you're doing it wrong. Since this patch doesn't seem to be from Jeff I've dropped his sobline and converted to an ack.
Quoted 6 lines
Quoted 4 lines
Really if you just want to acknowledge people who have contributed to a patch (e.g. you've based your patch on some version of theirs) do that in the commit message + Cc:
-DanielOh Sorry. I was not aware of this. I will follow the guidelines in future patch submission.
Yeah I think most examples of sob abuse come from vpg display, so updating your guidelines would be good.
-Daniel
Signature · 7 lines
Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v2 2/3 drm/i915: Increase the range of sideband address.
In reply to [email protected]From: Deepak S <[email protected]>
Looks like latest BSW/CHV production system has sideband address > 128. Use u32 data types to cover new offset/address range :)
--- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/intel_sideband.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +2 -2
@@ -3130,8 +3130,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *valint sandybridge_pcode_write (struct drm_i915_private *dev_priv,u32 mbox,u32 val);/* intel_sideband.c */ -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr); -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val); +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr); +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val);u32 vlv_nc_read (struct drm_i915_private *dev_priv,u8 addr);u32 vlv_gpio_nc_read (struct drm_i915_private *dev_priv,u32 reg);void vlv_gpio_nc_write (struct drm_i915_private *dev_priv,u32 reg,u32 val);
drivers/gpu/drm/i915/intel_sideband.c +2 -2
@@ -75,7 +75,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,return 0 ; } -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr) +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr) {u32 val =0 ;
@@ -89,7 +89,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)return val; } -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val) +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val) {WARN_ON (!mutex_is_locked (&dev_priv->rps.hw_lock));
Signature · 6 lines
1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2 2/3] drm/i915: Increase the range of sideband address.
Quoted 6 lines · On Fri, Jan 16, 2015 at 08:42:17PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Looks like latest BSW/CHV production system has sideband address > 128. Use u32 data types to cover new offset/address range :)
Signed-off-by Deepak S <[email protected]>
Quoted 44 lines
--- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/intel_sideband.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)drivers/gpu/drm/i915/i915_drv.h +2
-2@@ -3130,8 +3130,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *valint sandybridge_pcode_write (struct drm_i915_private *dev_priv,u32 mbox,u32 val);/* intel_sideband.c */ -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr); -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val); +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr); +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val);u32 vlv_nc_read (struct drm_i915_private *dev_priv,u8 addr);u32 vlv_gpio_nc_read (struct drm_i915_private *dev_priv,u32 reg);void vlv_gpio_nc_write (struct drm_i915_private *dev_priv,u32 reg,u32 val);drivers/gpu/drm/i915/intel_sideband.c +2
-2@@ -75,7 +75,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,return 0 ; } -u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr) +u32 vlv_punit_read (struct drm_i915_private *dev_priv,u32 addr) {u32 val =0 ;@@ -89,7 +89,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)return val; } -void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val) +void vlv_punit_write (struct drm_i915_private *dev_priv,u32 addr,u32 val) {WARN_ON (!mutex_is_locked (&dev_priv->rps.hw_lock));Signature · 1 line
1.9.1
Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v2 3/3 drm/i915: New offset for reading frequencies on CHV.
In reply to [email protected]From: Deepak S <[email protected]>
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run.
v2: reuse mask definitions & INTEL_INFO() to get device info (Ville)
--- drivers/gpu/drm/i915/i915_reg.h | 9 +++++++ drivers/gpu/drm/i915/intel_pm.c | 53 ++++++++++++++++++++++++++++++++++------- 2 files changed, 54 insertions(+), 8 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +9 -0
@@ -605,6 +605,15 @@ enum punit_power_well {#define PUNIT_FUSE_BUS2 0xf6/* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5/* bits 55:48 */ +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 +#define FB_GFX_FREQ_FUSE_MASK 0xff +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 + +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 +#define PUNIT_GPU_STATUS_REG 0xdb#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
drivers/gpu/drm/i915/intel_pm.c +45 -8
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2 3/3] drm/i915: New offset for reading frequencies on CHV.
Quoted 45 lines · On Fri, Jan 16, 2015 at 08:42:18PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run.
v2: reuse mask definitions &
INTEL_INFO()to get device info (Ville)Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 9 +++++++ drivers/gpu/drm/i915/intel_pm.c | 53 ++++++++++++++++++++++++++++++++++------- 2 files changed, 54 insertions(+), 8 deletions(-)drivers/gpu/drm/i915/i915_reg.h +9
-0@@ -605,6 +605,15 @@ enum punit_power_well {#define PUNIT_FUSE_BUS2 0xf6/* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5/* bits 55:48 */ +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 +#define FB_GFX_FREQ_FUSE_MASK 0xff +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 + +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 +#define PUNIT_GPU_STATUS_REG 0xdb#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xffdrivers/gpu/drm/i915/intel_pm.c +1
-0@@ -4338,11 +4338,32 @@ void gen6_update_ring_freq(struct drm_device *dev)static int cherryview_rps_max_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev;u32 val, rp0;
drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4350
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +7
-3- val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; - +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + +switch (INTEL_INFO (dev)->eu_total) { +case 8 : +/* (2 * 4) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT );
break;
drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4353
Quoted 3 lines
drivers/gpu/drm/i915/intel_pm.c +3
-0+case 12 : +/* (2 * 6) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT );
break;
drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4358
Quoted 5 lines
drivers/gpu/drm/i915/intel_pm.c +5
-0+case 16 : +/* (2 * 8) config */ +default : +/* Setting (2 * 8) Min RP0 for any other combination */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT );
Maybe break; here too if you feel like it :)
Hmm. Now that I started to think about it, might we be expecting EUs to be fused off in some other configurations? In that case the switch statement might be not be the best idea, or we'd need to use the gnu case range extension. But we can maybe worry about that later since it might require more investigative work, or I might be totally off base here anyway, and we should get this patch in ASAP.
So if you add the missing break statements this patch can have:
Quoted 55 lines
drivers/gpu/drm/i915/intel_pm.c +29
-5+ } + rp0 = (rp0 &FB_GFX_FREQ_FUSE_MASK ); + }else { +/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK ; + }return rp0; }@@ -4358,20 +4379,36 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)static int cherryview_rps_guar_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev;u32 val, rp1; - val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); - rp1 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; - +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + rp1 = (val &FB_GFX_FREQ_FUSE_MASK ); + }else { +/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); + rp1 = ((val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK ); + }return rp1; }static int cherryview_rps_min_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev;u32 val, rpn; - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rpn = (val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) &PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ; +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMIN_AT_VMIN_FUSE ); + rpn = ((val >>FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT ) & +FB_GFX_FREQ_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rpn = ((val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ); + } +return rpn; }Signature · 1 line
1.9.1
Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2 3/3] drm/i915: New offset for reading frequencies on CHV.
Quoted 63 lines · Ville Syrjälä
Quoted 45 lines · On Fri, Jan 16, 2015 at 08:42:18PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run.
v2: reuse mask definitions &
INTEL_INFO()to get device info (Ville)Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/i915_reg.h | 9 +++++++ drivers/gpu/drm/i915/intel_pm.c | 53 ++++++++++++++++++++++++++++++++++------- 2 files changed, 54 insertions(+), 8 deletions(-)drivers/gpu/drm/i915/i915_reg.h +9
-0@@ -605,6 +605,15 @@ enum punit_power_well {#define PUNIT_FUSE_BUS2 0xf6/* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5/* bits 55:48 */ +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 +#define FB_GFX_FREQ_FUSE_MASK 0xff +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 + +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 +#define PUNIT_GPU_STATUS_REG 0xdb#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xffdrivers/gpu/drm/i915/intel_pm.c +1
-0@@ -4338,11 +4338,32 @@ void gen6_update_ring_freq(struct drm_device *dev)static int cherryview_rps_max_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev;u32 val, rp0;drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4350
Quoted 10 lines
drivers/gpu/drm/i915/intel_pm.c +7
-3- val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; - +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + +switch (INTEL_INFO (dev)->eu_total) { +case 8 : +/* (2 * 4) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT );break;
drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4353
Quoted 3 lines
drivers/gpu/drm/i915/intel_pm.c +3
-0+case 12 : +/* (2 * 6) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT );break;
Quoted 6 lines
drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 4358
Quoted 5 lines
drivers/gpu/drm/i915/intel_pm.c +5
-0+case 16 : +/* (2 * 8) config */ +default : +/* Setting (2 * 8) Min RP0 for any other combination */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT );Maybe break; here too if you feel like it :)
:) Thanks for the review
Quoted 63 lines
Hmm. Now that I started to think about it, might we be expecting EUs to be fused off in some other configurations? In that case the switch statement might be not be the best idea, or we'd need to use the gnu case range extension. But we can maybe worry about that later since it might require more investigative work, or I might be totally off base here anyway, and we should get this patch in ASAP.
So if you add the missing break statements this patch can have:
Reviewed-by Ville Syrjälä <[email protected]>Quoted 53 lines
drivers/gpu/drm/i915/intel_pm.c +29
-5+ } + rp0 = (rp0 &FB_GFX_FREQ_FUSE_MASK ); + }else { +/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK ; + }return rp0; }@@ -4358,20 +4379,36 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)static int cherryview_rps_guar_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev;u32 val, rp1; - val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); - rp1 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; - +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + rp1 = (val &FB_GFX_FREQ_FUSE_MASK ); + }else { +/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); + rp1 = ((val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK ); + }return rp1; }static int cherryview_rps_min_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev;u32 val, rpn; - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rpn = (val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) &PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ; +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMIN_AT_VMIN_FUSE ); + rpn = ((val >>FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT ) & +FB_GFX_FREQ_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rpn = ((val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ); + } +return rpn; }
Quoted 2 lines
Quoted 2 lines
Signature · 1 line
1.9.1
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v3 1/1 drm/i915: New offset for reading frequencies on CHV.
From: Deepak S <[email protected]>
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run.
v2: reuse mask definitions & INTEL_INFO() to get device info (Ville)
v3: add break in switch conditions (Ville)
--- drivers/gpu/drm/i915/i915_reg.h | 9 +++++++ drivers/gpu/drm/i915/intel_pm.c | 54 +++++++++++++++++++++++++++++++++++------ 2 files changed, 56 insertions(+), 7 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +9 -0
@@ -605,6 +605,15 @@ enum punit_power_well {#define PUNIT_FUSE_BUS2 0xf6/* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5/* bits 55:48 */ +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 +#define FB_GFX_FREQ_FUSE_MASK 0xff +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 + +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 +#define PUNIT_GPU_STATUS_REG 0xdb#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
drivers/gpu/drm/i915/intel_pm.c +47 -7
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v3] drm/i915: New offset for reading frequencies on CHV.
Quoted 6 lines · On Sat, Jan 17, 2015 at 11:05:59AM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run.
Quoted 6 lines
v2: reuse mask definitions &
INTEL_INFO()to get device info (Ville)v3: add break in switch conditions (Ville)
Signed-off-by Deepak S <[email protected]>Reviewed-by Ville Syrjälä <ville.syrjala at linux.intel.com>
All 3 patches merged, thanks.
-Daniel
Quoted 112 lines
--- drivers/gpu/drm/i915/i915_reg.h | 9 +++++++ drivers/gpu/drm/i915/intel_pm.c | 54 +++++++++++++++++++++++++++++++++++------ 2 files changed, 56 insertions(+), 7 deletions(-)drivers/gpu/drm/i915/i915_reg.h +9
-0@@ -605,6 +605,15 @@ enum punit_power_well {#define PUNIT_FUSE_BUS2 0xf6/* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5/* bits 55:48 */ +#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 +#define FB_GFX_FREQ_FUSE_MASK 0xff +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 + +#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 +#define PUNIT_GPU_STATUS_REG 0xdb#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xffdrivers/gpu/drm/i915/intel_pm.c +47
-7@@ -4338,11 +4338,35 @@ void gen6_update_ring_freq(struct drm_device *dev)static int cherryview_rps_max_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev;u32 val, rp0; - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); +switch (INTEL_INFO (dev)->eu_total) { +case 8 : +/* (2 * 4) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT ); +break ; +case 12 : +/* (2 * 6) config */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT ); +break ; +case 16 : +/* (2 * 8) config */ +default : +/* Setting (2 * 8) Min RP0 for any other combination */ + rp0 = (val >>FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT ); +break ; + } + rp0 = (rp0 &FB_GFX_FREQ_FUSE_MASK ); + }else { +/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rp0 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK ; + }return rp0; }@@ -4358,20 +4382,36 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)static int cherryview_rps_guar_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev;u32 val, rp1; - val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); - rp1 = (val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) &PUNIT_GPU_STATUS_MAX_FREQ_MASK ; - +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMAX_AT_VMAX_FUSE ); + rp1 = (val &FB_GFX_FREQ_FUSE_MASK ); + }else { +/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS ); + rp1 = ((val >>PUNIT_GPU_STATUS_MAX_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_MAX_FREQ_MASK ); + }return rp1; }static int cherryview_rps_min_freq (struct drm_i915_private *dev_priv) { +struct drm_device *dev = dev_priv->dev;u32 val, rpn; - val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); - rpn = (val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) &PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ; +if (dev->pdev->revision >=0x20 ) { + val =vlv_punit_read (dev_priv,FB_GFX_FMIN_AT_VMIN_FUSE ); + rpn = ((val >>FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT ) & +FB_GFX_FREQ_FUSE_MASK ); + }else {/* For pre-production hardware */ + val =vlv_punit_read (dev_priv,PUNIT_GPU_STATUS_REG ); + rpn = ((val >>PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT ) & +PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK ); + } +return rpn; }Signature · 1 line
1.9.1
Signature · 7 lines
Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 4/4 drm/i915: Skip gunit save/restore for cherryview
In reply to [email protected]From: Deepak S <[email protected]>
With cherryview onwards, Gunit hardware itself save and restore all the Gunit registers. Skipping the "vlv_save_gunit_s0ix_state" & "vlv_restore_gunit_s0ix_state" for cherryview in S3/S0ix sequence.
--- drivers/gpu/drm/i915/i915_drv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_drv.c +5 -2
@@ -1299,7 +1299,9 @@ static int vlv_suspend_complete(struct drm_i915_private *dev_priv) err =vlv_allow_gt_wake (dev_priv, false);if (err) goto err2; -vlv_save_gunit_s0ix_state (dev_priv); + +if (!IS_CHERRYVIEW (dev_priv->dev)) +vlv_save_gunit_s0ix_state (dev_priv); err =vlv_force_gfx_clock (dev_priv, false);if (err)
@@ -1330,7 +1332,8 @@ static int vlv_resume_prepare(struct drm_i915_private *dev_priv,*/ ret =vlv_force_gfx_clock (dev_priv, true); -vlv_restore_gunit_s0ix_state (dev_priv); +if (!IS_CHERRYVIEW (dev_priv->dev)) +vlv_restore_gunit_s0ix_state (dev_priv); err =vlv_allow_gt_wake (dev_priv, true);if (!ret)
Signature · 6 lines
1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 4/4] drm/i915: Skip gunit save/restore for cherryview
Quoted 7 lines · On Fri, Dec 12, 2014 at 02:18:16PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
With cherryview onwards, Gunit hardware itself save and restore all the Gunit registers. Skipping the "
vlv_save_gunit_s0ix_state" & "vlv_restore_gunit_s0ix_state" for cherryview in S3/S0ix sequence.Signed-off-by Deepak S <[email protected]>
I had the same patch tucked away somewhere, but didn't bother to send it since I've not yet looked into s0ix. In any case the docs agree with this so:
Quoted 31 lines
--- drivers/gpu/drm/i915/i915_drv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_drv.c +5
-2@@ -1299,7 +1299,9 @@ static int vlv_suspend_complete(struct drm_i915_private *dev_priv) err =vlv_allow_gt_wake (dev_priv, false);if (err) goto err2; -vlv_save_gunit_s0ix_state (dev_priv); + +if (!IS_CHERRYVIEW (dev_priv->dev)) +vlv_save_gunit_s0ix_state (dev_priv); err =vlv_force_gfx_clock (dev_priv, false);if (err)@@ -1330,7 +1332,8 @@ static int vlv_resume_prepare(struct drm_i915_private *dev_priv,*/ ret =vlv_force_gfx_clock (dev_priv, true); -vlv_restore_gunit_s0ix_state (dev_priv); +if (!IS_CHERRYVIEW (dev_priv->dev)) +vlv_restore_gunit_s0ix_state (dev_priv); err =vlv_allow_gt_wake (dev_priv, true);if (!ret)Signature · 1 line
1.9.1
Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 4/4] drm/i915: Skip gunit save/restore for cherryview
Quoted 7 lines · Ville Syrjälä
Quoted 6 lines · On Fri, Dec 12, 2014 at 02:18:16PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
With cherryview onwards, Gunit hardware itself save and restore all the Gunit registers. Skipping the "
vlv_save_gunit_s0ix_state" & "vlv_restore_gunit_s0ix_state" for cherryview in S3/S0ix sequence.
Quoted 7 lines
Quoted 1 line
Signed-off-by Deepak S <[email protected]>I had the same patch tucked away somewhere, but didn't bother to send it since I've not yet looked into s0ix. In any case the docs agree with this so:
Reviewed-by Ville Syrjälä <[email protected]>
Merged patch 1&4 from this series, thanks.
-Daniel
Signature · 7 lines
Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v2 1/1 drm/i915/chv: Use timeout mode for RC6 on chv
In reply to [email protected]From: Deepak S <[email protected]>
Higher RC6 residency is observed using timeout mode instead of EI mode. It's Recommended to use TO Method for RC6.
v2: Add comment about timeout threshold. (Tom)
--- drivers/gpu/drm/i915/intel_pm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/intel_pm.c +3 -2
@@ -4689,7 +4689,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -I915_WRITE (GEN6_RC6_THRESHOLD ,50000 );/* 50/125ms per EI */ +/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL,
@@ -4703,7 +4704,7 @@ static void cherryview_enable_rps(struct drm_device *dev)/* 3: Enable RC6 */ if ((intel_enable_rc6 (dev) &INTEL_RC6_ENABLE ) && (pcbr >>VLV_PCBR_ADDR_SHIFT )) - rc6_mode =GEN6_RC_CTL_EI_MODE (1 ); + rc6_mode =GEN7_RC_CTL_TO_MODE ;I915_WRITE (GEN6_RC_CONTROL , rc6_mode);
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 6 lines · On Sat, Dec 13, 2014 at 11:43:27AM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Higher RC6 residency is observed using timeout mode instead of EI mode. It's Recommended to use TO Method for RC6.
v2: Add comment about timeout threshold. (Tom)
Yeah if TO is better let's just use it. The 1750us value is what the BIOS spec recommends, so:
Quoted 3 lines
Signed-off-by Deepak S <[email protected]>Signed-off-by Rodrigo Vivi <[email protected]>
Why is Rodrigo's sob here?
Quoted 29 lines
--- drivers/gpu/drm/i915/intel_pm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/intel_pm.c +3
-2@@ -4689,7 +4689,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -I915_WRITE (GEN6_RC6_THRESHOLD ,50000 );/* 50/125ms per EI */ +/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL,@@ -4703,7 +4704,7 @@ static void cherryview_enable_rps(struct drm_device *dev)/* 3: Enable RC6 */ if ((intel_enable_rc6 (dev) &INTEL_RC6_ENABLE ) && (pcbr >>VLV_PCBR_ADDR_SHIFT )) - rc6_mode =GEN6_RC_CTL_EI_MODE (1 ); + rc6_mode =GEN7_RC_CTL_TO_MODE ;I915_WRITE (GEN6_RC_CONTROL , rc6_mode);Signature · 1 line
1.9.1
Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 7 lines · Ville Syrjälä
Quoted 6 lines · On Sat, Dec 13, 2014 at 11:43:27AM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Higher RC6 residency is observed using timeout mode instead of EI mode. It's Recommended to use TO Method for RC6.
v2: Add comment about timeout threshold. (Tom)
Quoted 8 lines
Yeah if TO is better let's just use it. The 1750us value is what the BIOS spec recommends, so:
Reviewed-by Ville Syrjälä <[email protected]>Quoted 2 lines
Signed-off-by Deepak S <[email protected]>Signed-off-by Rodrigo Vivi <[email protected]>Why is Rodrigo's sob here?
Rodrigo had resubmitted my patch with his sob. just retained :)
Quoted 25 lines
Quoted 25 lines
--- drivers/gpu/drm/i915/intel_pm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/intel_pm.c +3
-2@@ -4689,7 +4689,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -I915_WRITE (GEN6_RC6_THRESHOLD ,50000 );/* 50/125ms per EI */ +/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL,@@ -4703,7 +4704,7 @@ static void cherryview_enable_rps(struct drm_device *dev)/* 3: Enable RC6 */ if ((intel_enable_rc6 (dev) &INTEL_RC6_ENABLE ) && (pcbr >>VLV_PCBR_ADDR_SHIFT )) - rc6_mode =GEN6_RC_CTL_EI_MODE (1 ); + rc6_mode =GEN7_RC_CTL_TO_MODE ;
Quoted 4 lines
Quoted 4 lines
drivers/gpu/drm/i915/intel_pm.c +0
-0I915_WRITE (GEN6_RC_CONTROL , rc6_mode);Signature · 1 line
1.9.1
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Quoted 12 lines · Deepak S
Quoted 10 lines · Ville Syrjälä
Quoted 6 lines · On Sat, Dec 13, 2014 at 11:43:27AM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
Higher RC6 residency is observed using timeout mode instead of EI mode. It's Recommended to use TO Method for RC6.
v2: Add comment about timeout threshold. (Tom)
Yeah if TO is better let's just use it. The 1750us value is what the BIOS spec recommends, so:
Quoted 7 lines
Quoted 5 lines
Reviewed-by Ville Syrjälä <[email protected]>Quoted 2 lines
Signed-off-by Deepak S <[email protected]>Signed-off-by Rodrigo Vivi <[email protected]>Why is Rodrigo's sob here?
Rodrigo had resubmitted my patch with his sob. just retained :)
Sob should document the path a patch took, not every possible person who every touch a patch. If you want to acknowledge indirect contributions just mention them in the commit message (E.g. "based on a patch by" or "squash in fixup from $person"). The bangalore team like to pile up sob lines especially, which isn't really how it's supposed to work.
A few things to check:
- First sob should be the original author.
- Last sob should be the submitter of the patch.
Anyway, back to merging patches for me ;-)
-Daniel
Signature · 7 lines
Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx