ARM: sun4i: SPI improvements

SPI transfers were limited to one FIFO depth, which is 64 bytes. This was an artificial limitation, however, as the hardware can handle much larger bursts. To accommodate this, we enable the interrupt when the Rx FIFO is 3/4 full, and drain the FIFO within the interrupt handler. The 3/4 ratio was chosen arbitrarily, with the intention to reduce the potential number of interrupts.

Since the SUN4I_CTL_TP bit is set, the hardware will pause transmission whenever the FIFO is full, so there is no risk of losing data if we can't service the interrupt in time.

For the Tx side, enable and use the Tx FIFO 3/4 empty interrupt to replenish the FIFO on large SPI bursts. This requires more care in when the interrupt is left enabled, as this interrupt will continually trigger when the FIFO is less than 1/4 full, even though we acknowledge it.

Signed-off-by Alexandru Gagniuc <[email protected]>

Acked-by Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/[email protected]>

---
 drivers/spi/spi-sun4i.c | 71

++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 62 insertions(+), 9 deletions(-)

drivers/spi/spi-sun4i.c +2 -0

index 85204c9..e0e2a31 100644
@@ -46,6 +46,8 @@
 #define SUN4I_CTL_TP				BIT(18)
 
 #define SUN4I_INT_CTL_REG		0x0c
+#define SUN4I_INT_CTL_RF_F34			BIT(4)
+#define SUN4I_INT_CTL_TF_E34			BIT(12)
 #define SUN4I_INT_CTL_TC			BIT(16)
 
 #define SUN4I_INT_STA_REG		0x10

drivers/spi/spi-sun4i.c +29 -4

 #define SUN4I_CLK_CTL_DRS			BIT(12)
 
+#define SUN4I_MAX_XFER_SIZE			0xffffff
+
 #define SUN4I_BURST_CNT_REG		0x20
-#define SUN4I_BURST_CNT(cnt)			((cnt) & 0xffffff)
+#define SUN4I_BURST_CNT(cnt)			((cnt) & SUN4I_MAX_XFER_SIZE)
 
 #define SUN4I_XMIT_CNT_REG		0x24
-#define SUN4I_XMIT_CNT(cnt)			((cnt) & 0xffffff)
+#define SUN4I_XMIT_CNT(cnt)			((cnt) & SUN4I_MAX_XFER_SIZE)
+
 
 #define SUN4I_FIFO_STA_REG		0x28
 #define SUN4I_FIFO_STA_RF_CNT_MASK		0x7f

@@ -96,6 +101,27 @@ static inline void sun4i_spi_write(struct sun4i_spi
 *sspi, u32 reg, u32 value) writel(value, sspi->base_addr + reg);
 }
 
+static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
+{
+	u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
+	reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
+	return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
+}
+
+static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32
 mask) +{
+	u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
+	reg |= mask;
+	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
+}
+
+static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32
 mask) +{
+	u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
+	reg &= ~mask;
+	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
+}
+
 static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
 {
 	u32 reg, cnt;

@@ -118,10 +144,13 @@ static inline void sun4i_spi_drain_fifo(struct
 sun4i_spi *sspi, int len)
 
 static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
 {
+	u32 cnt;
 	u8 byte;
 
-	if (len > sspi->len)
-		len = sspi->len;
+	/* See how much data we can fit */
+	cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
+
+	len = min3(len, (int)cnt, sspi->len);
 
 	while (len--) {

drivers/spi/spi-sun4i.c +2 -2

 		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;

@@ -174,8 +203,8 @@ static int sun4i_spi_transfer_one(struct spi_master
 *master, int ret = 0;
 	u32 reg;
 
-	/* We don't support transfer larger than the FIFO */
-	if (tfr->len > SUN4I_FIFO_DEPTH)
+	/* This is the maximum SPI burst size supported by the hardware */
+	if (tfr->len > SUN4I_MAX_XFER_SIZE)
 		return -EINVAL;
 
 	reinit_completion(&sspi->done);

drivers/spi/spi-sun4i.c +3 -2

+	/* Only enable Tx FIFO interrupt if we really need it */
+	if (tx_len > SUN4I_FIFO_DEPTH)
+		sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
 
 	/* Start the transfer */
 	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);

@@ -286,8 +318,6 @@ static int sun4i_spi_transfer_one(struct spi_master
 *master, goto out;
 	}
 
-	sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
-
 out:
 	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
 

@@ -302,10 +332,33 @@ static irqreturn_t sun4i_spi_handler(int irq, void
 *dev_id) /* Transfer complete */
 	if (status & SUN4I_INT_CTL_TC) {
 		sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);

These are based on the available SPI configurations of Cubieboard, Olimex LIME, and PcDuino. There is no pin group for SPI3, as all the boards seem to use those pins for EMAC.

Signed-off-by Alexandru Gagniuc <[email protected]>

Only SPI0 is enabled, as the schematic denotes it as the only SPI bus, while other pins are reserved for different peripherals.

Signed-off-by Alexandru Gagniuc <[email protected]>

This is a series of patches that gets SPI working in a better state on the Cubieboard. The main motivation was to use flashrom to to program SPI ROMs. There is one patch missing, which adds an spidev node on the Cubieboard. Since Maxime did not like the approach in that patch, I've left it out for now.

Quoted 4 lines · Alexandru Gagniuc

This is a series of patches that gets SPI working in a better state on the Cubieboard. The main motivation was to use flashrom to to program SPI ROMs. There is one patch missing, which adds an spidev node on the Cubieboard. Since Maxime did not like the approach in that patch, I've left it out for now.

Just to make things straight, it's not me alone that didn't like the approach.

It's both wrong on a theorical point of view to put that in the DT, since it has no hardware meaning at all (ie it doesn't describe the hardware, or the state the bootloader left the hardware in), and this has been NAKed a number of times already by Mark Brown.

See http://permalink.gmane.org/gmane.linux.kernel.spi.devel/11747 for example.