sun9i: clk: Fix compile error caused by "clk: sunxi: Give sunxi_factors_register a registers parameter"

PATCH New Hans de Goede 3 participants 4 messages Dec 12, 2014 – Dec 13, 2014

Subsystems (3)

Common clk Arm/Allwinner sunXi SoC support Arm/Allwinner SoC Clock Support

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Hans de Goede

author

2014-12-12 15:18 UTC #0 lore raw

PATCH v2 1/1 sun9i: clk: Fix compile error caused by "clk: sunxi: Give sunxi_factors_register a registers parameter"

My "clk: sunxi: Give sunxi_factors_register a registers parameter" patch did not adjust the sunxi_factors_clock register calls in the new clk-sun9i-core.c clock code, causing compilation errors. This fixes this.

Signed-off-by Hans de Goede <[email protected]>

---
 drivers/clk/sunxi/clk-sun9i-core.c | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

drivers/clk/sunxi/clk-sun9i-core.c +22 -5

index 3cb9036..110197a 100644
@@ -22,6 +22,21 @@
 
 #include "clk-factors.h"
 
+static struct clk *sun9i_factors_register(struct device_node *node,
+					  const struct factors_data *data,
+					  spinlock_t *lock)
+{
+	void __iomem *reg;
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("Could not get registers for factors-clk: %s\n",
+		       node->name);
+		return NULL;
+	}
+
+	return sunxi_factors_register(node, data, lock, reg);
+}
 
 /**
  * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL1

@@ -89,7 +104,7 @@ static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
 
 static void __init sun9i_a80_pll4_setup(struct device_node *node)
 {
-	sunxi_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
+	sun9i_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);

@@ -139,8 +154,10 @@ static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
 
 static void __init sun9i_a80_gt_setup(struct device_node *node)
 {
-	struct clk *gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
+	struct clk *gt = sun9i_factors_register(node, &sun9i_a80_gt_data,
 						&sun9i_a80_gt_lock);
+	if (!gt)
+		return;
 
 	/* The GT bus clock needs to be always enabled */
 	__clk_get(gt);

@@ -194,7 +211,7 @@ static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
 
 static void __init sun9i_a80_ahb_setup(struct device_node *node)
 {
-	sunxi_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
+	sun9i_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);

@@ -210,7 +227,7 @@ static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
 
 static void __init sun9i_a80_apb0_setup(struct device_node *node)
 {
-	sunxi_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
+	sun9i_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);

@@ -266,6 +283,6 @@ static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
 
 static void __init sun9i_a80_apb1_setup(struct device_node *node)
 {
-	sunxi_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
+	sun9i_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);

Signature · 1 line

2.1.0

Mike Turquette

Applied

2014-12-12 20:00 UTC #1 lore raw

PATCH v2 1/1 sun9i: clk: Fix compile error caused by "clk: sunxi: Give sunxi_factors_register a registers parameter"

Quoting Hans de Goede (2014-12-12 07:18:49)

Quoted 5 lines

My "clk: sunxi: Give sunxi_factors_register a registers parameter" patch did not adjust the sunxi_factors_clock register calls in the new clk-sun9i-core.c clock code, causing compilation errors. This fixes this.
Signed-off-by Hans de Goede <[email protected]>

Applied.

Regards,
Mike

Quoted 80 lines

---
 drivers/clk/sunxi/clk-sun9i-core.c | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

drivers/clk/sunxi/clk-sun9i-core.c +22 -5

index 3cb9036..110197a 100644
@@ -22,6 +22,21 @@
 
 #include "clk-factors.h"
 
+static struct clk *sun9i_factors_register(struct device_node *node,
+                                         const struct factors_data *data,
+                                         spinlock_t *lock)
+{
+       void __iomem *reg;
+
+       reg = of_iomap(node, 0);
+       if (!reg) {
+               pr_err("Could not get registers for factors-clk: %s\n",
+                      node->name);
+               return NULL;
+       }
+
+       return sunxi_factors_register(node, data, lock, reg);
+}
 
 /**
  * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL1

@@ -89,7 +104,7 @@ static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
 
 static void __init sun9i_a80_pll4_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
+       sun9i_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);

@@ -139,8 +154,10 @@ static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
 
 static void __init sun9i_a80_gt_setup(struct device_node *node)
 {
-       struct clk *gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
+       struct clk *gt = sun9i_factors_register(node, &sun9i_a80_gt_data,
                                                &sun9i_a80_gt_lock);
+       if (!gt)
+               return;
 
        /* The GT bus clock needs to be always enabled */
        __clk_get(gt);

@@ -194,7 +211,7 @@ static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
 
 static void __init sun9i_a80_ahb_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
+       sun9i_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);

@@ -210,7 +227,7 @@ static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
 
 static void __init sun9i_a80_apb0_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
+       sun9i_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);

@@ -266,6 +283,6 @@ static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
 
 static void __init sun9i_a80_apb1_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
+       sun9i_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);

Signature · 1 line

2.1.0

Mike Turquette

2014-12-12 21:35 UTC #2 lore raw

PATCH v2 1/1 sun9i: clk: Fix compile error caused by "clk: sunxi: Give sunxi_factors_register a registers parameter"

Quoting Mike Turquette (2014-12-12 12:00:03)

Quoted 8 lines

Quoting Hans de Goede (2014-12-12 07:18:49)
Quoted 5 lines
My "clk: sunxi: Give sunxi_factors_register a registers parameter" patch did not adjust the sunxi_factors_clock register calls in the new clk-sun9i-core.c clock code, causing compilation errors. This fixes this.
Signed-off-by Hans de Goede <[email protected]>
Applied.

Oops, spoke to soon. I don't have "clk: sunxi: Give sunxi_factors_register a registers parameter" in my tree yet. I was just trying to get this fix in quickly before sending out my PR. Please disregard the noise.

Regards,
Mike

Quoted 84 lines

Regards,
Mike

Quoted 80 lines

---
 drivers/clk/sunxi/clk-sun9i-core.c | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

drivers/clk/sunxi/clk-sun9i-core.c +22 -5

index 3cb9036..110197a 100644
@@ -22,6 +22,21 @@
 
 #include "clk-factors.h"
 
+static struct clk *sun9i_factors_register(struct device_node *node,
+                                         const struct factors_data *data,
+                                         spinlock_t *lock)
+{
+       void __iomem *reg;
+
+       reg = of_iomap(node, 0);
+       if (!reg) {
+               pr_err("Could not get registers for factors-clk: %s\n",
+                      node->name);
+               return NULL;
+       }
+
+       return sunxi_factors_register(node, data, lock, reg);
+}
 
 /**
  * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL1

@@ -89,7 +104,7 @@ static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
 
 static void __init sun9i_a80_pll4_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
+       sun9i_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);

@@ -139,8 +154,10 @@ static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
 
 static void __init sun9i_a80_gt_setup(struct device_node *node)
 {
-       struct clk *gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
+       struct clk *gt = sun9i_factors_register(node, &sun9i_a80_gt_data,
                                                &sun9i_a80_gt_lock);
+       if (!gt)
+               return;
 
        /* The GT bus clock needs to be always enabled */
        __clk_get(gt);

@@ -194,7 +211,7 @@ static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
 
 static void __init sun9i_a80_ahb_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
+       sun9i_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);

@@ -210,7 +227,7 @@ static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
 
 static void __init sun9i_a80_apb0_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
+       sun9i_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);

@@ -266,6 +283,6 @@ static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
 
 static void __init sun9i_a80_apb1_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
+       sun9i_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);

Signature · 1 line

2.1.0

Chen-Yu Tsai

2014-12-13 01:56 UTC #3 lore raw

PATCH v2 1/1 sun9i: clk: Fix compile error caused by "clk: sunxi: Give sunxi_factors_register a registers parameter"

Hi,

Quoted 6 lines · Mike Turquette

Quoting Mike Turquette (2014-12-12 12:00:03)
Quoted 5 lines
Quoting Hans de Goede (2014-12-12 07:18:49)
Quoted 4 lines
My "clk: sunxi: Give sunxi_factors_register a registers parameter" patch did not adjust the sunxi_factors_clock register calls in the new clk-sun9i-core.c clock code, causing compilation errors. This fixes this.

Quoted 8 lines

Quoted 3 lines
Quoted 1 line
Signed-off-by Hans de Goede <[email protected]>
Applied.
Oops, spoke to soon. I don't have "clk: sunxi: Give sunxi_factors_register a registers parameter" in my tree yet. I was just trying to get this fix in quickly before sending out my PR. Please disregard the noise.

AFAIK the sunxi_factors_register patch was queued up for 3.20. I sent a fix for the same issue a few weeks ago:

    http://www.spinics.net/lists/arm-kernel/msg381738.html

ChenYu

Quoted 84 lines

Regards,
Mike

Quoted 80 lines

---
 drivers/clk/sunxi/clk-sun9i-core.c | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

drivers/clk/sunxi/clk-sun9i-core.c +22 -6

index 3cb9036..110197a 100644
@@ -22,6 +22,21 @@
 
 #include "clk-factors.h"
 
+static struct clk *sun9i_factors_register(struct device_node *node,
+                                         const struct factors_data *data,
+                                         spinlock_t *lock)
+{
+       void __iomem *reg;
+
+       reg = of_iomap(node, 0);
+       if (!reg) {
+               pr_err("Could not get registers for factors-clk: %s\n",
+                      node->name);
+               return NULL;
+       }
+
+       return sunxi_factors_register(node, data, lock, reg);
+}
 
 /**
  * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL1

@@ -89,7 +104,7 @@ static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
 
 static void __init sun9i_a80_pll4_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
+       sun9i_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);

@@ -139,8 +154,10 @@ static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
 
 static void __init sun9i_a80_gt_setup(struct device_node *node)
 {
-       struct clk *gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
+       struct clk *gt = sun9i_factors_register(node, &sun9i_a80_gt_data,
                                                &sun9i_a80_gt_lock);
+       if (!gt)
+               return;
 
        /* The GT bus clock needs to be always enabled */
        __clk_get(gt);

@@ -194,7 +211,7 @@ static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
 
 static void __init sun9i_a80_ahb_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
+       sun9i_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);

@@ -210,7 +227,7 @@ static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
 
 static void __init sun9i_a80_apb0_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
+       sun9i_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);

@@ -266,6 +283,6 @@ static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
 
 static void __init sun9i_a80_apb1_setup(struct device_node *node)
 {
-       sunxi_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
+       sun9i_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);
--

2.1.0