arm: mxs: olinuxino: move DRAM config tuning to SPL
PATCH 1/1 arm: mxs: olinuxino: move DRAM config tuning to SPL
The weak mxs_adjust_memory_params function is called from spl_mem_init.c, so it must be linked into the SPL to have an effect. Move it from mx23_olinuxino.c to spl_boot.c.
This change was verified by reading back the register values.
---
I found this while bringing up barebox on the olinuxino with the power and memory setup code from u-boot. Thanks again to Marek for the hard work!
board/olimex/mx23_olinuxino/mx23_olinuxino.c | 30 ---------------------------- board/olimex/mx23_olinuxino/spl_boot.c | 30 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 30 deletions(-)
board/olimex/mx23_olinuxino/mx23_olinuxino.c +0 -30
@@ -78,33 +78,3 @@ int board_init(void)return 0 ; } - -/* Fine-tune the DRAM configuration. */ -void mxs_adjust_memory_params (uint32_t *dram_vals) -{ -/* Enable Auto Precharge. */ - dram_vals[3 ] |=1 <<8 ; -/* Enable Fast Writes. */ - dram_vals[5 ] |=1 <<8 ; -/* tEMRS = 3*tCK */ - dram_vals[10 ] &= ~(0x3 <<8 ); - dram_vals[10 ] |= (0x3 <<8 ); -/* CASLAT = 3*tCK */ - dram_vals[11 ] &= ~(0x3 <<0 ); - dram_vals[11 ] |= (0x3 <<0 ); -/* tCKE = 1*tCK */ - dram_vals[12 ] &= ~(0x7 <<0 ); - dram_vals[12 ] |= (0x1 <<0 ); -/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ - dram_vals[13 ] &= ~((0xf <<16 ) | (0xf <<24 ) | (0xf <<0 )); - dram_vals[13 ] |= (0x6 <<16 ) | (0x6 <<24 ) | (0x2 <<0 ); -/* tDAL = 6*tCK */ - dram_vals[15 ] &= ~(0xf <<16 ); - dram_vals[15 ] |= (0x6 <<16 ); -/* tREF = 1040*tCK */ - dram_vals[26 ] &= ~0xffff ; - dram_vals[26 ] |=0x0410 ; -/* tRAS_MAX = 9334*tCK */ - dram_vals[32 ] &= ~0xffff ; - dram_vals[32 ] |=0x2475 ; -}
board/olimex/mx23_olinuxino/spl_boot.c +30 -0
@@ -89,3 +89,33 @@ void board_init_ll(const uint32_t arg, const uint32_t *resptr) {mxs_common_spl_init (arg, resptr, iomux_setup,ARRAY_SIZE (iomux_setup)); } + +/* Fine-tune the DRAM configuration. */ +void mxs_adjust_memory_params (uint32_t *dram_vals) +{ +/* Enable Auto Precharge. */ + dram_vals[3 ] |=1 <<8 ; +/* Enable Fast Writes. */ + dram_vals[5 ] |=1 <<8 ; +/* tEMRS = 3*tCK */ + dram_vals[10 ] &= ~(0x3 <<8 ); + dram_vals[10 ] |= (0x3 <<8 ); +/* CASLAT = 3*tCK */ + dram_vals[11 ] &= ~(0x3 <<0 ); + dram_vals[11 ] |= (0x3 <<0 ); +/* tCKE = 1*tCK */ + dram_vals[12 ] &= ~(0x7 <<0 ); + dram_vals[12 ] |= (0x1 <<0 ); +/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ + dram_vals[13 ] &= ~((0xf <<16 ) | (0xf <<24 ) | (0xf <<0 )); + dram_vals[13 ] |= (0x6 <<16 ) | (0x6 <<24 ) | (0x2 <<0 ); +/* tDAL = 6*tCK */ + dram_vals[15 ] &= ~(0xf <<16 ); + dram_vals[15 ] |= (0x6 <<16 ); +/* tREF = 1040*tCK */ + dram_vals[26 ] &= ~0xffff ; + dram_vals[26 ] |=0x0410 ; +/* tRAS_MAX = 9334*tCK */ + dram_vals[32 ] &= ~0xffff ; + dram_vals[32 ] |=0x2475 ; +}
Signature · 1 line
2.1.3
PATCH 1/1 arm: mxs: olinuxino: move DRAM config tuning to SPL
Quoted 9 lines · Jan Luebbe
The weak
mxs_adjust_memory_paramsfunction is called fromspl_mem_init.c, so it must be linked into the SPL to have an effect. Move it frommx23_olinuxino.ctospl_boot.c.This change was verified by reading back the register values.
Signed-off-by Jan Luebbe <[email protected]>Cc Marek Vasut <[email protected]>Cc Stefano Babic <[email protected]>
You're obviously right, thank you for spotting this!
Best regards,
Marek Vasut
PATCH 1/1 arm: mxs: olinuxino: move DRAM config tuning to SPL
In reply to Jan LuebbeQuoted 10 lines · Jan Luebbe
The weak
mxs_adjust_memory_paramsfunction is called fromspl_mem_init.c, so it must be linked into the SPL to have an effect. Move it frommx23_olinuxino.ctospl_boot.c.This change was verified by reading back the register values.
Signed-off-by Jan Luebbe <[email protected]>Cc Marek Vasut <[email protected]>Cc Stefano Babic <[email protected]>---
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
Signature · 5 lines
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