arm: omap: reset sata on OS boot

index c9a3beb..12ed5e3 100644
@@ -137,6 +137,33 @@ static void sunxi_dma_init(volatile u8 *port_mmio)
 }
 #endif
 
+int ahci_reset(u32 base)
+{
+	int i = 1000;
+	u32 host_ctl_reg = base + HOST_CTL;
+	u32 tmp = readl(host_ctl_reg); /* global controller reset */
+
+	if ((tmp & HOST_RESET) == 0)
+		writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
+
+	/*
+	 * reset must complete within 1 second, or
+	 * the hardware should be considered fried.
+	 */
+	do {
+		udelay(1000);
+		tmp = readl(host_ctl_reg);
+		i--;
+	} while ((i > 0) && (tmp & HOST_RESET));
+
+	if (i == 0) {
+		printf("controller reset failed (0x%x)\n", tmp);
+		return -1;
+	}
+
+	return 0;
+}
+
 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
 {
 #ifndef CONFIG_SCSI_AHCI_PLAT

@@ -156,23 +183,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
 	cap_save &= ((1 << 28) | (1 << 17));
 	cap_save |= (1 << 27);  /* Staggered Spin-up. Not needed. */
 
-	/* global controller reset */
-	tmp = readl(mmio + HOST_CTL);
-	if ((tmp & HOST_RESET) == 0)
-		writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
-
-	/* reset must complete within 1 second, or
-	 * the hardware should be considered fried.
-	 */
-	i = 1000;
-	do {
-		udelay(1000);
-		tmp = readl(mmio + HOST_CTL);
-		if (!i--) {
-			debug("controller reset failed (0x%x)\n", tmp);
-			return -1;
-		}
-	} while (tmp & HOST_RESET);
+	ret = ahci_reset(probe_ent->mmio_base);
+	if (ret)
+		return ret;
 
 	writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
 	writel(cap_save, mmio + HOST_CAP);

index 35b8a8c..e8dee53 100644
@@ -161,5 +161,6 @@ struct ahci_probe_ent {
 };
 
 int ahci_init(u32 base);
+int ahci_reset(u32 base);
 
 #endif

index 12ed5e3..37d2d2a 100644
@@ -1010,12 +1010,11 @@ static int ata_io_flush(u8 port)
 }
 
 
-void scsi_bus_reset(void)
+__weak void scsi_bus_reset(void)
 {
 	/*Not implement*/
 }
 
-
 void scsi_print_error(ccb * pccb)
 {
 	/*The ahci error info can be read in the ahci driver*/

index a24baa1..d18bc50 100644
@@ -85,3 +85,9 @@ void scsi_init(void)
 	init_sata(0);
 	scsi_scan(1);
 }
+
+void scsi_bus_reset(void)
+{
+	ahci_reset(DWC_AHSATA_BASE);
+	ahci_init(DWC_AHSATA_BASE);
+}

index cb18908..00a1082 100644
@@ -9,12 +9,14 @@
  */
 
 #include <common.h>
+#include <ahci.h>
 #include <spl.h>
 #include <asm/omap_common.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <watchdog.h>
+#include <scsi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -143,3 +145,10 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	image_entry((u32 *)&gd->arch.omap_boot_params);
 }
 #endif
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void arch_preboot_os(void)
+{
+	ahci_reset(DWC_AHSATA_BASE);
+}
+#endif

index 92ce1e1..0cd4aec 100644
@@ -63,6 +63,19 @@
 #define CONFIG_HSMMC2_8BIT
 #define CONFIG_SUPPORT_EMMC_BOOT
 
+/* SATA Boot related defines */
+#define CONFIG_SPL_SATA_SUPPORT
+#define CONFIG_SPL_SATA_BOOT_DEVICE		0
+#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
+
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
 /* USB UHH support options */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_HOST