x86: Add a README.x86 for U-Boot on x86 support
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
--- doc/README.x86 | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 doc/README.x86
doc/README.x86 new file +123 -0
@@ -0,0 +1,123 @@ +# +# Copyright (C) 2014, Simon Glass <[email protected]> +# Copyright (C) 2014, Bin Meng <[email protected]> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +============= + +This document describes the information about U-Boot running on x86 targets, +including supported boards, build instructions, todo list, etc. + +Status +------ +U-Boot supports running as a coreboot [1] payload on x86. So far only link +(Chromebook pixel) has been tested, but it should work with minimal adjustments +on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Google Chromebook link and Intel +Crown Bay board support running U-Boot 'bare metal'. + +As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux +kernel as part of a FIT image. It also supports a compressed zImage. + +Build Instructions +------------------ +Building U-Boot as a coreboot payload is just like building U-Boot for targets +on other architectures, like below: + +$ make coreboot-x86_defconfig +$ make all + +Building rom version U-Boot (hereafter referred to as u-boot.rom) is a little +bit tricky, as generally it requires several binary blobs which are not shipped +in the U-Boot source tree. Due to this reason, the u-boot.rom build is not +turned on by default in the U-Boot source tree. Firstly, you need turn it on +by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Google Chromebook link specific instructions: + +Firstly, you need the following binary blobs: + +* descriptor.bin - Intel flash descriptor +* me.bin - Intel Management Engine +* mrc.bin - Memory Reference Code, which sets up SDRAM +* video ROM - sets up the display + +You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin. +As for the video ROM, you can get it here [2]. + +Now you can build U-Boot and obtain u-boot.rom: + +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: + +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide including initialization of the CPU, +memory controller, chipset and certain bus interfaces. + +Downalod the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd +* ./Microcode/C0_22211.BIN + +Now you can build U-Boot and obtaim u-boot.rom + +$ make crownbay_defconfig +$ make menuconfig # points FSP and CMC binary path to the correct one +$ make all + +CPU Microcode +------------- +Modern CPU usually requires a special bit stream called microcode [5] to be +loaded on the processor after power up in order to function properly. U-Boot +has already integrated these as hex dumps in the source tree. + +Driver Model +------------ +x86 has been converted to use driver model for serial and GPIO. + +Device Tree +----------- +x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to +be turned on. Not every device on the board is configured via devie tree, but +more and more devices will be added as time goes by. Check out the directory +arch/x86/dts/ for these device tree source files. + +TODO List +--------- +- MTRR support (for performance) +- Audio +- Chrome OS verified boot +- SMI and ACPI support, to provide platform info and facilities to Linux + +References +---------- +[1] http://www.coreboot.org +[2] http://www.coreboot.org/~stepan/pci8086,0166.rom +[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +[4] http://www.intel.com/fsp +[5] http://en.wikipedia.org/wiki/Microcode
Signature · 1 line
1.8.2.1
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
Hi Bin,
Quoted 12 lines · Bin Meng
Signed-off-by Bin Meng <[email protected]>--- doc/README.x86 | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 doc/README.x86doc/README.x86 new file +0
-0
doc/README.x86 line 9
Quoted 9 lines
doc/README.x86 new file +9
-0@@ -0,0 +1,123 @@ +# +# Copyright (C) 2014, Simon Glass <[email protected]> +# Copyright (C) 2014, Bin Meng <[email protected]> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +=============
Very nice!
Quoted 63 lines
doc/README.x86 new file +63
-0+ +This document describes the information about U-Boot running on x86 targets, +including supported boards, build instructions, todo list, etc. + +Status +------ +U-Boot supports running as a coreboot [1] payload on x86. So far only link +(Chromebook pixel) has been tested, but it should work with minimal adjustments +on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Google Chromebook link and Intel +Crown Bay board support running U-Boot 'bare metal'. + +As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux +kernel as part of a FIT image. It also supports a compressed zImage. + +Build Instructions +------------------ +Building U-Boot as a coreboot payload is just like building U-Boot for targets +on other architectures, like below: + +$ make coreboot-x86_defconfig +$ make all + +Building rom version U-Boot (hereafter referred to as u-boot.rom) is a little +bit tricky, as generally it requires several binary blobs which are not shipped +in the U-Boot source tree. Due to this reason, the u-boot.rom build is not +turned on by default in the U-Boot source tree. Firstly, you need turn it on +by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Google Chromebook link specific instructions: + +Firstly, you need the following binary blobs: + +* descriptor.bin - Intel flash descriptor +* me.bin - Intel Management Engine +* mrc.bin - Memory Reference Code, which sets up SDRAM +* video ROM - sets up the display + +You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin. +As for the video ROM, you can get it here [2]. + +Now you can build U-Boot and obtain u-boot.rom: + +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: +
doc/README.x86 line 82
Quoted 10 lines
doc/README.x86 new file +10
-0+U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide including initialization of the CPU, +memory controller, chipset and certain bus interfaces. + +Downalod the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too.
Can we just put them in the board directory with standard names?
doc/README.x86 line 90
Quoted 8 lines
doc/README.x86 new file +8
-0+ +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd +* ./Microcode/C0_22211.BIN + +Now you can build U-Boot and obtaim u-boot.rom + +$ make crownbay_defconfig +$ make menuconfig # points FSP and CMC binary path to the correct one
Best if we can avoid that step.
Quoted 12 lines
doc/README.x86 new file +12
-0+$ make all + +CPU Microcode +------------- +Modern CPU usually requires a special bit stream called microcode [5] to be +loaded on the processor after power up in order to function properly. U-Boot +has already integrated these as hex dumps in the source tree. + +Driver Model +------------ +x86 has been converted to use driver model for serial and GPIO. +
doc/README.x86 line 112
Quoted 10 lines
doc/README.x86 new file +10
-0+Device Tree +----------- +x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to +be turned on. Not every device on the board is configured via devie tree, but +more and more devices will be added as time goes by. Check out the directory +arch/x86/dts/ for these device tree source files. + +TODO List +--------- +- MTRR support (for performance)
I'm interested - does the lack of this make your board slow?
Quoted 12 lines
doc/README.x86 new file +11
-1+- Audio +- Chrome OS verified boot +- SMI and ACPI support, to provide platform info and facilities to Linux + +References +---------- +[1] http://www.coreboot.org +[2] http://www.coreboot.org/~stepan/pci8086,0166.rom +[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +[4] http://www.intel.com/fsp +[5] http://en.wikipedia.org/wiki/Microcode --
Quoted 2 lines
1.8.2.1
Regards,
Simon
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
Hi Simon,
Quoted 94 lines · Simon Glass
Hi Bin,
Quoted 12 lines · Bin Meng
Signed-off-by Bin Meng <[email protected]>--- doc/README.x86 | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 doc/README.x86doc/README.x86 new file +0
-0doc/README.x86 line 9
Quoted 9 lines
doc/README.x86 new file +9
-0@@ -0,0 +1,123 @@ +# +# Copyright (C) 2014, Simon Glass <[email protected]> +# Copyright (C) 2014, Bin Meng <[email protected]> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +=============Very nice!
Quoted 67 lines
doc/README.x86 new file +67
-0+ +This document describes the information about U-Boot running on x86 targets, +including supported boards, build instructions, todo list, etc. + +Status +------ +U-Boot supports running as a coreboot [1] payload on x86. So far only link +(Chromebook pixel) has been tested, but it should work with minimal adjustments +on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Google Chromebook link and Intel +Crown Bay board support running U-Boot 'bare metal'. + +As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux +kernel as part of a FIT image. It also supports a compressed zImage. + +Build Instructions +------------------ +Building U-Boot as a coreboot payload is just like building U-Boot for targets +on other architectures, like below: + +$ make coreboot-x86_defconfig +$ make all + +Building rom version U-Boot (hereafter referred to as u-boot.rom) is a little +bit tricky, as generally it requires several binary blobs which are not shipped +in the U-Boot source tree. Due to this reason, the u-boot.rom build is not +turned on by default in the U-Boot source tree. Firstly, you need turn it on +by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Google Chromebook link specific instructions: + +Firstly, you need the following binary blobs: + +* descriptor.bin - Intel flash descriptor +* me.bin - Intel Management Engine +* mrc.bin - Memory Reference Code, which sets up SDRAM +* video ROM - sets up the display + +You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin. +As for the video ROM, you can get it here [2]. + +Now you can build U-Boot and obtain u-boot.rom: + +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: + +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide including initialization of the CPU, +memory controller, chipset and certain bus interfaces.
Quoted 8 lines
doc/README.x86 line 82
Quoted 6 lines
doc/README.x86 new file +6
-0+ +Downalod the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too.Can we just put them in the board directory with standard names?
Yes, will do it in v2.
Quoted 10 lines
doc/README.x86 line 90
Quoted 8 lines
doc/README.x86 new file +8
-0+ +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd +* ./Microcode/C0_22211.BIN + +Now you can build U-Boot and obtaim u-boot.rom + +$ make crownbay_defconfig +$ make menuconfig # points FSP and CMC binary path to the correct oneBest if we can avoid that step.
I will update the instructions to use the standard binary blob names, so that this step can be omitted.
Quoted 16 lines
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doc/README.x86 new file +16
-0+$ make all + +CPU Microcode +------------- +Modern CPU usually requires a special bit stream called microcode [5] to be +loaded on the processor after power up in order to function properly. U-Boot +has already integrated these as hex dumps in the source tree. + +Driver Model +------------ +x86 has been converted to use driver model for serial and GPIO. + +Device Tree +----------- +x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to +be turned on. Not every device on the board is configured via devie tree, but
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doc/README.x86 line 112
Quoted 6 lines
doc/README.x86 new file +6
-0+more and more devices will be added as time goes by. Check out the directory +arch/x86/dts/ for these device tree source files. + +TODO List +--------- +- MTRR support (for performance)I'm interested - does the lack of this make your board slow?
I believe the FSP binary blob already has the MTRR support, and U-Boot running on my board is pretty fast.
[snip]
Regards,
Bin
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
In reply to Simon GlassHi Simon, Bin,
u-boot-bounces at lists.denx.de wrote on 12/04/2014 04:03:54 PM:
Quoted 27 lines
From: Simon Glass <[email protected]>
To: Bin Meng <[email protected]>
Cc: U-Boot Mailing List <[email protected]>
Date: 12/04/2014 04:04 PM
Subject: Re: [U-Boot] [PATCH 25/25] x86: Add a README.x86 for U-Boot on x86 support
Sent by: u-boot-bounces at lists.denx.deHi Bin,
Quoted 3 lines · Bin Meng
Signed-off-by Bin Meng <[email protected]>--- doc/README.x86 | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Quoted 12 lines
1 file changed, 123 insertions(+) create mode 100644 doc/README.x86doc/README.x86 new file +3
-0@@ -0,0 +1,123 @@ +# +# Copyright (C) 2014, Simon Glass <[email protected]> +# Copyright (C) 2014, Bin Meng <[email protected]>
Quoted 9 lines
doc/README.x86 line 9
Quoted 6 lines
doc/README.x86 new file +6
-0+# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +=============Very nice!
This is all really great work.
I do have a question though, and if it's already been asked/answered and I missed the thread I apologize for the noise. Part of the reason we've held off on doing this project (other than resources of course :) ) was a concern about licensing. U-boot is released under the GPL and we're worried that by linking in Intel's FSP we're creating a "derived work" that would then require Intel to release the source for the FSP, which they aren't going to do and would leave us open to law suits. Doing it by calls into an opaque blob can loosely be defined as a dynamically linked library and therefore fall under the GPL exception clause, but our legal department considers that a dangerous assumption on our part.
Has anyone considered this issue? I'm not a lawyer so I get lost in the legalize of licences pretty fast.
Thanks again for all the work.
V/r
Bruce
[snip]
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
Hi Bruce,
Quoted 54 lines · On 5 December 2014 at 11:34, <[email protected]> wrote:
Hi Simon, Bin,
u-boot-bounces at lists.denx.de wrote on 12/04/2014 04:03:54 PM:
Quoted 27 lines
From: Simon Glass <[email protected]>
To: Bin Meng <[email protected]>
Cc: U-Boot Mailing List <[email protected]>
Date: 12/04/2014 04:04 PM
Subject: Re: [U-Boot] [PATCH 25/25] x86: Add a README.x86 for U-Boot on x86 support
Sent by: u-boot-bounces at lists.denx.deHi Bin,
Quoted 3 lines · Bin Meng
Signed-off-by Bin Meng <[email protected]>--- doc/README.x86 | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Quoted 12 lines
1 file changed, 123 insertions(+) create mode 100644 doc/README.x86doc/README.x86 new file +3
-0@@ -0,0 +1,123 @@ +# +# Copyright (C) 2014, Simon Glass <[email protected]> +# Copyright (C) 2014, Bin Meng <[email protected]>Quoted 9 lines
doc/README.x86 line 9
Quoted 6 lines
doc/README.x86 new file +6
-0+# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +=============Very nice!
This is all really great work.
I do have a question though, and if it's already been asked/answered and I missed the thread I apologize for the noise. Part of the reason we've held off on doing this project (other than resources of course :) ) was a concern about licensing. U-boot is released under the GPL and we're worried that by linking in Intel's FSP we're creating a "derived work" that would then require Intel to release the source for the FSP, which they aren't going to do and would leave us open to law suits. Doing it by calls into an opaque blob can loosely be defined as a dynamically linked library and therefore fall under the GPL exception clause, but our legal department considers that a dangerous assumption on our part.
Quoted 4 lines
Has anyone considered this issue? I'm not a lawyer so I get lost in the legalize of licences pretty fast.
Thanks again for all the work.
Well if you a legal department, that's what you pay them for and they should be able to figure this out. Clearly if it were not permitted to use the binary blobs in open source software then the blobs wouldn't be very useful. But I'm not a lawyer either and am not qualified to provide legal advice! It would be useful if you could post what you find either way. And if for some reason there is a problem, we could take it up with Intel.
You can get to the license here:
This is what it says today:
The terms of the software license agreement included with any software you download will control your use of the software.
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Regards,
Simon
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
Hi Simon,
sjg at google.com wrote on 12/05/2014 11:05:30 AM:
Quoted 9 lines
From: Simon Glass <[email protected]>
To:Bruce_Leonardat selinc.com
Cc: Bin Meng <[email protected]>, U-Boot Mailing List <u- boot at lists.denx.de>, u-boot-bounces at lists.denx.de
Date: 12/05/2014 11:05 AM
Subject: Re: [U-Boot] [PATCH 25/25] x86: Add a README.x86 for U-Boot on x86 support
Sent by: sjg at google.com
Quoted 47 lines
Hi Bruce,
Quoted 44 lines · On 5 December 2014 at 11:34, <[email protected]> wrote:
Hi Simon, Bin,
u-boot-bounces at lists.denx.de wrote on 12/04/2014 04:03:54 PM:
Quoted 27 lines
From: Simon Glass <[email protected]>
To: Bin Meng <[email protected]>
Cc: U-Boot Mailing List <[email protected]>
Date: 12/04/2014 04:04 PM
Subject: Re: [U-Boot] [PATCH 25/25] x86: Add a README.x86 for U-Boot on x86 support
Sent by: u-boot-bounces at lists.denx.deHi Bin,
Quoted 3 lines · Bin Meng
Signed-off-by Bin Meng <[email protected]>--- doc/README.x86 | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Quoted 12 lines
1 file changed, 123 insertions(+) create mode 100644 doc/README.x86doc/README.x86 new file +3
-0@@ -0,0 +1,123 @@ +# +# Copyright (C) 2014, Simon Glass <[email protected]> +# Copyright (C) 2014, Bin Meng <[email protected]>Quoted 9 lines
doc/README.x86 line 9
Quoted 6 lines
doc/README.x86 new file +6
-0+# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +=============Very nice!
This is all really great work.
I do have a question though, and if it's already been asked/answered
and I
Quoted 1 line
Quoted 1 line
missed the thread I apologize for the noise. Part of the reason we've
held
Quoted 1 line
Quoted 1 line
off on doing this project (other than resources of course :) ) wasa
concern
Quoted 1 line
Quoted 1 line
about licensing. U-boot is released under the GPL and we're worried
that by
Quoted 2 lines
Quoted 2 lines
linking in Intel's FSP we're creating a "derived work" that would then require Intel to release the source for the FSP, which they aren't
going to
Quoted 1 line
Quoted 1 line
do and would leave us open to law suits. Doing it by calls into an
opaque
Quoted 1 line
Quoted 1 line
blob can loosely be defined as a dynamically linked library and
therefore
Quoted 1 line
Quoted 1 line
fall under the GPL exception clause, but our legal department
considers that
Quoted 3 lines
Quoted 3 lines
a dangerous assumption on our part.
Has anyone considered this issue? I'm not a lawyer so I get lost in
the
Quoted 4 lines
Quoted 3 lines
legalize of licences pretty fast.
Thanks again for all the work.
Quoted 9 lines
Well if you a legal department, that's what you pay them for and they should be able to figure this out. Clearly if it were not permitted to use the binary blobs in open source software then the blobs wouldn't be very useful. But I'm not a lawyer either and am not qualified to provide legal advice! It would be useful if you could post what you find either way. And if for some reason there is a problem, we could take it up with Intel.
Thanks for the info. We were sort of hoping that either the u-boot community or Denx SE may have already addressed this. Probably what we'll have to do is get an Intel lawyer on the phone with a copy of both the GPL and the FSP licences and just go through them item by item. We'll feedback to the list what we find out.
Have a good weekend!
V/r
Bruce
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
Hi Bruce,
Quoted 99 lines · On Sat, Dec 6, 2014 at 4:02 AM, <[email protected]> wrote:
Hi Simon,
sjg at google.com wrote on 12/05/2014 11:05:30 AM:
Quoted 79 lines
From: Simon Glass <[email protected]>
To:Bruce_Leonardat selinc.com
Cc: Bin Meng <[email protected]>, U-Boot Mailing List <u- boot at lists.denx.de>, u-boot-bounces at lists.denx.de
Date: 12/05/2014 11:05 AM
Subject: Re: [U-Boot] [PATCH 25/25] x86: Add a README.x86 for U-Boot on x86 support
Sent by: sjg at google.comHi Bruce,
Quoted 62 lines · On 5 December 2014 at 11:34, <[email protected]> wrote:
Hi Simon, Bin,
u-boot-bounces at lists.denx.de wrote on 12/04/2014 04:03:54 PM:
Quoted 27 lines
From: Simon Glass <[email protected]>
To: Bin Meng <[email protected]>
Cc: U-Boot Mailing List <[email protected]>
Date: 12/04/2014 04:04 PM
Subject: Re: [U-Boot] [PATCH 25/25] x86: Add a README.x86 for U-Boot on x86 support
Sent by: u-boot-bounces at lists.denx.deHi Bin,
Quoted 3 lines · Bin Meng
Signed-off-by Bin Meng <[email protected]>--- doc/README.x86 | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Quoted 12 lines
1 file changed, 123 insertions(+) create mode 100644 doc/README.x86doc/README.x86 new file +3
-0@@ -0,0 +1,123 @@ +# +# Copyright (C) 2014, Simon Glass <[email protected]> +# Copyright (C) 2014, Bin Meng <[email protected]>Quoted 9 lines
doc/README.x86 line 9
Quoted 6 lines
doc/README.x86 new file +6
-0+# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 +=============Very nice!
This is all really great work.
I do have a question though, and if it's already been asked/answered and I
missed the thread I apologize for the noise. Part of the reason we've held
off on doing this project (other than resources of course :) ) wasa concern
about licensing. U-boot is released under the GPL and we're worried that by
linking in Intel's FSP we're creating a "derived work" that would then require Intel to release the source for the FSP, which they aren't going to
do and would leave us open to law suits. Doing it by calls into an opaque
blob can loosely be defined as a dynamically linked library and therefore
fall under the GPL exception clause, but our legal department considers that
a dangerous assumption on our part.Quoted 4 lines
Has anyone considered this issue? I'm not a lawyer so I get lost in the legalize of licences pretty fast.
Thanks again for all the work.
Quoted 9 lines
Well if you a legal department, that's what you pay them for and they should be able to figure this out. Clearly if it were not permitted to use the binary blobs in open source software then the blobs wouldn't be very useful. But I'm not a lawyer either and am not qualified to provide legal advice! It would be useful if you could post what you find either way. And if for some reason there is a problem, we could take it up with Intel.
Thanks for the info. We were sort of hoping that either the u-boot community or Denx SE may have already addressed this. Probably what we'll have to do is get an Intel lawyer on the phone with a copy of both the GPL and the FSP licences and just go through them item by item. We'll feedback to the list what we find out.
Quoted 4 lines
Have a good weekend!
V/r
Bruce
Actually coreboot supports Intel FSP as well on several other platforms already. There was once a thread talking about integrating FSP which might be helpful on your questions. Check it out @
http://www.coreboot.org/pipermail/coreboot/2013-December/076801.html.
Looks Intel is OK to have coreboot to integrate the FSP binary blobs in the coreboot source tree, but coreboot maintainers don't do that.
Regards,
Bin
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
In reply to Bin MengHi!
Quoted 5 lines
doc/README.x86 new file +4
-0+Status +------ +U-Boot supports running as a coreboot [1] payload on x86. So far only link +(Chromebook pixel) has been tested, but it should work with minimaladjustments
Link is codeword for Chromebook Pixel? I'd write "Chromebook Pixel (Link)" if so.
doc/README.x86 line 21
Quoted 4 lines
doc/README.x86 new file +4
-0+on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Google Chromebook link and Intel
Should this me "Chromebook Pixel"?
Quoted 1 line
+Building rom version U-Boot (hereafter referred to as u-boot.rom) is a little
"ROM version of" ?
doc/README.x86 line 43
Quoted 8 lines
doc/README.x86 new file +8
-0+bit tricky, as generally it requires several binary blobs which are not shipped +in the U-Boot source tree. Due to this reason, the u-boot.rom build is not +turned on by default in the U-Boot source tree. Firstly, you need turn it on +by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Google Chromebook link specific instructions:
"link -> Pixel"?
Quoted 1 line
+Firstly, you need the following binary blobs:
Firstly->First
doc/README.x86 line 63
Quoted 12 lines
doc/README.x86 new file +12
-0+You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin.
Should there be instruction where to put those files? Perhaps a script doing this and getting ROM would be nice?
Quoted 12 lines
doc/README.x86 new file +11
-0+As for the video ROM, you can get it here [2]. + +Now you can build U-Boot and obtain u-boot.rom: +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: + +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide including initialization of
Quoted 1 line
the CPU,
"Guide, "
Quoted 1 line
+Downalod the Intel FSP for Atom E6xx series and Platform Controller
-> Download.
Thanks,
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
Hi Pavel,
Quoted 71 lines · Pavel Machek
Hi!
Quoted 5 lines
doc/README.x86 new file +4
-0+Status +------ +U-Boot supports running as a coreboot [1] payload on x86. So far only link +(Chromebook pixel) has been tested, but it should work with minimaladjustments
Link is codeword for Chromebook Pixel? I'd write "Chromebook Pixel (Link)" if so.
doc/README.x86 line 21
Quoted 4 lines
doc/README.x86 new file +4
-0+on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Google Chromebook link and IntelShould this me "Chromebook Pixel"?
Quoted 1 line
+Building rom version U-Boot (hereafter referred to as u-boot.rom) is a little
"ROM version of" ?
doc/README.x86 line 43
Quoted 8 lines
doc/README.x86 new file +8
-0+bit tricky, as generally it requires several binary blobs which are not shipped +in the U-Boot source tree. Due to this reason, the u-boot.rom build is not +turned on by default in the U-Boot source tree. Firstly, you need turn it on +by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Google Chromebook link specific instructions:"link -> Pixel"?
Quoted 1 line
+Firstly, you need the following binary blobs:
Firstly->Firstdoc/README.x86 line 63
Quoted 12 lines
doc/README.x86 new file +12
-0+You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin.Should there be instruction where to put those files? Perhaps a script doing this and getting ROM would be nice?
Quoted 12 lines
doc/README.x86 new file +11
-0+As for the video ROM, you can get it here [2]. + +Now you can build U-Boot and obtain u-boot.rom: +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: + +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide including initialization ofQuoted 1 line
the CPU,
"Guide, "
Quoted 4 lines
Quoted 1 line
+Downalod the Intel FSP for Atom E6xx series and Platform Controller
-> Download.
Most issues fixed in the v4 patch @
http://patchwork.ozlabs.org/patch/422203/, except the Chromebook Pixel (link) issue which will need Simon to comment.
Regards,
Bin
PATCH 25/25 x86: Add a README.x86 for U-Boot on x86 support
In reply to Pavel MachekHi Pavel,
Quoted 12 lines · Pavel Machek
Hi!
Quoted 5 lines
doc/README.x86 new file +4
-0+Status +------ +U-Boot supports running as a coreboot [1] payload on x86. So far only link +(Chromebook pixel) has been tested, but it should work with minimaladjustments
Link is codeword for Chromebook Pixel? I'd write "Chromebook Pixel (Link)" if so.
Quoted 6 lines
doc/README.x86 line 21
Quoted 4 lines
doc/README.x86 new file +4
-0+on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Google Chromebook link and IntelShould this me "Chromebook Pixel"?
Yes we should either say 'Chromebook Pixel' or link. I will tidy this up when applying.
Quoted 54 lines
Quoted 3 lines
+Building rom version U-Boot (hereafter referred to as u-boot.rom) is a little
"ROM version of" ?
doc/README.x86 line 43
Quoted 8 lines
doc/README.x86 new file +8
-0+bit tricky, as generally it requires several binary blobs which are not shipped +in the U-Boot source tree. Due to this reason, the u-boot.rom build is not +turned on by default in the U-Boot source tree. Firstly, you need turn it on +by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Google Chromebook link specific instructions:"link -> Pixel"?
Quoted 1 line
+Firstly, you need the following binary blobs:
Firstly->Firstdoc/README.x86 line 63
Quoted 12 lines
doc/README.x86 new file +12
-0+You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin.Should there be instruction where to put those files? Perhaps a script doing this and getting ROM would be nice?
Quoted 12 lines
doc/README.x86 new file +11
-0+As for the video ROM, you can get it here [2]. + +Now you can build U-Boot and obtain u-boot.rom: +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: + +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide including initialization ofQuoted 1 line
the CPU,
"Guide, "
Quoted 3 lines
Quoted 1 line
+Downalod the Intel FSP for Atom E6xx series and Platform Controller
-> Download.
Regards,
Simon