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clk: tegra: add support for the Tegra132 CAR IP block

PATCH In review Paul Walmsley 4 participants 11 messages Dec 16, 2014 – Jan 14, 2015

Subsystems (6)
Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +2 more subsystems
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Paul Walmsley

author
#0 lore raw

cover clk: tegra: add support for the Tegra132 CAR IP block

This series follows up on Peter De Schrijver's posting of a Tegra132 CAR series in July of this year. It adds common clock framework support for the Tegra132 CAR IP block.

The patches are based on next-20141209 and have been compiled and boot-tested on a Tegra30 Beaver board, a Tegra114 Dalmore board, and a Tegra124 Jetson TK1. They've also been tested on a Tegra132 Norrin FFD board, with some other patches applied since support for that board isn't completely upstream (but is coming shortly).

Intended for v3.20.

- Paul

---

Paul Walmsley (2):
clk: tegra: split Tegra124 clock header file
clk: tegra: Add support for the Tegra132 CAR IP block

Peter De Schrijver (2):
clk: tegra: make tegra_clocks_apply_init_table() arch_initcall
clk: tegra: Update binding doc for Tegra132

 .../bindings/clock/nvidia,tegra124-car.txt         |   10 -
 arch/arm/mach-tegra/tegra.c                        |    2 
 drivers/clk/tegra/Makefile                         |    1 
 drivers/clk/tegra/clk-pll.c                        |   10 -
 drivers/clk/tegra/clk-tegra124.c                   |  130 +++++++-
 drivers/clk/tegra/clk.c                            |    7 
 include/dt-bindings/clock/tegra124-car-common.h    |  345 ++++++++++++++++++++
 include/dt-bindings/clock/tegra124-car.h           |  345 +-------------------
 include/linux/clk/tegra.h                          |    2 
 9 files changed, 494 insertions(+), 358 deletions(-)
 create mode 100644 include/dt-bindings/clock/tegra124-car-common.h
author
#1 lore raw

PATCH 1/4 clk: tegra: make tegra_clocks_apply_init_table() arch_initcall

From: Peter De Schrijver <[email protected]>

tegra_clocks_apply_init_table() needs to be called after the udelay loop has been calibrated (see commit 441f199a37cfd66c5dd8dd45490bd3ea6971117d ("clk: tegra: defer application of init table") for why that is). On existing Tegra SoCs this was done by calling tegra_clocks_apply_init_table() from tegra_dt_init(). To make this also work on ARM64, we need to change this into an initcall. tegra_dt_init() is called from customize_machine which is an arch_initcall. Therefore this should also work on existing 32bit Tegra SoCs.

Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and Tegra132.

Signed-off-by Peter De Schrijver <[email protected]>
[paul at pwsan.com: tweaked the commit message]
Signed-off-by Paul Walmsley <[email protected]>
Signed-off-by Paul Walmsley <[email protected]>
Cc Thierry Reding <[email protected]>
Cc Prashant Gaikwad <[email protected]>
Cc Mike Turquette <[email protected]>
Cc Stephen Boyd <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Thierry Reding <[email protected]>
Cc Alexandre Courbot <[email protected]>
---
 arch/arm/mach-tegra/tegra.c |    2 --
 drivers/clk/tegra/clk.c     |    7 +++++--
 include/linux/clk/tegra.h   |    2 --
 3 files changed, 5 insertions(+), 6 deletions(-)
arch/arm/mach-tegra/tegra.c +0 -2
index ef016af..914341b 100644
@@ -91,8 +91,6 @@ static void __init tegra_dt_init(void)
 	struct soc_device *soc_dev;
 	struct device *parent = NULL;
 
-	tegra_clocks_apply_init_table();
-
 	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 	if (!soc_dev_attr)
 		goto out;
drivers/clk/tegra/clk.c +5 -2
index 97dc859..9ddb754 100644
@@ -302,10 +302,13 @@ struct clk ** __init tegra_lookup_dt_id(int clk_id,
 
 tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 
-void __init tegra_clocks_apply_init_table(void)
+static int __init tegra_clocks_apply_init_table(void)
 {
 	if (!tegra_clk_apply_init_table)
-		return;
+		return 0;
 
 	tegra_clk_apply_init_table();
+
+	return 0;
 }
+arch_initcall(tegra_clocks_apply_init_table);
include/linux/clk/tegra.h +0 -2
index 3ca9fca..19c4208 100644
@@ -120,6 +120,4 @@ static inline void tegra_cpu_clock_resume(void)
 }
 #endif
 
-void tegra_clocks_apply_init_table(void);
-
 #endif /* __LINUX_CLK_TEGRA_H_ */
#2 lore raw

Re: [PATCH 1/4] clk: tegra: make tegra_clocks_apply_init_table() arch_initcall

Quoted 12 lines · Paul Walmsley

From: Peter De Schrijver <[email protected]>

tegra_clocks_apply_init_table() needs to be called after the udelay loop has been calibrated (see commit 441f199a37cfd66c5dd8dd45490bd3ea6971117d ("clk: tegra: defer application of init table") for why that is). On existing Tegra SoCs this was done by calling tegra_clocks_apply_init_table() from tegra_dt_init(). To make this also work on ARM64, we need to change this into an initcall. tegra_dt_init() is called from customize_machine which is an arch_initcall. Therefore this should also work on existing 32bit Tegra SoCs.

Quoted 2 lines

Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and Tegra132.

Thierry, I don't think this series has ever been reviewed by us? The patches apply nicely on my tree and look harmless but I would rather leave that part to you if you don't mind.

author
#3 lore raw

PATCH 2/4 clk: tegra: split Tegra124 clock header file

In reply to Paul Walmsley

From: Paul Walmsley <[email protected]>

Split the Tegra124 clock macros into two files:

1. Clock macros common to both Tegra124 and Tegra132
2. Clock macros specific to Tegra124

This was requested by Thierry in Message-ID
<20140716072539.GD7978@ulmo>.

Signed-off-by Paul Walmsley <[email protected]>
Signed-off-by Paul Walmsley <[email protected]>
Cc Peter De Schrijver <[email protected]>
Cc Rob Herring <[email protected]>
Cc Pawel Moll <[email protected]>
Cc Mark Rutland <[email protected]>
Cc Ian Campbell <[email protected]>
Cc Kumar Gala <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Thierry Reding <[email protected]>
Cc Alexandre Courbot <[email protected]>
---
 include/dt-bindings/clock/tegra124-car-common.h |  345 +++++++++++++++++++++++
 include/dt-bindings/clock/tegra124-car.h        |  345 +----------------------
 2 files changed, 354 insertions(+), 336 deletions(-)
 create mode 100644 include/dt-bindings/clock/tegra124-car-common.h
include/dt-bindings/clock/tegra124-car-common.h new file +345 -0
new file mode 100644
index 0000000..aeb52df
@@ -0,0 +1,345 @@
+/*
+ * This header provides constants for binding nvidia,tegra124-car or
+ * nvidia,tegra132-car.
+ *
+ * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 185 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+#define TEGRA124_CLK_ISPB 3
+#define TEGRA124_CLK_RTC 4
+#define TEGRA124_CLK_TIMER 5
+#define TEGRA124_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA124_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA124_CLK_I2S1 11
+#define TEGRA124_CLK_I2C1 12
+/* 13 */
+#define TEGRA124_CLK_SDMMC1 14
+#define TEGRA124_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA124_CLK_PWM 17
+#define TEGRA124_CLK_I2S2 18
+/* 20 (register bit affects vi and vi_sensor) */
+/* 21 */
+#define TEGRA124_CLK_USBD 22
+#define TEGRA124_CLK_ISP 23
+/* 26 */
+/* 25 */
+#define TEGRA124_CLK_DISP2 26
+#define TEGRA124_CLK_DISP1 27
+#define TEGRA124_CLK_HOST1X 28
+#define TEGRA124_CLK_VCP 29
+#define TEGRA124_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA124_CLK_MC 32
+/* 33 */
+#define TEGRA124_CLK_APBDMA 34
+/* 35 */
+#define TEGRA124_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA124_CLK_KFUSE 40
+#define TEGRA124_CLK_SBC1 41
+#define TEGRA124_CLK_NOR 42
+/* 43 */
+#define TEGRA124_CLK_SBC2 44
+/* 45 */
+#define TEGRA124_CLK_SBC3 46
+#define TEGRA124_CLK_I2C5 47
+#define TEGRA124_CLK_DSIA 48
+/* 49 */
+#define TEGRA124_CLK_MIPI 50
+#define TEGRA124_CLK_HDMI 51
+#define TEGRA124_CLK_CSI 52
+/* 53 */
+#define TEGRA124_CLK_I2C2 54
+#define TEGRA124_CLK_UARTC 55
+#define TEGRA124_CLK_MIPI_CAL 56
+#define TEGRA124_CLK_EMC 57
+#define TEGRA124_CLK_USB2 58
+#define TEGRA124_CLK_USB3 59
+/* 60 */
+#define TEGRA124_CLK_VDE 61
+#define TEGRA124_CLK_BSEA 62
+#define TEGRA124_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA124_CLK_UARTD 65
+/* 66 */
+#define TEGRA124_CLK_I2C3 67
+#define TEGRA124_CLK_SBC4 68
+#define TEGRA124_CLK_SDMMC3 69
+#define TEGRA124_CLK_PCIE 70
+#define TEGRA124_CLK_OWR 71
+#define TEGRA124_CLK_AFI 72
+#define TEGRA124_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA124_CLK_LA 76
+#define TEGRA124_CLK_TRACE 77
+#define TEGRA124_CLK_SOC_THERM 78
+#define TEGRA124_CLK_DTV 79
+/* 80 */
+#define TEGRA124_CLK_I2CSLOW 81
+#define TEGRA124_CLK_DSIB 82
+#define TEGRA124_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA124_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA124_CLK_MSENC 91
+#define TEGRA124_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA124_CLK_MSELECT 99
+#define TEGRA124_CLK_TSENSOR 100
+#define TEGRA124_CLK_I2S3 101
+#define TEGRA124_CLK_I2S4 102
+#define TEGRA124_CLK_I2C4 103
+#define TEGRA124_CLK_SBC5 104
+#define TEGRA124_CLK_SBC6 105
+#define TEGRA124_CLK_D_AUDIO 106
+#define TEGRA124_CLK_APBIF 107
+#define TEGRA124_CLK_DAM0 108
+#define TEGRA124_CLK_DAM1 109
+#define TEGRA124_CLK_DAM2 110
+#define TEGRA124_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA124_CLK_AUDIO0_2X 113
+#define TEGRA124_CLK_AUDIO1_2X 114
+#define TEGRA124_CLK_AUDIO2_2X 115
+#define TEGRA124_CLK_AUDIO3_2X 116
+#define TEGRA124_CLK_AUDIO4_2X 117
+#define TEGRA124_CLK_SPDIF_2X 118
+#define TEGRA124_CLK_ACTMON 119
+#define TEGRA124_CLK_EXTERN1 120
+#define TEGRA124_CLK_EXTERN2 121
+#define TEGRA124_CLK_EXTERN3 122
+#define TEGRA124_CLK_SATA_OOB 123
+#define TEGRA124_CLK_SATA 124
+#define TEGRA124_CLK_HDA 125
+/* 126 */
+#define TEGRA124_CLK_SE 127
+
+#define TEGRA124_CLK_HDA2HDMI 128
+#define TEGRA124_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/*      xusb_host_src and xusb_ss_src) */
+#define TEGRA124_CLK_CILAB 144
+#define TEGRA124_CLK_CILCD 145
+#define TEGRA124_CLK_CILE 146
+#define TEGRA124_CLK_DSIALP 147
+#define TEGRA124_CLK_DSIBLP 148
+#define TEGRA124_CLK_ENTROPY 149
+#define TEGRA124_CLK_DDS 150
+/* 151 */
+#define TEGRA124_CLK_DP2 152
+#define TEGRA124_CLK_AMX 153
+#define TEGRA124_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA124_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+#define TEGRA124_CLK_I2C6 166
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+#define TEGRA124_CLK_VIM2_CLK 171
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+#define TEGRA124_CLK_HDMI_AUDIO 176
+#define TEGRA124_CLK_CLK72MHZ 177
+#define TEGRA124_CLK_VIC03 178
+/* 179 */
+#define TEGRA124_CLK_ADX1 180
+#define TEGRA124_CLK_DPAUX 181
+#define TEGRA124_CLK_SOR0 182
+/* 183 */
+#define TEGRA124_CLK_GPU 184
+#define TEGRA124_CLK_AMX1 185
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+#define TEGRA124_CLK_UARTB 192
+#define TEGRA124_CLK_VFIR 193
+#define TEGRA124_CLK_SPDIF_IN 194
+#define TEGRA124_CLK_SPDIF_OUT 195
+#define TEGRA124_CLK_VI 196
+#define TEGRA124_CLK_VI_SENSOR 197
+#define TEGRA124_CLK_FUSE 198
+#define TEGRA124_CLK_FUSE_BURN 199
+#define TEGRA124_CLK_CLK_32K 200
+#define TEGRA124_CLK_CLK_M 201
+#define TEGRA124_CLK_CLK_M_DIV2 202
+#define TEGRA124_CLK_CLK_M_DIV4 203
+#define TEGRA124_CLK_PLL_REF 204
+#define TEGRA124_CLK_PLL_C 205
+#define TEGRA124_CLK_PLL_C_OUT1 206
+#define TEGRA124_CLK_PLL_C2 207
+#define TEGRA124_CLK_PLL_C3 208
+#define TEGRA124_CLK_PLL_M 209
+#define TEGRA124_CLK_PLL_M_OUT1 210
+#define TEGRA124_CLK_PLL_P 211
+#define TEGRA124_CLK_PLL_P_OUT1 212
+#define TEGRA124_CLK_PLL_P_OUT2 213
+#define TEGRA124_CLK_PLL_P_OUT3 214
+#define TEGRA124_CLK_PLL_P_OUT4 215
+#define TEGRA124_CLK_PLL_A 216
+#define TEGRA124_CLK_PLL_A_OUT0 217
+#define TEGRA124_CLK_PLL_D 218
+#define TEGRA124_CLK_PLL_D_OUT0 219
+#define TEGRA124_CLK_PLL_D2 220
+#define TEGRA124_CLK_PLL_D2_OUT0 221
+#define TEGRA124_CLK_PLL_U 222
+#define TEGRA124_CLK_PLL_U_480M 223
+
+#define TEGRA124_CLK_PLL_U_60M 224
+#define TEGRA124_CLK_PLL_U_48M 225
+#define TEGRA124_CLK_PLL_U_12M 226
+/* 227 */
+/* 228 */
+#define TEGRA124_CLK_PLL_RE_VCO 229
+#define TEGRA124_CLK_PLL_RE_OUT 230
+#define TEGRA124_CLK_PLL_E 231
+#define TEGRA124_CLK_SPDIF_IN_SYNC 232
+#define TEGRA124_CLK_I2S0_SYNC 233
+#define TEGRA124_CLK_I2S1_SYNC 234
+#define TEGRA124_CLK_I2S2_SYNC 235
+#define TEGRA124_CLK_I2S3_SYNC 236
+#define TEGRA124_CLK_I2S4_SYNC 237
+#define TEGRA124_CLK_VIMCLK_SYNC 238
+#define TEGRA124_CLK_AUDIO0 239
+#define TEGRA124_CLK_AUDIO1 240
+#define TEGRA124_CLK_AUDIO2 241
+#define TEGRA124_CLK_AUDIO3 242
+#define TEGRA124_CLK_AUDIO4 243
+#define TEGRA124_CLK_SPDIF 244
+#define TEGRA124_CLK_CLK_OUT_1 245
+#define TEGRA124_CLK_CLK_OUT_2 246
+#define TEGRA124_CLK_CLK_OUT_3 247
+#define TEGRA124_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA124_CLK_XUSB_HOST_SRC 252
+#define TEGRA124_CLK_XUSB_FALCON_SRC 253
+#define TEGRA124_CLK_XUSB_FS_SRC 254
+#define TEGRA124_CLK_XUSB_SS_SRC 255
+
+#define TEGRA124_CLK_XUSB_DEV_SRC 256
+#define TEGRA124_CLK_XUSB_DEV 257
+#define TEGRA124_CLK_XUSB_HS_SRC 258
+#define TEGRA124_CLK_SCLK 259
+#define TEGRA124_CLK_HCLK 260
+#define TEGRA124_CLK_PCLK 261
+/* 262 */
+/* 263 */
+#define TEGRA124_CLK_DFLL_REF 264
+#define TEGRA124_CLK_DFLL_SOC 265
+#define TEGRA124_CLK_VI_SENSOR2 266
+#define TEGRA124_CLK_PLL_P_OUT5 267
+#define TEGRA124_CLK_CML0 268
+#define TEGRA124_CLK_CML1 269
+#define TEGRA124_CLK_PLL_C4 270
+#define TEGRA124_CLK_PLL_DP 271
+#define TEGRA124_CLK_PLL_E_MUX 272
+/* 273 */
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA124_CLK_AUDIO0_MUX 300
+#define TEGRA124_CLK_AUDIO1_MUX 301
+#define TEGRA124_CLK_AUDIO2_MUX 302
+#define TEGRA124_CLK_AUDIO3_MUX 303
+#define TEGRA124_CLK_AUDIO4_MUX 304
+#define TEGRA124_CLK_SPDIF_MUX 305
+#define TEGRA124_CLK_CLK_OUT_1_MUX 306
+#define TEGRA124_CLK_CLK_OUT_2_MUX 307
+#define TEGRA124_CLK_CLK_OUT_3_MUX 308
+#define TEGRA124_CLK_DSIA_MUX 309
+#define TEGRA124_CLK_DSIB_MUX 310
+#define TEGRA124_CLK_SOR0_LVDS 311
+#define TEGRA124_CLK_XUSB_SS_DIV2 312
+
+#define TEGRA124_CLK_PLL_M_UD 313
+#define TEGRA124_CLK_PLL_C_UD 314
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
include/dt-bindings/clock/tegra124-car.h +9 -336

355 lines not on this page · raw message

author
#4 lore raw

PATCH 3/4 clk: tegra: Update binding doc for Tegra132

In reply to Paul Walmsley

From: Peter De Schrijver <[email protected]>

Tegra132 has almost the same clock structure than Tegra124. This patch documents the missing clock IDs.

Signed-off-by Peter De Schrijver <[email protected]>

[paul at pwsan.com: updated binding documentation to reflect the recent
split of Tegra124 clock IDs into a Tegra124/132-common file and a Tegra124-specific file]

Signed-off-by Paul Walmsley <[email protected]>
Signed-off-by Paul Walmsley <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Thierry Reding <[email protected]>
Cc Alexandre Courbot <[email protected]>
Cc Rob Herring <[email protected]>
Cc Pawel Moll <[email protected]>
Cc Mark Rutland <[email protected]>
Cc Ian Campbell <[email protected]>
Cc Kumar Gala <[email protected]>
---
 .../bindings/clock/nvidia,tegra124-car.txt         |   10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +6 -4
index ded5d62..c6620bc 100644
@@ -1,4 +1,4 @@
-NVIDIA Tegra124 Clock And Reset Controller
+NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
 
 This binding uses the common clock binding:
 Documentation/devicetree/bindings/clock/clock-bindings.txt

@@ -7,14 +7,16 @@ The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
 for muxing and gating Tegra's clocks, and setting their rates.
 
 Required properties :
-- compatible : Should be "nvidia,tegra124-car"
+- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
 - reg : Should contain CAR registers location and length
 - clocks : Should contain phandle and clock specifiers for two clocks:
   the 32 KHz "32k_in", and the board-specific oscillator "osc".
 - #clock-cells : Should be 1.
   In clock consumers, this cell represents the clock ID exposed by the
-  CAR. The assignments may be found in header file
-  <dt-bindings/clock/tegra124-car.h>.
+  CAR. The assignments may be found in the header files
+  <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
+  to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
+  (for Tegra124-specific clocks).
 - #reset-cells : Should be 1.
   In clock consumers, this cell represents the bit number in the CAR's
   array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
author
#5 lore raw

PATCH 4/4 clk: tegra: Add support for the Tegra132 CAR IP block

In reply to Paul Walmsley

From: Paul Walmsley <[email protected]>

Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This patch mostly deals with the small differences.

Since Tegra132 contains many of the same PLL clock sources used on Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when the kernel is configured to include Tegra132 support.

This patch is based on several patches from others:

1. a patch from Peter De Schrijver:

http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html

2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and

3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132").

Signed-off-by Paul Walmsley <[email protected]>
Signed-off-by Paul Walmsley <[email protected]>
Cc Peter De Schrijver <[email protected]>
Cc Allen Martin <[email protected]>
Cc Prashant Gaikwad <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Thierry Reding <[email protected]>
Cc Alexandre Courbot <[email protected]>
Cc Bill Huang <[email protected]>
Cc Mike Turquette <[email protected]>
Cc Stephen Boyd <[email protected]>
---
 drivers/clk/tegra/Makefile       |    1 
 drivers/clk/tegra/clk-pll.c      |   10 ++-
 drivers/clk/tegra/clk-tegra124.c |  130 +++++++++++++++++++++++++++++++++++---
 3 files changed, 129 insertions(+), 12 deletions(-)
drivers/clk/tegra/Makefile +1 -0
index f7dfb72..edb8358 100644
@@ -15,3 +15,4 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o
 obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124.o
+obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
drivers/clk/tegra/clk-pll.c +7 -3
index c7c6d8f..a04e584 100644
@@ -816,7 +816,9 @@ const struct clk_ops tegra_clk_plle_ops = {
 	.enable = clk_plle_enable,
 };
 
-#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
+#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
+	defined(CONFIG_ARCH_TEGRA_124_SOC) || \
+	defined(CONFIG_ARCH_TEGRA_132_SOC)
 
 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
 			   unsigned long parent_rate)

@@ -1505,7 +1507,9 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
 	return clk;
 }
 
-#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
+#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
+	defined(CONFIG_ARCH_TEGRA_124_SOC) || \
+	defined(CONFIG_ARCH_TEGRA_132_SOC)
 static const struct clk_ops tegra_clk_pllxc_ops = {
 	.is_enabled = clk_pll_is_enabled,
 	.enable = clk_pll_iddq_enable,

@@ -1802,7 +1806,7 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
 }
 #endif
 
-#ifdef CONFIG_ARCH_TEGRA_124_SOC
+#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
 static const struct clk_ops tegra_clk_pllss_ops = {
 	.is_enabled = clk_pll_is_enabled,
 	.enable = clk_pll_iddq_enable,
drivers/clk/tegra/clk-tegra124.c +121 -9

187 lines not on this page · raw message

#6 lore raw

Re: [PATCH 4/4] clk: tegra: Add support for the Tegra132 CAR IP block

Quoted 13 lines · Paul Walmsley

From: Paul Walmsley <[email protected]>

Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This patch mostly deals with the small differences.

Since Tegra132 contains many of the same PLL clock sources used on Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when the kernel is configured to include Tegra132 support.

This patch is based on several patches from others:

1. a patch from Peter De Schrijver:

Quoted 7 lines

http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html

2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and

3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132").

Doesn't this technically require Signed-off-bys from each of the above, then?

Quoted 1 line
drivers/clk/tegra/clk-tegra124.c +0 -0

[...]

drivers/clk/tegra/clk-tegra124.c static struct tegra_clk_init_table init_table[] __initdata = { · line 1455

Quoted 11 lines
drivers/clk/tegra/clk-tegra124.c +11 -0
+/**
+ * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
+ * @np: struct device_node * of the DT node for the SoC CAR IP block
+ *
+ * Register most of the clocks controlled by the CAR IP block, along
+ * with a few clocks controlled by the PMC IP block.  Everything in
+ * this function should be common to Tegra124 and Tegra132.  XXX The
+ * PMC clock initialization should probably be moved to PMC-specific
+ * driver code.  No return value.
+ */
+static void __init tegra124_132_clock_init_pre(struct device_node *np)

I would've personally named this tegra124_clock_init_pre(). In the past we've named these functions after the first chip that needed them and if later chips remained compatible they would simply use the one from an earlier chip. That's consistent with the naming of compatible strings and doesn't require changes to the function names if yet another SoC generation were to need the same functionality.

Thierry
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author
#7 lore raw

Re: [PATCH 4/4] clk: tegra: Add support for the Tegra132 CAR IP block

Hi Thierry

Quoted 8 lines · Thierry Reding
Quoted 7 lines · Paul Walmsley

This patch is based on several patches from others:

1. a patch from Peter De Schrijver:

http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html

Quoted 8 lines
Quoted 5 lines

2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and

3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132").

Doesn't this technically require Signed-off-bys from each of the above, then?

I don't think so. Documentation/SubmittingPatches states:

---
The rules are pretty simple: if you can certify the below:

Developer's Certificate of Origin 1.1

By making a contribution to this project, I certify that:

(a) The contribution was created in whole or in part by me and I have the right to submit it under the open source license indicated in the file; or

(b) The contribution is based upon previous work that, to the best of my knowledge, is covered under an appropriate open source license and I have the right under that license to submit that work with modifications, whether created in whole or in part by me, under the same open source license (unless I am permitted to submit under a different license), as indicated in the file; or

(c) The contribution was provided directly to me by some other person who certified (a), (b) or (c) and I have not modified it.

(d) I understand and agree that this project and the contribution are public and that a record of the contribution (including all personal information I submit with it, including my sign-off) is maintained indefinitely and may be redistributed consistent with this project or the open source license(s) involved.
---

My Signed-off-by: is based on paragraphs (a), (b), and (d).

The intention of my statement is to ensure that credit is appropriately provided to everyone who I drew significant inspiration or code from, and that such credit makes it into the official commits (e.g., is not dropped when the patches are applied.) However, the patch that I sent is differs from the patches that I reviewed while preparing it.

Of course, if anyone would like to add Acked-by or Reviewed-by tags, etc., or comment if I've misunderstood something technically etc., that's definitely welcome.

Quoted 12 lines
Quoted 1 line
drivers/clk/tegra/clk-tegra124.c +0 -0

[...]

Quoted 10 lines

+/**
+ * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
+ * @np: struct device_node * of the DT node for the SoC CAR IP block
+ *
+ * Register most of the clocks controlled by the CAR IP block, along
+ * with a few clocks controlled by the PMC IP block. Everything in
+ * this function should be common to Tegra124 and Tegra132. XXX The
+ * PMC clock initialization should probably be moved to PMC-specific
+ * driver code. No return value.
+ */

Quoted 8 lines
Quoted 1 line

+static void __init tegra124_132_clock_init_pre(struct device_node *np)

I would've personally named this tegra124_clock_init_pre(). In the past we've named these functions after the first chip that needed them and if later chips remained compatible they would simply use the one from an earlier chip. That's consistent with the naming of compatible strings and doesn't require changes to the function names if yet another SoC generation were to need the same functionality.

Yes, I agree it's unwieldy. It would be nice to find some concise way to refer to "the family of NVIDIA SoCs that includes T124 and T132". Maybe tegra124_family_clock_init_pre() might be a better choice...

- Paul

#8 lore raw

Re: [PATCH 4/4] clk: tegra: Add support for the Tegra132 CAR IP block

Quoted 15 lines · Paul Walmsley

Hi Thierry

Quoted 11 lines · Thierry Reding
Quoted 10 lines · Paul Walmsley

This patch is based on several patches from others:

1. a patch from Peter De Schrijver:

http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html

2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and

Quoted 7 lines
Quoted 5 lines
Quoted 2 lines

3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132").

Doesn't this technically require Signed-off-bys from each of the above, then?

I don't think so. Documentation/SubmittingPatches states:

It's certainly been deemed acceptable in the past, if admittedly not optimal, for the person who is the "exit point" of an organization/company for the patch to be the only person to sign it off. The reason being they're vouching that the Certificate of Origin applies to all the company-sponsored work internal to the organization.

author
#9 lore raw

Re: [PATCH 4/4] clk: tegra: Add support for the Tegra132 CAR IP block

Quoted 22 lines · Stephen Warren
Quoted 21 lines · Paul Walmsley

Hi Thierry

Quoted 16 lines · Thierry Reding
Quoted 5 lines · Paul Walmsley

This patch is based on several patches from others:

1. a patch from Peter De Schrijver:

Quoted 7 lines

http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html

2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and

3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132").

Doesn't this technically require Signed-off-bys from each of the above, then?

Quoted 7 lines
Quoted 1 line

I don't think so. Documentation/SubmittingPatches states:

It's certainly been deemed acceptable in the past, if admittedly not optimal, for the person who is the "exit point" of an organization/company for the patch to be the only person to sign it off. The reason being they're vouching that the Certificate of Origin applies to all the company-sponsored work internal to the organization.

I'm not even sure that applies to this patch. If I were passing along a verbatim copy of someone else's patch, or a copy with minor modifications, then it definitely be appropriate and expected to pass along their Signed-off-by:. But this patch is original work; it's not a verbatim copy of any of the patches that I mention above (which are all publicly available, incidentally).

- Paul

Acked-by on the v1 series
#10 lore raw
In reply to Paul Walmsley
Quoted 16 lines · Paul Walmsley

This series follows up on Peter De Schrijver's posting of a Tegra132 CAR series in July of this year. It adds common clock framework support for the Tegra132 CAR IP block.

The patches are based on next-20141209 and have been compiled and boot-tested on a Tegra30 Beaver board, a Tegra114 Dalmore board, and a Tegra124 Jetson TK1. They've also been tested on a Tegra132 Norrin FFD board, with some other patches applied since support for that board isn't completely upstream (but is coming shortly).

Intended for v3.20.

- Paul

---

Quoted 7 lines

Paul Walmsley (2):
clk: tegra: split Tegra124 clock header file
clk: tegra: Add support for the Tegra132 CAR IP block

Peter De Schrijver (2):
clk: tegra: make tegra_clocks_apply_init_table() arch_initcall
clk: tegra: Update binding doc for Tegra132

Peter, you've collected clock patches in a separate branch in the past and sent off pull requests to Mike. Are you going to pick up these patches, too?

With the comments on patch 4/4 addressed, the series:

Acked-by Thierry Reding <[email protected]>

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